Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10026693 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
149 |
| auto[1] |
7683025 |
1 |
|
|
T24 |
217 |
|
T1 |
37942 |
|
T11 |
984 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16721641 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
356 |
| auto[1] |
988077 |
1 |
|
|
T24 |
10 |
|
T1 |
5059 |
|
T11 |
42 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10021046 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
150 |
| auto[1] |
7688672 |
1 |
|
|
T24 |
216 |
|
T1 |
41024 |
|
T11 |
1101 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3340608 |
1 |
|
|
T24 |
95 |
|
T1 |
18283 |
|
T11 |
564 |
| auto[1] |
auto[0] |
auto[1] |
491720 |
1 |
|
|
T24 |
3 |
|
T1 |
2587 |
|
T11 |
25 |
| auto[1] |
auto[1] |
auto[0] |
3359987 |
1 |
|
|
T24 |
111 |
|
T1 |
17682 |
|
T11 |
495 |
| auto[1] |
auto[1] |
auto[1] |
496357 |
1 |
|
|
T24 |
7 |
|
T1 |
2472 |
|
T11 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |