Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10007893 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
149 |
| auto[1] |
7701825 |
1 |
|
|
T24 |
217 |
|
T1 |
38358 |
|
T11 |
1000 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16719499 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
353 |
| auto[1] |
990219 |
1 |
|
|
T24 |
13 |
|
T1 |
4617 |
|
T11 |
39 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10011793 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
174 |
| auto[1] |
7697925 |
1 |
|
|
T24 |
192 |
|
T1 |
38609 |
|
T11 |
1091 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3367888 |
1 |
|
|
T24 |
73 |
|
T1 |
17588 |
|
T11 |
468 |
| auto[1] |
auto[0] |
auto[1] |
497534 |
1 |
|
|
T24 |
5 |
|
T1 |
2449 |
|
T11 |
19 |
| auto[1] |
auto[1] |
auto[0] |
3339818 |
1 |
|
|
T24 |
106 |
|
T1 |
16404 |
|
T11 |
584 |
| auto[1] |
auto[1] |
auto[1] |
492685 |
1 |
|
|
T24 |
8 |
|
T1 |
2168 |
|
T11 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |