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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 946
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T93 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.892304864 Jul 10 04:49:00 PM PDT 24 Jul 10 04:49:03 PM PDT 24 71929657 ps
T765 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3502940219 Jul 10 04:49:45 PM PDT 24 Jul 10 04:49:48 PM PDT 24 50504426 ps
T46 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1819880782 Jul 10 04:49:46 PM PDT 24 Jul 10 04:49:49 PM PDT 24 327814833 ps
T766 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1481200853 Jul 10 04:49:44 PM PDT 24 Jul 10 04:49:47 PM PDT 24 45553952 ps
T767 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.482473264 Jul 10 04:49:41 PM PDT 24 Jul 10 04:49:44 PM PDT 24 100930256 ps
T47 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3591801841 Jul 10 04:49:06 PM PDT 24 Jul 10 04:49:08 PM PDT 24 493017065 ps
T768 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2666707388 Jul 10 04:49:00 PM PDT 24 Jul 10 04:49:01 PM PDT 24 35193770 ps
T769 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1439246947 Jul 10 04:49:21 PM PDT 24 Jul 10 04:49:24 PM PDT 24 87942016 ps
T104 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1298139294 Jul 10 04:49:37 PM PDT 24 Jul 10 04:49:39 PM PDT 24 20610039 ps
T770 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3522235065 Jul 10 04:49:44 PM PDT 24 Jul 10 04:49:46 PM PDT 24 627862360 ps
T771 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2581023132 Jul 10 04:49:46 PM PDT 24 Jul 10 04:49:49 PM PDT 24 42243192 ps
T97 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1412277932 Jul 10 04:49:45 PM PDT 24 Jul 10 04:49:48 PM PDT 24 76263751 ps
T772 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1610157971 Jul 10 04:49:19 PM PDT 24 Jul 10 04:49:23 PM PDT 24 268715538 ps
T773 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3335637441 Jul 10 04:49:07 PM PDT 24 Jul 10 04:49:09 PM PDT 24 21685026 ps
T774 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2323122687 Jul 10 04:49:52 PM PDT 24 Jul 10 04:49:54 PM PDT 24 30477536 ps
T775 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3561411685 Jul 10 04:49:53 PM PDT 24 Jul 10 04:49:57 PM PDT 24 51586059 ps
T776 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3589801962 Jul 10 04:49:12 PM PDT 24 Jul 10 04:49:14 PM PDT 24 20714731 ps
T105 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2169153364 Jul 10 04:49:38 PM PDT 24 Jul 10 04:49:41 PM PDT 24 34633358 ps
T41 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3749264901 Jul 10 04:49:45 PM PDT 24 Jul 10 04:49:48 PM PDT 24 121599383 ps
T777 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2269117175 Jul 10 04:49:44 PM PDT 24 Jul 10 04:49:47 PM PDT 24 125489008 ps
T778 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.766352323 Jul 10 04:49:14 PM PDT 24 Jul 10 04:49:15 PM PDT 24 95679421 ps
T779 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1066432373 Jul 10 04:49:25 PM PDT 24 Jul 10 04:49:27 PM PDT 24 63955673 ps
T780 /workspace/coverage/cover_reg_top/39.gpio_intr_test.2106181269 Jul 10 04:49:56 PM PDT 24 Jul 10 04:49:58 PM PDT 24 26678251 ps
T781 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3072654678 Jul 10 04:49:32 PM PDT 24 Jul 10 04:49:35 PM PDT 24 76401349 ps
T782 /workspace/coverage/cover_reg_top/17.gpio_intr_test.3493271109 Jul 10 04:49:44 PM PDT 24 Jul 10 04:49:47 PM PDT 24 11789062 ps
T783 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2873238536 Jul 10 04:49:09 PM PDT 24 Jul 10 04:49:10 PM PDT 24 66530487 ps
T94 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2418140602 Jul 10 04:49:43 PM PDT 24 Jul 10 04:49:44 PM PDT 24 46603142 ps
T784 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2757067147 Jul 10 04:49:01 PM PDT 24 Jul 10 04:49:04 PM PDT 24 653201411 ps
T42 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1033095991 Jul 10 04:49:31 PM PDT 24 Jul 10 04:49:33 PM PDT 24 429164922 ps
T785 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1147327942 Jul 10 04:49:31 PM PDT 24 Jul 10 04:49:34 PM PDT 24 192547041 ps
T786 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.381493267 Jul 10 04:49:33 PM PDT 24 Jul 10 04:49:35 PM PDT 24 33873218 ps
T787 /workspace/coverage/cover_reg_top/27.gpio_intr_test.1203771396 Jul 10 04:49:53 PM PDT 24 Jul 10 04:49:55 PM PDT 24 24382612 ps
T788 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.594107412 Jul 10 04:49:05 PM PDT 24 Jul 10 04:49:07 PM PDT 24 78256526 ps
T789 /workspace/coverage/cover_reg_top/9.gpio_intr_test.2278484937 Jul 10 04:49:30 PM PDT 24 Jul 10 04:49:31 PM PDT 24 64535097 ps
T790 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.87881316 Jul 10 04:49:19 PM PDT 24 Jul 10 04:49:21 PM PDT 24 11505154 ps
T791 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.640514475 Jul 10 04:49:27 PM PDT 24 Jul 10 04:49:29 PM PDT 24 135885012 ps
T792 /workspace/coverage/cover_reg_top/18.gpio_intr_test.667745805 Jul 10 04:49:51 PM PDT 24 Jul 10 04:49:53 PM PDT 24 86830224 ps
T793 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.814469842 Jul 10 04:49:51 PM PDT 24 Jul 10 04:49:53 PM PDT 24 121029977 ps
T794 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.309214302 Jul 10 04:49:47 PM PDT 24 Jul 10 04:49:49 PM PDT 24 22413170 ps
T795 /workspace/coverage/cover_reg_top/20.gpio_intr_test.2304498672 Jul 10 04:49:50 PM PDT 24 Jul 10 04:49:52 PM PDT 24 17033810 ps
T796 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2210445852 Jul 10 04:49:51 PM PDT 24 Jul 10 04:49:53 PM PDT 24 14625470 ps
T797 /workspace/coverage/cover_reg_top/33.gpio_intr_test.680409228 Jul 10 04:49:58 PM PDT 24 Jul 10 04:50:00 PM PDT 24 25275884 ps
T798 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1461375547 Jul 10 04:49:12 PM PDT 24 Jul 10 04:49:15 PM PDT 24 877586485 ps
T799 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3266320086 Jul 10 04:49:20 PM PDT 24 Jul 10 04:49:22 PM PDT 24 65017849 ps
T800 /workspace/coverage/cover_reg_top/46.gpio_intr_test.14923914 Jul 10 04:49:57 PM PDT 24 Jul 10 04:49:59 PM PDT 24 15431369 ps
T801 /workspace/coverage/cover_reg_top/34.gpio_intr_test.1311590103 Jul 10 04:49:59 PM PDT 24 Jul 10 04:50:01 PM PDT 24 60011753 ps
T802 /workspace/coverage/cover_reg_top/14.gpio_intr_test.4178258075 Jul 10 04:49:43 PM PDT 24 Jul 10 04:49:45 PM PDT 24 21292052 ps
T803 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2301493145 Jul 10 04:49:14 PM PDT 24 Jul 10 04:49:15 PM PDT 24 54279781 ps
T804 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2738085243 Jul 10 04:49:45 PM PDT 24 Jul 10 04:49:47 PM PDT 24 99338458 ps
T805 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1766034331 Jul 10 04:49:47 PM PDT 24 Jul 10 04:49:50 PM PDT 24 68718876 ps
T806 /workspace/coverage/cover_reg_top/40.gpio_intr_test.1268177344 Jul 10 04:49:55 PM PDT 24 Jul 10 04:49:57 PM PDT 24 49071132 ps
T807 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.4109236184 Jul 10 04:49:02 PM PDT 24 Jul 10 04:49:04 PM PDT 24 24163607 ps
T808 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3268061690 Jul 10 04:49:44 PM PDT 24 Jul 10 04:49:49 PM PDT 24 1156901407 ps
T809 /workspace/coverage/cover_reg_top/16.gpio_intr_test.2891269952 Jul 10 04:49:45 PM PDT 24 Jul 10 04:49:47 PM PDT 24 38353260 ps
T810 /workspace/coverage/cover_reg_top/30.gpio_intr_test.286058381 Jul 10 04:49:52 PM PDT 24 Jul 10 04:49:54 PM PDT 24 36380552 ps
T811 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3524341219 Jul 10 04:49:31 PM PDT 24 Jul 10 04:49:33 PM PDT 24 47223475 ps
T812 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3236023325 Jul 10 04:49:44 PM PDT 24 Jul 10 04:49:46 PM PDT 24 20854864 ps
T98 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.648241538 Jul 10 04:49:25 PM PDT 24 Jul 10 04:49:27 PM PDT 24 15208021 ps
T813 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1075758210 Jul 10 04:49:33 PM PDT 24 Jul 10 04:49:35 PM PDT 24 65887524 ps
T814 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1853582929 Jul 10 04:49:38 PM PDT 24 Jul 10 04:49:42 PM PDT 24 103731656 ps
T815 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1819394231 Jul 10 04:49:01 PM PDT 24 Jul 10 04:49:03 PM PDT 24 23077780 ps
T816 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3707841080 Jul 10 04:49:50 PM PDT 24 Jul 10 04:49:52 PM PDT 24 157903161 ps
T817 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.928746711 Jul 10 04:49:26 PM PDT 24 Jul 10 04:49:28 PM PDT 24 72342273 ps
T818 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3100587705 Jul 10 04:49:18 PM PDT 24 Jul 10 04:49:22 PM PDT 24 172449084 ps
T95 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1820559780 Jul 10 04:49:32 PM PDT 24 Jul 10 04:49:34 PM PDT 24 47536334 ps
T819 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.4083629410 Jul 10 04:48:55 PM PDT 24 Jul 10 04:48:58 PM PDT 24 23853879 ps
T96 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1010819347 Jul 10 04:49:07 PM PDT 24 Jul 10 04:49:09 PM PDT 24 133501141 ps
T820 /workspace/coverage/cover_reg_top/35.gpio_intr_test.2918203513 Jul 10 04:50:01 PM PDT 24 Jul 10 04:50:03 PM PDT 24 49378240 ps
T821 /workspace/coverage/cover_reg_top/37.gpio_intr_test.3099939175 Jul 10 04:49:55 PM PDT 24 Jul 10 04:49:57 PM PDT 24 30019980 ps
T822 /workspace/coverage/cover_reg_top/21.gpio_intr_test.425973432 Jul 10 04:49:51 PM PDT 24 Jul 10 04:49:53 PM PDT 24 18369552 ps
T823 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3505278127 Jul 10 04:49:18 PM PDT 24 Jul 10 04:49:20 PM PDT 24 15216505 ps
T824 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3389508223 Jul 10 04:49:19 PM PDT 24 Jul 10 04:49:21 PM PDT 24 43592202 ps
T825 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3288959030 Jul 10 04:49:52 PM PDT 24 Jul 10 04:49:55 PM PDT 24 141444194 ps
T826 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1983162385 Jul 10 04:49:55 PM PDT 24 Jul 10 04:49:56 PM PDT 24 45269896 ps
T99 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3620673684 Jul 10 04:49:35 PM PDT 24 Jul 10 04:49:36 PM PDT 24 42034280 ps
T827 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1791235737 Jul 10 04:49:40 PM PDT 24 Jul 10 04:49:41 PM PDT 24 18141418 ps
T828 /workspace/coverage/cover_reg_top/15.gpio_intr_test.32909712 Jul 10 04:49:46 PM PDT 24 Jul 10 04:49:48 PM PDT 24 41252259 ps
T829 /workspace/coverage/cover_reg_top/10.gpio_intr_test.3233258204 Jul 10 04:49:32 PM PDT 24 Jul 10 04:49:34 PM PDT 24 31209041 ps
T830 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2259764045 Jul 10 04:49:31 PM PDT 24 Jul 10 04:49:36 PM PDT 24 1451711948 ps
T831 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2043049193 Jul 10 04:49:11 PM PDT 24 Jul 10 04:49:12 PM PDT 24 47663330 ps
T832 /workspace/coverage/cover_reg_top/4.gpio_intr_test.426667877 Jul 10 04:49:18 PM PDT 24 Jul 10 04:49:19 PM PDT 24 37428531 ps
T833 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3777102289 Jul 10 04:49:38 PM PDT 24 Jul 10 04:49:40 PM PDT 24 13593714 ps
T834 /workspace/coverage/cover_reg_top/1.gpio_intr_test.1664347636 Jul 10 04:49:01 PM PDT 24 Jul 10 04:49:03 PM PDT 24 34261625 ps
T835 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1711361460 Jul 10 04:49:44 PM PDT 24 Jul 10 04:49:47 PM PDT 24 18567350 ps
T836 /workspace/coverage/cover_reg_top/7.gpio_intr_test.2956317595 Jul 10 04:49:25 PM PDT 24 Jul 10 04:49:27 PM PDT 24 15082684 ps
T837 /workspace/coverage/cover_reg_top/6.gpio_intr_test.785073707 Jul 10 04:49:25 PM PDT 24 Jul 10 04:49:26 PM PDT 24 16135342 ps
T838 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.284343080 Jul 10 04:49:06 PM PDT 24 Jul 10 04:49:10 PM PDT 24 260490779 ps
T839 /workspace/coverage/cover_reg_top/0.gpio_intr_test.1867190908 Jul 10 04:49:02 PM PDT 24 Jul 10 04:49:04 PM PDT 24 61499700 ps
T45 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.251908140 Jul 10 04:49:01 PM PDT 24 Jul 10 04:49:04 PM PDT 24 74461075 ps
T840 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3875855828 Jul 10 04:49:42 PM PDT 24 Jul 10 04:49:43 PM PDT 24 35442146 ps
T841 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.453875414 Jul 10 04:49:32 PM PDT 24 Jul 10 04:49:36 PM PDT 24 145190990 ps
T842 /workspace/coverage/cover_reg_top/28.gpio_intr_test.4054222790 Jul 10 04:49:51 PM PDT 24 Jul 10 04:49:53 PM PDT 24 25361655 ps
T843 /workspace/coverage/cover_reg_top/49.gpio_intr_test.3906675052 Jul 10 04:50:03 PM PDT 24 Jul 10 04:50:05 PM PDT 24 31693196 ps
T844 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.4141492057 Jul 10 04:49:25 PM PDT 24 Jul 10 04:49:27 PM PDT 24 75261126 ps
T845 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3158076688 Jul 10 04:49:28 PM PDT 24 Jul 10 04:49:29 PM PDT 24 36767408 ps
T846 /workspace/coverage/cover_reg_top/48.gpio_intr_test.2685907105 Jul 10 04:50:03 PM PDT 24 Jul 10 04:50:05 PM PDT 24 167260559 ps
T847 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1393543090 Jul 10 04:50:26 PM PDT 24 Jul 10 04:50:28 PM PDT 24 202676706 ps
T848 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1662826493 Jul 10 04:50:32 PM PDT 24 Jul 10 04:50:35 PM PDT 24 23443225 ps
T849 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1620599804 Jul 10 04:50:15 PM PDT 24 Jul 10 04:50:17 PM PDT 24 65097277 ps
T850 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2971691403 Jul 10 04:50:34 PM PDT 24 Jul 10 04:50:38 PM PDT 24 122165041 ps
T851 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.392688103 Jul 10 04:50:24 PM PDT 24 Jul 10 04:50:27 PM PDT 24 449564056 ps
T852 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2798097279 Jul 10 04:50:32 PM PDT 24 Jul 10 04:50:35 PM PDT 24 145235816 ps
T853 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3859980167 Jul 10 04:50:09 PM PDT 24 Jul 10 04:50:11 PM PDT 24 54435120 ps
T854 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1739575081 Jul 10 04:50:04 PM PDT 24 Jul 10 04:50:07 PM PDT 24 126009273 ps
T855 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.22100582 Jul 10 04:50:34 PM PDT 24 Jul 10 04:50:37 PM PDT 24 30005953 ps
T856 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1054255057 Jul 10 04:50:09 PM PDT 24 Jul 10 04:50:11 PM PDT 24 78318019 ps
T857 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2945092654 Jul 10 04:50:23 PM PDT 24 Jul 10 04:50:26 PM PDT 24 62315774 ps
T858 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1745466542 Jul 10 04:50:33 PM PDT 24 Jul 10 04:50:37 PM PDT 24 403290756 ps
T859 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1822461910 Jul 10 04:50:33 PM PDT 24 Jul 10 04:50:37 PM PDT 24 82754159 ps
T860 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1007419150 Jul 10 04:50:17 PM PDT 24 Jul 10 04:50:21 PM PDT 24 187931590 ps
T861 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3247759330 Jul 10 04:50:32 PM PDT 24 Jul 10 04:50:34 PM PDT 24 70782619 ps
T862 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1208534722 Jul 10 04:50:22 PM PDT 24 Jul 10 04:50:25 PM PDT 24 216906120 ps
T863 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1867160082 Jul 10 04:50:16 PM PDT 24 Jul 10 04:50:19 PM PDT 24 123973679 ps
T864 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.468158924 Jul 10 04:50:11 PM PDT 24 Jul 10 04:50:13 PM PDT 24 141105616 ps
T865 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.387520535 Jul 10 04:50:36 PM PDT 24 Jul 10 04:50:39 PM PDT 24 74097105 ps
T866 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.474021692 Jul 10 04:50:07 PM PDT 24 Jul 10 04:50:09 PM PDT 24 79863775 ps
T867 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.430631564 Jul 10 04:50:09 PM PDT 24 Jul 10 04:50:11 PM PDT 24 127621110 ps
T868 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1061059926 Jul 10 04:50:10 PM PDT 24 Jul 10 04:50:13 PM PDT 24 170156509 ps
T869 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1888857994 Jul 10 04:50:16 PM PDT 24 Jul 10 04:50:18 PM PDT 24 316731010 ps
T870 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2824298785 Jul 10 04:50:33 PM PDT 24 Jul 10 04:50:36 PM PDT 24 51138631 ps
T871 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4219176307 Jul 10 04:50:05 PM PDT 24 Jul 10 04:50:08 PM PDT 24 258306724 ps
T872 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.229328427 Jul 10 04:50:34 PM PDT 24 Jul 10 04:50:38 PM PDT 24 72014223 ps
T873 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2168000896 Jul 10 04:50:05 PM PDT 24 Jul 10 04:50:07 PM PDT 24 33831473 ps
T874 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.217244150 Jul 10 04:50:17 PM PDT 24 Jul 10 04:50:21 PM PDT 24 231664025 ps
T875 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2051449387 Jul 10 04:50:32 PM PDT 24 Jul 10 04:50:35 PM PDT 24 586315380 ps
T876 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.318363028 Jul 10 04:50:03 PM PDT 24 Jul 10 04:50:06 PM PDT 24 84972045 ps
T877 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.458412730 Jul 10 04:50:23 PM PDT 24 Jul 10 04:50:26 PM PDT 24 68953827 ps
T878 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2092265004 Jul 10 04:50:32 PM PDT 24 Jul 10 04:50:35 PM PDT 24 79232740 ps
T879 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.4107537097 Jul 10 04:50:11 PM PDT 24 Jul 10 04:50:13 PM PDT 24 37509596 ps
T880 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2237607165 Jul 10 04:50:18 PM PDT 24 Jul 10 04:50:22 PM PDT 24 45882640 ps
T881 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.585194211 Jul 10 04:50:18 PM PDT 24 Jul 10 04:50:22 PM PDT 24 265414779 ps
T882 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.895637678 Jul 10 04:50:12 PM PDT 24 Jul 10 04:50:14 PM PDT 24 127318914 ps
T883 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.175415163 Jul 10 04:50:23 PM PDT 24 Jul 10 04:50:27 PM PDT 24 160914821 ps
T884 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3993476369 Jul 10 04:50:16 PM PDT 24 Jul 10 04:50:17 PM PDT 24 41306234 ps
T885 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1168018878 Jul 10 04:50:17 PM PDT 24 Jul 10 04:50:21 PM PDT 24 119201491 ps
T886 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1519774661 Jul 10 04:50:07 PM PDT 24 Jul 10 04:50:09 PM PDT 24 70477808 ps
T887 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1069378426 Jul 10 04:50:03 PM PDT 24 Jul 10 04:50:06 PM PDT 24 921232864 ps
T888 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3220792102 Jul 10 04:50:23 PM PDT 24 Jul 10 04:50:26 PM PDT 24 143020000 ps
T889 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1602737192 Jul 10 04:50:15 PM PDT 24 Jul 10 04:50:18 PM PDT 24 75661002 ps
T890 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3412707033 Jul 10 04:50:18 PM PDT 24 Jul 10 04:50:23 PM PDT 24 325456159 ps
T891 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1935804238 Jul 10 04:50:22 PM PDT 24 Jul 10 04:50:26 PM PDT 24 116540572 ps
T892 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.153201426 Jul 10 04:50:17 PM PDT 24 Jul 10 04:50:21 PM PDT 24 26539708 ps
T893 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3766869720 Jul 10 04:50:16 PM PDT 24 Jul 10 04:50:18 PM PDT 24 65570896 ps
T894 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.418779975 Jul 10 04:50:05 PM PDT 24 Jul 10 04:50:08 PM PDT 24 112433773 ps
T895 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3846118554 Jul 10 04:50:04 PM PDT 24 Jul 10 04:50:07 PM PDT 24 58872145 ps
T896 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.460269114 Jul 10 04:50:33 PM PDT 24 Jul 10 04:50:37 PM PDT 24 61579891 ps
T897 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2015402619 Jul 10 04:50:24 PM PDT 24 Jul 10 04:50:27 PM PDT 24 352337412 ps
T898 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3453435024 Jul 10 04:50:17 PM PDT 24 Jul 10 04:50:19 PM PDT 24 59679052 ps
T899 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2409222792 Jul 10 04:50:22 PM PDT 24 Jul 10 04:50:25 PM PDT 24 79837970 ps
T900 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.744646875 Jul 10 04:50:25 PM PDT 24 Jul 10 04:50:28 PM PDT 24 159174654 ps
T901 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2472787012 Jul 10 04:50:12 PM PDT 24 Jul 10 04:50:14 PM PDT 24 141266180 ps
T902 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.638405374 Jul 10 04:50:18 PM PDT 24 Jul 10 04:50:22 PM PDT 24 72331315 ps
T903 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2595547344 Jul 10 04:50:23 PM PDT 24 Jul 10 04:50:26 PM PDT 24 163373983 ps
T904 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3465824162 Jul 10 04:50:23 PM PDT 24 Jul 10 04:50:26 PM PDT 24 245320051 ps
T905 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.304201449 Jul 10 04:50:16 PM PDT 24 Jul 10 04:50:18 PM PDT 24 69538610 ps
T906 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1205843370 Jul 10 04:50:34 PM PDT 24 Jul 10 04:50:38 PM PDT 24 235335308 ps
T907 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2103294433 Jul 10 04:50:33 PM PDT 24 Jul 10 04:50:37 PM PDT 24 115910663 ps
T908 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4261587893 Jul 10 04:50:33 PM PDT 24 Jul 10 04:50:36 PM PDT 24 48733748 ps
T909 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.527614474 Jul 10 04:50:18 PM PDT 24 Jul 10 04:50:22 PM PDT 24 1429665015 ps
T910 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.266296541 Jul 10 04:50:25 PM PDT 24 Jul 10 04:50:28 PM PDT 24 46715974 ps
T911 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3912962778 Jul 10 04:50:11 PM PDT 24 Jul 10 04:50:13 PM PDT 24 122871109 ps
T912 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4172490960 Jul 10 04:50:22 PM PDT 24 Jul 10 04:50:25 PM PDT 24 25288975 ps
T913 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3020951042 Jul 10 04:50:33 PM PDT 24 Jul 10 04:50:36 PM PDT 24 63675398 ps
T914 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.4269694364 Jul 10 04:50:18 PM PDT 24 Jul 10 04:50:22 PM PDT 24 571120088 ps
T915 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3217004447 Jul 10 04:50:34 PM PDT 24 Jul 10 04:50:38 PM PDT 24 58853391 ps
T916 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.635481290 Jul 10 04:50:03 PM PDT 24 Jul 10 04:50:05 PM PDT 24 36645457 ps
T917 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.44317727 Jul 10 04:50:35 PM PDT 24 Jul 10 04:50:38 PM PDT 24 69612962 ps
T918 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3306723128 Jul 10 04:50:04 PM PDT 24 Jul 10 04:50:06 PM PDT 24 108349785 ps
T919 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.349584349 Jul 10 04:50:34 PM PDT 24 Jul 10 04:50:38 PM PDT 24 196818584 ps
T920 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3360350571 Jul 10 04:50:16 PM PDT 24 Jul 10 04:50:19 PM PDT 24 619064787 ps
T921 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1081375044 Jul 10 04:50:09 PM PDT 24 Jul 10 04:50:11 PM PDT 24 84269781 ps
T922 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1399255952 Jul 10 04:50:18 PM PDT 24 Jul 10 04:50:22 PM PDT 24 72647750 ps
T923 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3875731298 Jul 10 04:50:12 PM PDT 24 Jul 10 04:50:14 PM PDT 24 28566396 ps
T924 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1873835608 Jul 10 04:50:26 PM PDT 24 Jul 10 04:50:29 PM PDT 24 77835935 ps
T925 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3357902597 Jul 10 04:50:16 PM PDT 24 Jul 10 04:50:17 PM PDT 24 18608890 ps
T926 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.996397147 Jul 10 04:50:16 PM PDT 24 Jul 10 04:50:18 PM PDT 24 44525392 ps
T927 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2556814141 Jul 10 04:50:24 PM PDT 24 Jul 10 04:50:27 PM PDT 24 86634427 ps
T928 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3947000791 Jul 10 04:50:18 PM PDT 24 Jul 10 04:50:23 PM PDT 24 202480429 ps
T929 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.855419566 Jul 10 04:50:04 PM PDT 24 Jul 10 04:50:06 PM PDT 24 150555428 ps
T930 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3579264848 Jul 10 04:50:34 PM PDT 24 Jul 10 04:50:38 PM PDT 24 63976353 ps
T931 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3627317793 Jul 10 04:50:24 PM PDT 24 Jul 10 04:50:26 PM PDT 24 224439178 ps
T932 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1060895577 Jul 10 04:50:17 PM PDT 24 Jul 10 04:50:21 PM PDT 24 32882852 ps
T933 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2665859234 Jul 10 04:50:30 PM PDT 24 Jul 10 04:50:32 PM PDT 24 50921001 ps
T934 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.149316407 Jul 10 04:50:09 PM PDT 24 Jul 10 04:50:11 PM PDT 24 285641078 ps
T935 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3174025828 Jul 10 04:50:32 PM PDT 24 Jul 10 04:50:36 PM PDT 24 81111461 ps
T936 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.450081635 Jul 10 04:50:32 PM PDT 24 Jul 10 04:50:34 PM PDT 24 96675440 ps
T937 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1892839051 Jul 10 04:50:32 PM PDT 24 Jul 10 04:50:34 PM PDT 24 213944873 ps
T938 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3900974151 Jul 10 04:50:07 PM PDT 24 Jul 10 04:50:09 PM PDT 24 613154161 ps
T939 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.216661698 Jul 10 04:50:18 PM PDT 24 Jul 10 04:50:22 PM PDT 24 70097941 ps
T940 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1165320636 Jul 10 04:50:25 PM PDT 24 Jul 10 04:50:28 PM PDT 24 52002864 ps
T941 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2891769718 Jul 10 04:50:10 PM PDT 24 Jul 10 04:50:13 PM PDT 24 1186237371 ps
T942 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3498478841 Jul 10 04:50:04 PM PDT 24 Jul 10 04:50:06 PM PDT 24 235475259 ps
T943 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1218398872 Jul 10 04:50:33 PM PDT 24 Jul 10 04:50:36 PM PDT 24 151160398 ps
T944 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2209550300 Jul 10 04:50:33 PM PDT 24 Jul 10 04:50:37 PM PDT 24 100247852 ps
T945 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2585295170 Jul 10 04:50:10 PM PDT 24 Jul 10 04:50:13 PM PDT 24 300324199 ps
T946 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3203312983 Jul 10 04:50:22 PM PDT 24 Jul 10 04:50:25 PM PDT 24 119152955 ps

Test location /workspace/coverage/default/15.gpio_stress_all.2737701988
Short name T1
Test name
Test status
Simulation time 82527827543 ps
CPU time 144.91 seconds
Started Jul 10 05:35:56 PM PDT 24
Finished Jul 10 05:38:22 PM PDT 24
Peak memory 198768 kb
Host smart-f4622a12-8c07-4430-8507-fc84d9b059c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737701988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2737701988
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3197157979
Short name T13
Test name
Test status
Simulation time 124026090 ps
CPU time 3.89 seconds
Started Jul 10 05:36:10 PM PDT 24
Finished Jul 10 05:36:15 PM PDT 24
Peak memory 196912 kb
Host smart-f0f83c61-98eb-48be-8296-ecf36707cc6c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197157979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3197157979
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.3255088598
Short name T19
Test name
Test status
Simulation time 1992733946953 ps
CPU time 1633.32 seconds
Started Jul 10 05:37:39 PM PDT 24
Finished Jul 10 06:04:53 PM PDT 24
Peak memory 198888 kb
Host smart-d4667e74-581f-410b-b80c-c7cd08d933ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3255088598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.3255088598
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1514802799
Short name T35
Test name
Test status
Simulation time 35418960 ps
CPU time 0.79 seconds
Started Jul 10 05:34:16 PM PDT 24
Finished Jul 10 05:34:17 PM PDT 24
Peak memory 214180 kb
Host smart-4a071dd4-4a3b-405b-b145-bb60843fc5fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514802799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1514802799
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.757979573
Short name T82
Test name
Test status
Simulation time 299265352 ps
CPU time 0.94 seconds
Started Jul 10 04:49:00 PM PDT 24
Finished Jul 10 04:49:02 PM PDT 24
Peak memory 197084 kb
Host smart-636772b9-2845-49ca-9034-f5d76bd29514
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757979573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.757979573
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2701529034
Short name T34
Test name
Test status
Simulation time 1565648162 ps
CPU time 1.35 seconds
Started Jul 10 04:49:47 PM PDT 24
Finished Jul 10 04:49:50 PM PDT 24
Peak memory 198508 kb
Host smart-ecac29fb-c777-4e03-b2ea-e085ba601f66
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701529034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2701529034
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/14.gpio_alert_test.898982082
Short name T28
Test name
Test status
Simulation time 16195266 ps
CPU time 0.54 seconds
Started Jul 10 05:35:53 PM PDT 24
Finished Jul 10 05:35:55 PM PDT 24
Peak memory 194632 kb
Host smart-2d76624e-7511-4be7-89bd-13a386a8226f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898982082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.898982082
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1503913072
Short name T80
Test name
Test status
Simulation time 110308567 ps
CPU time 0.73 seconds
Started Jul 10 04:48:54 PM PDT 24
Finished Jul 10 04:48:56 PM PDT 24
Peak memory 195536 kb
Host smart-987bc5e8-3516-4942-8b7b-39eb9cd5d20f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503913072 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1503913072
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.251908140
Short name T45
Test name
Test status
Simulation time 74461075 ps
CPU time 1.13 seconds
Started Jul 10 04:49:01 PM PDT 24
Finished Jul 10 04:49:04 PM PDT 24
Peak memory 198568 kb
Host smart-f80d138d-e1fa-49b3-97b4-e347d558da20
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251908140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.251908140
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2666707388
Short name T768
Test name
Test status
Simulation time 35193770 ps
CPU time 0.88 seconds
Started Jul 10 04:49:00 PM PDT 24
Finished Jul 10 04:49:01 PM PDT 24
Peak memory 196664 kb
Host smart-21a0834a-f72d-4510-a364-ebb957600ea7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666707388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2666707388
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.116297585
Short name T759
Test name
Test status
Simulation time 1501267197 ps
CPU time 3.68 seconds
Started Jul 10 04:48:59 PM PDT 24
Finished Jul 10 04:49:04 PM PDT 24
Peak memory 197732 kb
Host smart-4267d24c-2b2c-42d6-ae14-abd6b535fc9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116297585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.116297585
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1002441013
Short name T107
Test name
Test status
Simulation time 54390624 ps
CPU time 0.62 seconds
Started Jul 10 04:49:02 PM PDT 24
Finished Jul 10 04:49:04 PM PDT 24
Peak memory 195160 kb
Host smart-b2b3f4bb-4e78-4fef-b6f8-0c89969a8c85
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002441013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1002441013
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.636372412
Short name T754
Test name
Test status
Simulation time 30581341 ps
CPU time 1.44 seconds
Started Jul 10 04:49:00 PM PDT 24
Finished Jul 10 04:49:02 PM PDT 24
Peak memory 198652 kb
Host smart-8029c2ff-a324-4aa2-bfa3-13808d5608d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636372412 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.636372412
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.4083629410
Short name T819
Test name
Test status
Simulation time 23853879 ps
CPU time 0.64 seconds
Started Jul 10 04:48:55 PM PDT 24
Finished Jul 10 04:48:58 PM PDT 24
Peak memory 195408 kb
Host smart-8468674e-72fd-4f3e-92ce-1a9500389b15
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083629410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.4083629410
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1867190908
Short name T839
Test name
Test status
Simulation time 61499700 ps
CPU time 0.63 seconds
Started Jul 10 04:49:02 PM PDT 24
Finished Jul 10 04:49:04 PM PDT 24
Peak memory 194208 kb
Host smart-3cc0d23f-24e0-4f8f-9ff8-48fd2598f691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867190908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1867190908
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2757067147
Short name T784
Test name
Test status
Simulation time 653201411 ps
CPU time 1.86 seconds
Started Jul 10 04:49:01 PM PDT 24
Finished Jul 10 04:49:04 PM PDT 24
Peak memory 198596 kb
Host smart-5b2676a9-fb76-470a-8bbc-6bd6cd7eba4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757067147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2757067147
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.649104014
Short name T753
Test name
Test status
Simulation time 412136278 ps
CPU time 1.23 seconds
Started Jul 10 04:48:55 PM PDT 24
Finished Jul 10 04:48:58 PM PDT 24
Peak memory 198128 kb
Host smart-79fc71b0-689f-4fde-a98f-105fa6dcca87
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649104014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.649104014
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.892304864
Short name T93
Test name
Test status
Simulation time 71929657 ps
CPU time 1.38 seconds
Started Jul 10 04:49:00 PM PDT 24
Finished Jul 10 04:49:03 PM PDT 24
Peak memory 197736 kb
Host smart-92981e7e-334d-4ff6-a477-62225c81ec18
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892304864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.892304864
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3205880532
Short name T106
Test name
Test status
Simulation time 54620955 ps
CPU time 0.62 seconds
Started Jul 10 04:49:01 PM PDT 24
Finished Jul 10 04:49:04 PM PDT 24
Peak memory 195892 kb
Host smart-1b19cbf3-ef58-4b43-8869-e0adccec3b5b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205880532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3205880532
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.4109236184
Short name T807
Test name
Test status
Simulation time 24163607 ps
CPU time 0.79 seconds
Started Jul 10 04:49:02 PM PDT 24
Finished Jul 10 04:49:04 PM PDT 24
Peak memory 198404 kb
Host smart-91a8d9fd-081a-4abb-95a0-0d8895d91f22
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109236184 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.4109236184
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.4089413002
Short name T91
Test name
Test status
Simulation time 29150193 ps
CPU time 0.63 seconds
Started Jul 10 04:49:00 PM PDT 24
Finished Jul 10 04:49:02 PM PDT 24
Peak memory 195392 kb
Host smart-cf9a767c-7a49-41c3-8336-2b5ccf26949c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089413002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.4089413002
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1664347636
Short name T834
Test name
Test status
Simulation time 34261625 ps
CPU time 0.6 seconds
Started Jul 10 04:49:01 PM PDT 24
Finished Jul 10 04:49:03 PM PDT 24
Peak memory 194804 kb
Host smart-d178e1af-4b91-41d7-8956-72645065f6d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664347636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1664347636
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1819394231
Short name T815
Test name
Test status
Simulation time 23077780 ps
CPU time 0.65 seconds
Started Jul 10 04:49:01 PM PDT 24
Finished Jul 10 04:49:03 PM PDT 24
Peak memory 195760 kb
Host smart-69356223-8df5-4ae9-b0c1-af2a50be76b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819394231 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1819394231
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2604586997
Short name T736
Test name
Test status
Simulation time 208148387 ps
CPU time 2.12 seconds
Started Jul 10 04:49:00 PM PDT 24
Finished Jul 10 04:49:03 PM PDT 24
Peak memory 198628 kb
Host smart-501fbe0b-5ca5-4e71-ba0d-7eab8af8968f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604586997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2604586997
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2017350957
Short name T741
Test name
Test status
Simulation time 137789038 ps
CPU time 1.02 seconds
Started Jul 10 04:49:32 PM PDT 24
Finished Jul 10 04:49:35 PM PDT 24
Peak memory 198456 kb
Host smart-fd79932e-7594-4177-9fdc-22f1d711ed26
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017350957 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2017350957
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3128194194
Short name T758
Test name
Test status
Simulation time 13148509 ps
CPU time 0.58 seconds
Started Jul 10 04:49:43 PM PDT 24
Finished Jul 10 04:49:44 PM PDT 24
Peak memory 195136 kb
Host smart-70cb5dad-c0b4-4d6a-a2ba-1c040c0832e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128194194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3128194194
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3233258204
Short name T829
Test name
Test status
Simulation time 31209041 ps
CPU time 0.57 seconds
Started Jul 10 04:49:32 PM PDT 24
Finished Jul 10 04:49:34 PM PDT 24
Peak memory 194180 kb
Host smart-bbcb1825-f538-4ddf-a6f6-65a31415c707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233258204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3233258204
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3524341219
Short name T811
Test name
Test status
Simulation time 47223475 ps
CPU time 0.68 seconds
Started Jul 10 04:49:31 PM PDT 24
Finished Jul 10 04:49:33 PM PDT 24
Peak memory 195944 kb
Host smart-f88d98c0-09f6-4d0e-82a6-2facdb267c2f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524341219 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3524341219
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2259764045
Short name T830
Test name
Test status
Simulation time 1451711948 ps
CPU time 2.84 seconds
Started Jul 10 04:49:31 PM PDT 24
Finished Jul 10 04:49:36 PM PDT 24
Peak memory 198628 kb
Host smart-692acdee-a992-4c98-961f-f6e9a5e45d76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259764045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2259764045
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1033095991
Short name T42
Test name
Test status
Simulation time 429164922 ps
CPU time 1.4 seconds
Started Jul 10 04:49:31 PM PDT 24
Finished Jul 10 04:49:33 PM PDT 24
Peak memory 198576 kb
Host smart-a822586b-4feb-447d-8863-d01e07ca1ea1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033095991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1033095991
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1252653460
Short name T746
Test name
Test status
Simulation time 97209483 ps
CPU time 0.92 seconds
Started Jul 10 04:49:31 PM PDT 24
Finished Jul 10 04:49:34 PM PDT 24
Peak memory 198420 kb
Host smart-52cbb27f-38c0-4a87-9c3d-ed35eeb52c7c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252653460 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1252653460
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2418140602
Short name T94
Test name
Test status
Simulation time 46603142 ps
CPU time 0.63 seconds
Started Jul 10 04:49:43 PM PDT 24
Finished Jul 10 04:49:44 PM PDT 24
Peak memory 195432 kb
Host smart-ce4376cc-8c14-4a59-a7fe-e6432bcb8d1a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418140602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2418140602
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.4195048911
Short name T730
Test name
Test status
Simulation time 94263310 ps
CPU time 0.57 seconds
Started Jul 10 04:49:41 PM PDT 24
Finished Jul 10 04:49:42 PM PDT 24
Peak memory 194048 kb
Host smart-d64826c6-f961-44ab-aded-f3af8c058d5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195048911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.4195048911
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3875855828
Short name T840
Test name
Test status
Simulation time 35442146 ps
CPU time 0.9 seconds
Started Jul 10 04:49:42 PM PDT 24
Finished Jul 10 04:49:43 PM PDT 24
Peak memory 197008 kb
Host smart-8e20459c-a3ae-4253-9adf-9c07eeac3066
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875855828 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3875855828
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3072654678
Short name T781
Test name
Test status
Simulation time 76401349 ps
CPU time 1.51 seconds
Started Jul 10 04:49:32 PM PDT 24
Finished Jul 10 04:49:35 PM PDT 24
Peak memory 198568 kb
Host smart-c1c456f7-2b90-4160-b3c1-732a357b1d63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072654678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3072654678
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2752580132
Short name T32
Test name
Test status
Simulation time 469050036 ps
CPU time 1.5 seconds
Started Jul 10 04:49:30 PM PDT 24
Finished Jul 10 04:49:33 PM PDT 24
Peak memory 198628 kb
Host smart-dc83c8a7-4a87-467f-b0a1-961e82246de1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752580132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2752580132
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1791235737
Short name T827
Test name
Test status
Simulation time 18141418 ps
CPU time 0.67 seconds
Started Jul 10 04:49:40 PM PDT 24
Finished Jul 10 04:49:41 PM PDT 24
Peak memory 197284 kb
Host smart-05e4c7a3-36f3-4913-94b4-d82d2e847e31
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791235737 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1791235737
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1820559780
Short name T95
Test name
Test status
Simulation time 47536334 ps
CPU time 0.63 seconds
Started Jul 10 04:49:32 PM PDT 24
Finished Jul 10 04:49:34 PM PDT 24
Peak memory 195316 kb
Host smart-5f946000-d0af-40fd-9697-8a45b0a522b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820559780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1820559780
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.486319804
Short name T723
Test name
Test status
Simulation time 17682710 ps
CPU time 0.63 seconds
Started Jul 10 04:49:37 PM PDT 24
Finished Jul 10 04:49:39 PM PDT 24
Peak memory 194200 kb
Host smart-81074ede-6c77-4b47-a651-d3db945886e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486319804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.486319804
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1298139294
Short name T104
Test name
Test status
Simulation time 20610039 ps
CPU time 0.87 seconds
Started Jul 10 04:49:37 PM PDT 24
Finished Jul 10 04:49:39 PM PDT 24
Peak memory 196860 kb
Host smart-40b9bd95-5e4a-47e3-bb3c-5a677660a190
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298139294 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.1298139294
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.482473264
Short name T767
Test name
Test status
Simulation time 100930256 ps
CPU time 2.37 seconds
Started Jul 10 04:49:41 PM PDT 24
Finished Jul 10 04:49:44 PM PDT 24
Peak memory 198560 kb
Host smart-db611cbd-18a4-4dd8-b1b4-9f4bb782c20e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482473264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.482473264
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1004124347
Short name T727
Test name
Test status
Simulation time 50228368 ps
CPU time 0.84 seconds
Started Jul 10 04:49:47 PM PDT 24
Finished Jul 10 04:49:50 PM PDT 24
Peak memory 198340 kb
Host smart-7ff0a334-ed13-4f52-a746-44513675cf6d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004124347 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1004124347
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.601676702
Short name T108
Test name
Test status
Simulation time 43879607 ps
CPU time 0.59 seconds
Started Jul 10 04:49:38 PM PDT 24
Finished Jul 10 04:49:40 PM PDT 24
Peak memory 195920 kb
Host smart-6a0d684f-f119-4c06-8c36-4389fc1df3bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601676702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.601676702
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1247310235
Short name T747
Test name
Test status
Simulation time 20952022 ps
CPU time 0.63 seconds
Started Jul 10 04:49:38 PM PDT 24
Finished Jul 10 04:49:40 PM PDT 24
Peak memory 194316 kb
Host smart-1d9d9eb3-dabf-446e-b92d-99d3d4408650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247310235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1247310235
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2169153364
Short name T105
Test name
Test status
Simulation time 34633358 ps
CPU time 0.83 seconds
Started Jul 10 04:49:38 PM PDT 24
Finished Jul 10 04:49:41 PM PDT 24
Peak memory 197604 kb
Host smart-9aead4f9-cd7b-4cdb-957c-88f17d0a2b56
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169153364 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2169153364
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1853582929
Short name T814
Test name
Test status
Simulation time 103731656 ps
CPU time 2.5 seconds
Started Jul 10 04:49:38 PM PDT 24
Finished Jul 10 04:49:42 PM PDT 24
Peak memory 198564 kb
Host smart-cf14b013-8832-41e9-b057-c5d403053d02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853582929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1853582929
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3956345409
Short name T40
Test name
Test status
Simulation time 617908316 ps
CPU time 1.16 seconds
Started Jul 10 04:49:40 PM PDT 24
Finished Jul 10 04:49:42 PM PDT 24
Peak memory 198580 kb
Host smart-9c9068d1-653c-4331-be33-cafadc2f3ef4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956345409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.3956345409
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.629467506
Short name T722
Test name
Test status
Simulation time 36984801 ps
CPU time 0.93 seconds
Started Jul 10 04:49:40 PM PDT 24
Finished Jul 10 04:49:42 PM PDT 24
Peak memory 198488 kb
Host smart-9da34764-ed37-4bcb-b1b1-f5a2a6d217e9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629467506 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.629467506
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3777102289
Short name T833
Test name
Test status
Simulation time 13593714 ps
CPU time 0.62 seconds
Started Jul 10 04:49:38 PM PDT 24
Finished Jul 10 04:49:40 PM PDT 24
Peak memory 195200 kb
Host smart-f8144c4f-135d-4f11-a5c0-35dfeb89a652
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777102289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3777102289
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.4178258075
Short name T802
Test name
Test status
Simulation time 21292052 ps
CPU time 0.59 seconds
Started Jul 10 04:49:43 PM PDT 24
Finished Jul 10 04:49:45 PM PDT 24
Peak memory 194184 kb
Host smart-9ee7cc0d-ee56-4ea1-8a80-6de2cb946b78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178258075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.4178258075
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2736498930
Short name T85
Test name
Test status
Simulation time 20679983 ps
CPU time 0.92 seconds
Started Jul 10 04:49:37 PM PDT 24
Finished Jul 10 04:49:39 PM PDT 24
Peak memory 198424 kb
Host smart-616c1985-8d59-4a7f-b81d-2b819f32b4e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736498930 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2736498930
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3268061690
Short name T808
Test name
Test status
Simulation time 1156901407 ps
CPU time 3.13 seconds
Started Jul 10 04:49:44 PM PDT 24
Finished Jul 10 04:49:49 PM PDT 24
Peak memory 198568 kb
Host smart-06deca7f-f813-4ffb-85de-f16f552e780e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268061690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3268061690
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1939590197
Short name T43
Test name
Test status
Simulation time 83810697 ps
CPU time 0.85 seconds
Started Jul 10 04:49:47 PM PDT 24
Finished Jul 10 04:49:50 PM PDT 24
Peak memory 197636 kb
Host smart-55db9e6c-a5ef-41ef-afa6-ba068403745b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939590197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1939590197
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2738085243
Short name T804
Test name
Test status
Simulation time 99338458 ps
CPU time 0.85 seconds
Started Jul 10 04:49:45 PM PDT 24
Finished Jul 10 04:49:47 PM PDT 24
Peak memory 198428 kb
Host smart-35683e3b-ec29-4d07-952f-9a18dd35751d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738085243 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2738085243
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.674991423
Short name T83
Test name
Test status
Simulation time 24626894 ps
CPU time 0.62 seconds
Started Jul 10 04:49:46 PM PDT 24
Finished Jul 10 04:49:48 PM PDT 24
Peak memory 195440 kb
Host smart-373a71a8-9a9c-475a-b0fd-fca53b3eca26
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674991423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.674991423
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.32909712
Short name T828
Test name
Test status
Simulation time 41252259 ps
CPU time 0.61 seconds
Started Jul 10 04:49:46 PM PDT 24
Finished Jul 10 04:49:48 PM PDT 24
Peak memory 194816 kb
Host smart-5480c289-dcd3-46ff-b157-3da92c8c22b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32909712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.32909712
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1711361460
Short name T835
Test name
Test status
Simulation time 18567350 ps
CPU time 0.67 seconds
Started Jul 10 04:49:44 PM PDT 24
Finished Jul 10 04:49:47 PM PDT 24
Peak memory 196076 kb
Host smart-114b205e-874e-4ad2-ac8a-d6115ef665a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711361460 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1711361460
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.451047368
Short name T731
Test name
Test status
Simulation time 419504188 ps
CPU time 3.56 seconds
Started Jul 10 04:49:44 PM PDT 24
Finished Jul 10 04:49:50 PM PDT 24
Peak memory 198592 kb
Host smart-ef544c48-ae79-47c9-bf95-eb2fbecd45b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451047368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.451047368
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3522235065
Short name T770
Test name
Test status
Simulation time 627862360 ps
CPU time 0.89 seconds
Started Jul 10 04:49:44 PM PDT 24
Finished Jul 10 04:49:46 PM PDT 24
Peak memory 198324 kb
Host smart-adb32f7f-cd82-492b-9005-c614dd470909
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522235065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3522235065
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3502940219
Short name T765
Test name
Test status
Simulation time 50504426 ps
CPU time 1.27 seconds
Started Jul 10 04:49:45 PM PDT 24
Finished Jul 10 04:49:48 PM PDT 24
Peak memory 198664 kb
Host smart-e81e9012-5fea-40be-a085-7268aa659c33
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502940219 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3502940219
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2581023132
Short name T771
Test name
Test status
Simulation time 42243192 ps
CPU time 0.63 seconds
Started Jul 10 04:49:46 PM PDT 24
Finished Jul 10 04:49:49 PM PDT 24
Peak memory 195368 kb
Host smart-01e5b13c-6a0e-434f-a884-cc67d1b8231c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581023132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2581023132
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2891269952
Short name T809
Test name
Test status
Simulation time 38353260 ps
CPU time 0.58 seconds
Started Jul 10 04:49:45 PM PDT 24
Finished Jul 10 04:49:47 PM PDT 24
Peak memory 194176 kb
Host smart-dc43c7ea-8961-44e7-8191-dc4d66b285a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891269952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2891269952
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2269117175
Short name T777
Test name
Test status
Simulation time 125489008 ps
CPU time 0.9 seconds
Started Jul 10 04:49:44 PM PDT 24
Finished Jul 10 04:49:47 PM PDT 24
Peak memory 197644 kb
Host smart-bcfdb992-4faf-43da-b11c-55eaa8dfa4b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269117175 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2269117175
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2677451620
Short name T744
Test name
Test status
Simulation time 54392281 ps
CPU time 2.83 seconds
Started Jul 10 04:49:47 PM PDT 24
Finished Jul 10 04:49:51 PM PDT 24
Peak memory 198592 kb
Host smart-1aacbaa5-a2d3-4ec3-9ce1-b90b389a8ffb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677451620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2677451620
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3749264901
Short name T41
Test name
Test status
Simulation time 121599383 ps
CPU time 0.85 seconds
Started Jul 10 04:49:45 PM PDT 24
Finished Jul 10 04:49:48 PM PDT 24
Peak memory 197764 kb
Host smart-e62f4cc9-61ab-4cba-b142-dbbda93175db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749264901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3749264901
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3236023325
Short name T812
Test name
Test status
Simulation time 20854864 ps
CPU time 0.71 seconds
Started Jul 10 04:49:44 PM PDT 24
Finished Jul 10 04:49:46 PM PDT 24
Peak memory 197844 kb
Host smart-e6c7e175-6a09-4af9-884a-9712851fd59f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236023325 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3236023325
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2942362302
Short name T756
Test name
Test status
Simulation time 27768056 ps
CPU time 0.58 seconds
Started Jul 10 04:49:50 PM PDT 24
Finished Jul 10 04:49:52 PM PDT 24
Peak memory 195160 kb
Host smart-9347f7e2-b867-4620-9f81-61eb0427b78b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942362302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2942362302
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3493271109
Short name T782
Test name
Test status
Simulation time 11789062 ps
CPU time 0.61 seconds
Started Jul 10 04:49:44 PM PDT 24
Finished Jul 10 04:49:47 PM PDT 24
Peak memory 194352 kb
Host smart-977cba1d-0142-4dc6-ab3a-22f5927d2246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493271109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3493271109
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.814469842
Short name T793
Test name
Test status
Simulation time 121029977 ps
CPU time 0.8 seconds
Started Jul 10 04:49:51 PM PDT 24
Finished Jul 10 04:49:53 PM PDT 24
Peak memory 196648 kb
Host smart-9d2ff3e0-c24c-4c17-a004-329b5c5b04db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814469842 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.814469842
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1481200853
Short name T766
Test name
Test status
Simulation time 45553952 ps
CPU time 1.69 seconds
Started Jul 10 04:49:44 PM PDT 24
Finished Jul 10 04:49:47 PM PDT 24
Peak memory 198580 kb
Host smart-56ed82ed-33ce-46de-a1f7-8624b8abf901
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481200853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1481200853
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1766034331
Short name T805
Test name
Test status
Simulation time 68718876 ps
CPU time 1.12 seconds
Started Jul 10 04:49:47 PM PDT 24
Finished Jul 10 04:49:50 PM PDT 24
Peak memory 198596 kb
Host smart-967bc34e-5486-468a-9440-561d4510a5b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766034331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1766034331
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.309214302
Short name T794
Test name
Test status
Simulation time 22413170 ps
CPU time 1.12 seconds
Started Jul 10 04:49:47 PM PDT 24
Finished Jul 10 04:49:49 PM PDT 24
Peak memory 198664 kb
Host smart-6e51301d-fb9b-45c9-a75e-361a22044615
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309214302 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.309214302
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1412277932
Short name T97
Test name
Test status
Simulation time 76263751 ps
CPU time 0.62 seconds
Started Jul 10 04:49:45 PM PDT 24
Finished Jul 10 04:49:48 PM PDT 24
Peak memory 195424 kb
Host smart-2bb15cd4-f08e-4534-815e-b1b3c4e9ff14
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412277932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1412277932
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.667745805
Short name T792
Test name
Test status
Simulation time 86830224 ps
CPU time 0.6 seconds
Started Jul 10 04:49:51 PM PDT 24
Finished Jul 10 04:49:53 PM PDT 24
Peak memory 194212 kb
Host smart-283eeace-b465-404b-ac37-e8b1c493a23d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667745805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.667745805
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.961828704
Short name T100
Test name
Test status
Simulation time 36688089 ps
CPU time 0.87 seconds
Started Jul 10 04:49:45 PM PDT 24
Finished Jul 10 04:49:47 PM PDT 24
Peak memory 196844 kb
Host smart-f235d802-7e48-4bde-a5f5-eeda3a6dc8ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961828704 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.gpio_same_csr_outstanding.961828704
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3561411685
Short name T775
Test name
Test status
Simulation time 51586059 ps
CPU time 2.74 seconds
Started Jul 10 04:49:53 PM PDT 24
Finished Jul 10 04:49:57 PM PDT 24
Peak memory 198592 kb
Host smart-e0c79fbc-260c-4a12-a279-ba3bd202fe75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561411685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3561411685
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1819880782
Short name T46
Test name
Test status
Simulation time 327814833 ps
CPU time 1.16 seconds
Started Jul 10 04:49:46 PM PDT 24
Finished Jul 10 04:49:49 PM PDT 24
Peak memory 198336 kb
Host smart-bae87553-57ba-4c02-acc1-a25a51d02a11
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819880782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1819880782
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3079753031
Short name T757
Test name
Test status
Simulation time 42531099 ps
CPU time 1 seconds
Started Jul 10 04:49:51 PM PDT 24
Finished Jul 10 04:49:53 PM PDT 24
Peak memory 198576 kb
Host smart-1665a46f-4375-40d6-af7e-4a3d7457c54c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079753031 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3079753031
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1301516406
Short name T755
Test name
Test status
Simulation time 12926424 ps
CPU time 0.63 seconds
Started Jul 10 04:49:53 PM PDT 24
Finished Jul 10 04:49:55 PM PDT 24
Peak memory 195236 kb
Host smart-b605e1ff-94f0-449d-88dc-e21a5eb6167b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301516406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1301516406
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1258381378
Short name T734
Test name
Test status
Simulation time 45485694 ps
CPU time 0.6 seconds
Started Jul 10 04:49:53 PM PDT 24
Finished Jul 10 04:49:55 PM PDT 24
Peak memory 194188 kb
Host smart-7320a41e-dd3d-45b2-9a2e-186fcbd9fee5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258381378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1258381378
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3288959030
Short name T825
Test name
Test status
Simulation time 141444194 ps
CPU time 0.85 seconds
Started Jul 10 04:49:52 PM PDT 24
Finished Jul 10 04:49:55 PM PDT 24
Peak memory 196716 kb
Host smart-dc53d7e4-445a-4b3b-8753-48c9675ea5ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288959030 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3288959030
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1349978118
Short name T724
Test name
Test status
Simulation time 140933055 ps
CPU time 2.91 seconds
Started Jul 10 04:49:52 PM PDT 24
Finished Jul 10 04:49:57 PM PDT 24
Peak memory 198572 kb
Host smart-030b5a75-1bfb-4de3-af2d-4d6dff8a1ad2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349978118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1349978118
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3707841080
Short name T816
Test name
Test status
Simulation time 157903161 ps
CPU time 0.94 seconds
Started Jul 10 04:49:50 PM PDT 24
Finished Jul 10 04:49:52 PM PDT 24
Peak memory 197736 kb
Host smart-e288df79-24a9-40b6-951e-b4395f79c02c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707841080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3707841080
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.4170886552
Short name T81
Test name
Test status
Simulation time 36056110 ps
CPU time 0.65 seconds
Started Jul 10 04:49:00 PM PDT 24
Finished Jul 10 04:49:02 PM PDT 24
Peak memory 195388 kb
Host smart-13ca7716-094f-42bc-8101-84399a64252a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170886552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.4170886552
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.284343080
Short name T838
Test name
Test status
Simulation time 260490779 ps
CPU time 3.42 seconds
Started Jul 10 04:49:06 PM PDT 24
Finished Jul 10 04:49:10 PM PDT 24
Peak memory 197724 kb
Host smart-76bc427d-d76c-4cd1-aaf3-08c8f01b38e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284343080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.284343080
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.662101573
Short name T87
Test name
Test status
Simulation time 19762268 ps
CPU time 0.69 seconds
Started Jul 10 04:49:07 PM PDT 24
Finished Jul 10 04:49:09 PM PDT 24
Peak memory 196232 kb
Host smart-8a1e4ae5-b0b6-4b0e-b8a7-53bf6783199d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662101573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.662101573
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3335637441
Short name T773
Test name
Test status
Simulation time 21685026 ps
CPU time 0.98 seconds
Started Jul 10 04:49:07 PM PDT 24
Finished Jul 10 04:49:09 PM PDT 24
Peak memory 198480 kb
Host smart-86bd286f-1cf2-4435-8db5-1963fe7a93ee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335637441 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3335637441
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1610426370
Short name T88
Test name
Test status
Simulation time 25534132 ps
CPU time 0.6 seconds
Started Jul 10 04:49:00 PM PDT 24
Finished Jul 10 04:49:02 PM PDT 24
Peak memory 195128 kb
Host smart-9e5d669d-d72b-41c2-baa3-f310b425b8b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610426370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1610426370
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3680082457
Short name T750
Test name
Test status
Simulation time 53774005 ps
CPU time 0.65 seconds
Started Jul 10 04:49:09 PM PDT 24
Finished Jul 10 04:49:10 PM PDT 24
Peak memory 194200 kb
Host smart-f3d0f5af-3744-4418-851e-8ef3102e92c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680082457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3680082457
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2932376146
Short name T86
Test name
Test status
Simulation time 45743879 ps
CPU time 0.66 seconds
Started Jul 10 04:49:00 PM PDT 24
Finished Jul 10 04:49:01 PM PDT 24
Peak memory 195816 kb
Host smart-fe1dfadd-f1f4-41e3-a14a-c4670fa0b904
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932376146 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2932376146
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.206915115
Short name T737
Test name
Test status
Simulation time 541890697 ps
CPU time 2.49 seconds
Started Jul 10 04:49:05 PM PDT 24
Finished Jul 10 04:49:09 PM PDT 24
Peak memory 198584 kb
Host smart-d6a3b9ff-29fc-4239-8fb5-630df28194c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206915115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.206915115
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3591801841
Short name T47
Test name
Test status
Simulation time 493017065 ps
CPU time 1.32 seconds
Started Jul 10 04:49:06 PM PDT 24
Finished Jul 10 04:49:08 PM PDT 24
Peak memory 198592 kb
Host smart-0cfb485d-05b4-4fab-8218-ed71c96aa0bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591801841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3591801841
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2304498672
Short name T795
Test name
Test status
Simulation time 17033810 ps
CPU time 0.59 seconds
Started Jul 10 04:49:50 PM PDT 24
Finished Jul 10 04:49:52 PM PDT 24
Peak memory 194240 kb
Host smart-98ae51dc-aeca-49fb-9da9-69c8afd1b131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304498672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2304498672
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.425973432
Short name T822
Test name
Test status
Simulation time 18369552 ps
CPU time 0.64 seconds
Started Jul 10 04:49:51 PM PDT 24
Finished Jul 10 04:49:53 PM PDT 24
Peak memory 194304 kb
Host smart-544d91a1-87d3-4e1d-8025-8b0b0d5a373a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425973432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.425973432
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.4262538201
Short name T740
Test name
Test status
Simulation time 102911468 ps
CPU time 0.63 seconds
Started Jul 10 04:49:53 PM PDT 24
Finished Jul 10 04:49:55 PM PDT 24
Peak memory 194196 kb
Host smart-998d89f4-c48b-46eb-95a1-f858ea6a874a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262538201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.4262538201
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1983162385
Short name T826
Test name
Test status
Simulation time 45269896 ps
CPU time 0.66 seconds
Started Jul 10 04:49:55 PM PDT 24
Finished Jul 10 04:49:56 PM PDT 24
Peak memory 193556 kb
Host smart-89d5f98f-329b-4a46-ab90-95246f21e703
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983162385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1983162385
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3053690636
Short name T748
Test name
Test status
Simulation time 18773506 ps
CPU time 0.66 seconds
Started Jul 10 04:49:55 PM PDT 24
Finished Jul 10 04:49:56 PM PDT 24
Peak memory 193452 kb
Host smart-5c161755-2641-466d-9aec-1d2ec6371bea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053690636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3053690636
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2210445852
Short name T796
Test name
Test status
Simulation time 14625470 ps
CPU time 0.61 seconds
Started Jul 10 04:49:51 PM PDT 24
Finished Jul 10 04:49:53 PM PDT 24
Peak memory 194268 kb
Host smart-ba4226d7-c85e-488b-a314-c493d48d9528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210445852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2210445852
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3326732365
Short name T732
Test name
Test status
Simulation time 31122852 ps
CPU time 0.61 seconds
Started Jul 10 04:49:51 PM PDT 24
Finished Jul 10 04:49:53 PM PDT 24
Peak memory 194252 kb
Host smart-07c6e363-d395-407e-b6b7-0a404070437d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326732365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3326732365
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1203771396
Short name T787
Test name
Test status
Simulation time 24382612 ps
CPU time 0.61 seconds
Started Jul 10 04:49:53 PM PDT 24
Finished Jul 10 04:49:55 PM PDT 24
Peak memory 194200 kb
Host smart-ef95d1fd-bc08-48de-bb5e-a4eb2c26dbee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203771396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1203771396
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.4054222790
Short name T842
Test name
Test status
Simulation time 25361655 ps
CPU time 0.61 seconds
Started Jul 10 04:49:51 PM PDT 24
Finished Jul 10 04:49:53 PM PDT 24
Peak memory 194588 kb
Host smart-57c94425-a5de-4c88-bcbf-1e2698a80074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054222790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.4054222790
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2323122687
Short name T774
Test name
Test status
Simulation time 30477536 ps
CPU time 0.65 seconds
Started Jul 10 04:49:52 PM PDT 24
Finished Jul 10 04:49:54 PM PDT 24
Peak memory 194288 kb
Host smart-4abc59c2-a5bc-44fd-b848-e8feb7488e89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323122687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2323122687
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1010819347
Short name T96
Test name
Test status
Simulation time 133501141 ps
CPU time 0.79 seconds
Started Jul 10 04:49:07 PM PDT 24
Finished Jul 10 04:49:09 PM PDT 24
Peak memory 197100 kb
Host smart-52658d86-ea37-490d-9324-ba61fb7d8872
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010819347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1010819347
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1461375547
Short name T798
Test name
Test status
Simulation time 877586485 ps
CPU time 2.4 seconds
Started Jul 10 04:49:12 PM PDT 24
Finished Jul 10 04:49:15 PM PDT 24
Peak memory 198576 kb
Host smart-720c28c9-944a-439e-b92a-1aefe033fef1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461375547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1461375547
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3210968791
Short name T89
Test name
Test status
Simulation time 14173280 ps
CPU time 0.61 seconds
Started Jul 10 04:49:11 PM PDT 24
Finished Jul 10 04:49:12 PM PDT 24
Peak memory 195584 kb
Host smart-b0f3eb35-42d7-4189-8b64-db8cf41ebea0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210968791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3210968791
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2873238536
Short name T783
Test name
Test status
Simulation time 66530487 ps
CPU time 0.66 seconds
Started Jul 10 04:49:09 PM PDT 24
Finished Jul 10 04:49:10 PM PDT 24
Peak memory 197868 kb
Host smart-339a8e18-3074-471a-8c37-138d030b4684
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873238536 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2873238536
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.624346229
Short name T751
Test name
Test status
Simulation time 13524404 ps
CPU time 0.64 seconds
Started Jul 10 04:49:05 PM PDT 24
Finished Jul 10 04:49:07 PM PDT 24
Peak memory 195352 kb
Host smart-99aa76f2-3998-458b-a859-fef08c5e7d5a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624346229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.624346229
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2043049193
Short name T831
Test name
Test status
Simulation time 47663330 ps
CPU time 0.61 seconds
Started Jul 10 04:49:11 PM PDT 24
Finished Jul 10 04:49:12 PM PDT 24
Peak memory 194832 kb
Host smart-aed01a07-b636-4fc0-a55f-b3bd9f043ea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043049193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2043049193
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3976138970
Short name T102
Test name
Test status
Simulation time 35029889 ps
CPU time 0.81 seconds
Started Jul 10 04:49:07 PM PDT 24
Finished Jul 10 04:49:09 PM PDT 24
Peak memory 196740 kb
Host smart-b1f50f56-04f7-4203-b8dc-1687e05b443a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976138970 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3976138970
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2636382035
Short name T745
Test name
Test status
Simulation time 24716324 ps
CPU time 1.3 seconds
Started Jul 10 04:49:05 PM PDT 24
Finished Jul 10 04:49:07 PM PDT 24
Peak memory 198668 kb
Host smart-8dd82182-ce3d-42e6-9ca8-045b92483e43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636382035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2636382035
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.594107412
Short name T788
Test name
Test status
Simulation time 78256526 ps
CPU time 0.89 seconds
Started Jul 10 04:49:05 PM PDT 24
Finished Jul 10 04:49:07 PM PDT 24
Peak memory 197880 kb
Host smart-e1caec5e-c370-4420-a709-4b3e0f1b4fd6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594107412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.594107412
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.286058381
Short name T810
Test name
Test status
Simulation time 36380552 ps
CPU time 0.57 seconds
Started Jul 10 04:49:52 PM PDT 24
Finished Jul 10 04:49:54 PM PDT 24
Peak memory 194184 kb
Host smart-b1b035d6-d984-4f13-a9bb-9d487c50c7aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286058381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.286058381
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1606506704
Short name T762
Test name
Test status
Simulation time 19508895 ps
CPU time 0.63 seconds
Started Jul 10 04:49:52 PM PDT 24
Finished Jul 10 04:49:54 PM PDT 24
Peak memory 194228 kb
Host smart-05408368-4616-4838-86a3-d8c3c4b63af3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606506704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1606506704
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.421140966
Short name T725
Test name
Test status
Simulation time 21116295 ps
CPU time 0.62 seconds
Started Jul 10 04:49:58 PM PDT 24
Finished Jul 10 04:49:59 PM PDT 24
Peak memory 195168 kb
Host smart-411faf46-d889-4a3d-a6f7-56137e2f556a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421140966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.421140966
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.680409228
Short name T797
Test name
Test status
Simulation time 25275884 ps
CPU time 0.62 seconds
Started Jul 10 04:49:58 PM PDT 24
Finished Jul 10 04:50:00 PM PDT 24
Peak memory 194288 kb
Host smart-96680a82-d78c-471f-aa0d-2b3b17cb2c55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680409228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.680409228
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1311590103
Short name T801
Test name
Test status
Simulation time 60011753 ps
CPU time 0.62 seconds
Started Jul 10 04:49:59 PM PDT 24
Finished Jul 10 04:50:01 PM PDT 24
Peak memory 194244 kb
Host smart-885a12b0-cab4-4948-8225-4b3fac7dbd6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311590103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1311590103
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2918203513
Short name T820
Test name
Test status
Simulation time 49378240 ps
CPU time 0.57 seconds
Started Jul 10 04:50:01 PM PDT 24
Finished Jul 10 04:50:03 PM PDT 24
Peak memory 194244 kb
Host smart-8bbafabd-0925-452e-b2ab-3413decda7df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918203513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2918203513
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2419996659
Short name T742
Test name
Test status
Simulation time 33625281 ps
CPU time 0.59 seconds
Started Jul 10 04:49:56 PM PDT 24
Finished Jul 10 04:49:58 PM PDT 24
Peak memory 194240 kb
Host smart-764f90ce-2cde-47e9-985d-21550ac518b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419996659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2419996659
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3099939175
Short name T821
Test name
Test status
Simulation time 30019980 ps
CPU time 0.65 seconds
Started Jul 10 04:49:55 PM PDT 24
Finished Jul 10 04:49:57 PM PDT 24
Peak memory 194892 kb
Host smart-197fc96c-a3af-4f9b-b4d4-f198dfa6351e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099939175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3099939175
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3609557807
Short name T739
Test name
Test status
Simulation time 17642481 ps
CPU time 0.61 seconds
Started Jul 10 04:49:56 PM PDT 24
Finished Jul 10 04:49:58 PM PDT 24
Peak memory 194288 kb
Host smart-1cc29116-1877-4647-aa7a-5713405e185a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609557807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3609557807
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2106181269
Short name T780
Test name
Test status
Simulation time 26678251 ps
CPU time 0.62 seconds
Started Jul 10 04:49:56 PM PDT 24
Finished Jul 10 04:49:58 PM PDT 24
Peak memory 194876 kb
Host smart-dd42c7ea-a076-4f94-ba38-e0ef520fda22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106181269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2106181269
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.766352323
Short name T778
Test name
Test status
Simulation time 95679421 ps
CPU time 0.79 seconds
Started Jul 10 04:49:14 PM PDT 24
Finished Jul 10 04:49:15 PM PDT 24
Peak memory 196208 kb
Host smart-e6647171-f7d0-410a-a397-c7695478dc11
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766352323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.766352323
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1610157971
Short name T772
Test name
Test status
Simulation time 268715538 ps
CPU time 3.35 seconds
Started Jul 10 04:49:19 PM PDT 24
Finished Jul 10 04:49:23 PM PDT 24
Peak memory 198564 kb
Host smart-4f075f87-772e-45ee-a544-592bd45c42a7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610157971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1610157971
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3505278127
Short name T823
Test name
Test status
Simulation time 15216505 ps
CPU time 0.63 seconds
Started Jul 10 04:49:18 PM PDT 24
Finished Jul 10 04:49:20 PM PDT 24
Peak memory 195792 kb
Host smart-4680cf49-c4d5-4dc2-9f07-c88a110acc1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505278127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3505278127
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3589801962
Short name T776
Test name
Test status
Simulation time 20714731 ps
CPU time 0.99 seconds
Started Jul 10 04:49:12 PM PDT 24
Finished Jul 10 04:49:14 PM PDT 24
Peak memory 198472 kb
Host smart-91bd5fe5-58c3-4640-a51c-a5c737d3acf0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589801962 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3589801962
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2710432876
Short name T90
Test name
Test status
Simulation time 10982373 ps
CPU time 0.63 seconds
Started Jul 10 04:49:14 PM PDT 24
Finished Jul 10 04:49:15 PM PDT 24
Peak memory 195320 kb
Host smart-f6112afb-4799-4f71-a996-78ccd2c41dcd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710432876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2710432876
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.426667877
Short name T832
Test name
Test status
Simulation time 37428531 ps
CPU time 0.6 seconds
Started Jul 10 04:49:18 PM PDT 24
Finished Jul 10 04:49:19 PM PDT 24
Peak memory 194208 kb
Host smart-4f0a8694-880a-4e2e-8e8b-bd48944ace15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426667877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.426667877
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2301493145
Short name T803
Test name
Test status
Simulation time 54279781 ps
CPU time 0.85 seconds
Started Jul 10 04:49:14 PM PDT 24
Finished Jul 10 04:49:15 PM PDT 24
Peak memory 196936 kb
Host smart-44f02a33-ee9e-482c-868f-c806fdb7694c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301493145 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2301493145
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1439246947
Short name T769
Test name
Test status
Simulation time 87942016 ps
CPU time 2.06 seconds
Started Jul 10 04:49:21 PM PDT 24
Finished Jul 10 04:49:24 PM PDT 24
Peak memory 198924 kb
Host smart-54c9aa26-b7bc-4004-8cd8-620c4d33b558
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439246947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1439246947
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2809089487
Short name T44
Test name
Test status
Simulation time 135154399 ps
CPU time 1.16 seconds
Started Jul 10 04:49:18 PM PDT 24
Finished Jul 10 04:49:20 PM PDT 24
Peak memory 198636 kb
Host smart-712bec53-6543-45db-b212-c820aedde699
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809089487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2809089487
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1268177344
Short name T806
Test name
Test status
Simulation time 49071132 ps
CPU time 0.58 seconds
Started Jul 10 04:49:55 PM PDT 24
Finished Jul 10 04:49:57 PM PDT 24
Peak memory 194200 kb
Host smart-8b8ef2e9-cf82-4fd3-b795-cb6f1b037720
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268177344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1268177344
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3525029974
Short name T749
Test name
Test status
Simulation time 75303651 ps
CPU time 0.6 seconds
Started Jul 10 04:49:56 PM PDT 24
Finished Jul 10 04:49:58 PM PDT 24
Peak memory 194900 kb
Host smart-5035d813-a3d5-4b94-810f-db08e432c017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525029974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3525029974
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1457548081
Short name T761
Test name
Test status
Simulation time 24484305 ps
CPU time 0.59 seconds
Started Jul 10 04:49:57 PM PDT 24
Finished Jul 10 04:49:59 PM PDT 24
Peak memory 194876 kb
Host smart-30f88119-05e1-4bd5-928c-5cdd92076507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457548081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1457548081
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2260624063
Short name T763
Test name
Test status
Simulation time 107858018 ps
CPU time 0.59 seconds
Started Jul 10 04:49:56 PM PDT 24
Finished Jul 10 04:49:58 PM PDT 24
Peak memory 194200 kb
Host smart-1d6538e7-4d2d-41f1-a3f1-db0ed38ac6a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260624063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2260624063
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2089175178
Short name T743
Test name
Test status
Simulation time 27506009 ps
CPU time 0.56 seconds
Started Jul 10 04:50:00 PM PDT 24
Finished Jul 10 04:50:02 PM PDT 24
Peak memory 194160 kb
Host smart-3f393251-744a-417f-9345-d7a87310ae97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089175178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2089175178
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1566377360
Short name T738
Test name
Test status
Simulation time 13057481 ps
CPU time 0.58 seconds
Started Jul 10 04:49:59 PM PDT 24
Finished Jul 10 04:50:01 PM PDT 24
Peak memory 194196 kb
Host smart-61ae9acf-b9ba-4efb-9fb3-cbd701713b1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566377360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1566377360
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.14923914
Short name T800
Test name
Test status
Simulation time 15431369 ps
CPU time 0.61 seconds
Started Jul 10 04:49:57 PM PDT 24
Finished Jul 10 04:49:59 PM PDT 24
Peak memory 195040 kb
Host smart-468ac173-a974-4526-bbbc-23a8066f335e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14923914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.14923914
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3230909055
Short name T764
Test name
Test status
Simulation time 14347897 ps
CPU time 0.62 seconds
Started Jul 10 04:50:04 PM PDT 24
Finished Jul 10 04:50:06 PM PDT 24
Peak memory 194192 kb
Host smart-b64b2d49-0924-4b79-a407-d934f23118bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230909055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3230909055
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2685907105
Short name T846
Test name
Test status
Simulation time 167260559 ps
CPU time 0.59 seconds
Started Jul 10 04:50:03 PM PDT 24
Finished Jul 10 04:50:05 PM PDT 24
Peak memory 194468 kb
Host smart-6aedeedc-bafe-465c-877c-92980984ad08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685907105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2685907105
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3906675052
Short name T843
Test name
Test status
Simulation time 31693196 ps
CPU time 0.63 seconds
Started Jul 10 04:50:03 PM PDT 24
Finished Jul 10 04:50:05 PM PDT 24
Peak memory 194956 kb
Host smart-d1e1e323-32bf-4377-b1dd-f308f7bed938
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906675052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3906675052
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.289092294
Short name T752
Test name
Test status
Simulation time 99819876 ps
CPU time 0.79 seconds
Started Jul 10 04:49:20 PM PDT 24
Finished Jul 10 04:49:21 PM PDT 24
Peak memory 198440 kb
Host smart-0c5ea149-1eeb-41d3-bcea-98c95351bb9e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289092294 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.289092294
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.87881316
Short name T790
Test name
Test status
Simulation time 11505154 ps
CPU time 0.69 seconds
Started Jul 10 04:49:19 PM PDT 24
Finished Jul 10 04:49:21 PM PDT 24
Peak memory 195580 kb
Host smart-169fe5f2-94a5-4933-bcfe-1d9ce804c004
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87881316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_c
sr_rw.87881316
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.909684376
Short name T735
Test name
Test status
Simulation time 18504820 ps
CPU time 0.58 seconds
Started Jul 10 04:49:19 PM PDT 24
Finished Jul 10 04:49:20 PM PDT 24
Peak memory 194192 kb
Host smart-a7adce3a-c961-4d46-a704-3837e2232a89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909684376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.909684376
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1412029549
Short name T84
Test name
Test status
Simulation time 64545183 ps
CPU time 0.76 seconds
Started Jul 10 04:49:17 PM PDT 24
Finished Jul 10 04:49:18 PM PDT 24
Peak memory 196564 kb
Host smart-d137dabb-2eec-43a6-9a59-6373427f40c3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412029549 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1412029549
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3100587705
Short name T818
Test name
Test status
Simulation time 172449084 ps
CPU time 3.44 seconds
Started Jul 10 04:49:18 PM PDT 24
Finished Jul 10 04:49:22 PM PDT 24
Peak memory 198640 kb
Host smart-c1250ce8-89c7-44ea-a231-b921edc8b9c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100587705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3100587705
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3266320086
Short name T799
Test name
Test status
Simulation time 65017849 ps
CPU time 0.85 seconds
Started Jul 10 04:49:20 PM PDT 24
Finished Jul 10 04:49:22 PM PDT 24
Peak memory 197748 kb
Host smart-1dbaf5fa-bff9-43ad-af24-f7e388c94c86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266320086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3266320086
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1066432373
Short name T779
Test name
Test status
Simulation time 63955673 ps
CPU time 0.96 seconds
Started Jul 10 04:49:25 PM PDT 24
Finished Jul 10 04:49:27 PM PDT 24
Peak memory 198472 kb
Host smart-5209990c-3ca9-4cbe-80c6-75cdecbaa75d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066432373 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1066432373
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3389508223
Short name T824
Test name
Test status
Simulation time 43592202 ps
CPU time 0.63 seconds
Started Jul 10 04:49:19 PM PDT 24
Finished Jul 10 04:49:21 PM PDT 24
Peak memory 195732 kb
Host smart-5f68ba36-c3e6-461f-b5d9-6f51b27314d2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389508223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3389508223
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.785073707
Short name T837
Test name
Test status
Simulation time 16135342 ps
CPU time 0.59 seconds
Started Jul 10 04:49:25 PM PDT 24
Finished Jul 10 04:49:26 PM PDT 24
Peak memory 194216 kb
Host smart-746f81f4-871c-413f-ab15-605474959402
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785073707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.785073707
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.4213757925
Short name T101
Test name
Test status
Simulation time 30502854 ps
CPU time 0.65 seconds
Started Jul 10 04:49:25 PM PDT 24
Finished Jul 10 04:49:27 PM PDT 24
Peak memory 196028 kb
Host smart-118f9e00-2266-463c-9950-0ccc3b2d9806
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213757925 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.4213757925
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.4066310440
Short name T728
Test name
Test status
Simulation time 171071975 ps
CPU time 3.29 seconds
Started Jul 10 04:49:31 PM PDT 24
Finished Jul 10 04:49:35 PM PDT 24
Peak memory 198900 kb
Host smart-28a49a61-82ba-4058-a991-4511ac769b88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066310440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.4066310440
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.928746711
Short name T817
Test name
Test status
Simulation time 72342273 ps
CPU time 0.83 seconds
Started Jul 10 04:49:26 PM PDT 24
Finished Jul 10 04:49:28 PM PDT 24
Peak memory 198256 kb
Host smart-c3bdfcff-3d9c-4569-88f9-451b048a1e4b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928746711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.928746711
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.640514475
Short name T791
Test name
Test status
Simulation time 135885012 ps
CPU time 1.53 seconds
Started Jul 10 04:49:27 PM PDT 24
Finished Jul 10 04:49:29 PM PDT 24
Peak memory 198676 kb
Host smart-938919e4-3471-44d0-bb96-2777fe09ea78
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640514475 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.640514475
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.806811173
Short name T92
Test name
Test status
Simulation time 47353798 ps
CPU time 0.61 seconds
Started Jul 10 04:49:26 PM PDT 24
Finished Jul 10 04:49:28 PM PDT 24
Peak memory 195440 kb
Host smart-f2ab8d40-2ab3-4dd1-9a36-93a5a9495de2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806811173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_
csr_rw.806811173
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2956317595
Short name T836
Test name
Test status
Simulation time 15082684 ps
CPU time 0.61 seconds
Started Jul 10 04:49:25 PM PDT 24
Finished Jul 10 04:49:27 PM PDT 24
Peak memory 194260 kb
Host smart-06639ad3-2ca3-4a25-a21e-3d1b5d71b43c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956317595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2956317595
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3158076688
Short name T845
Test name
Test status
Simulation time 36767408 ps
CPU time 0.81 seconds
Started Jul 10 04:49:28 PM PDT 24
Finished Jul 10 04:49:29 PM PDT 24
Peak memory 196976 kb
Host smart-738565ac-98db-4165-acb3-9249a43d38f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158076688 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3158076688
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2312566508
Short name T729
Test name
Test status
Simulation time 2212765130 ps
CPU time 2.86 seconds
Started Jul 10 04:49:27 PM PDT 24
Finished Jul 10 04:49:31 PM PDT 24
Peak memory 198596 kb
Host smart-ac8f18ab-9aa8-4294-b4d1-32034cd9b6d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312566508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2312566508
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.4141492057
Short name T844
Test name
Test status
Simulation time 75261126 ps
CPU time 0.83 seconds
Started Jul 10 04:49:25 PM PDT 24
Finished Jul 10 04:49:27 PM PDT 24
Peak memory 197424 kb
Host smart-d986c7dd-628c-4dbe-9a6b-e5374a99ce71
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141492057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.4141492057
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.362899725
Short name T733
Test name
Test status
Simulation time 65581133 ps
CPU time 1.34 seconds
Started Jul 10 04:49:31 PM PDT 24
Finished Jul 10 04:49:34 PM PDT 24
Peak memory 198580 kb
Host smart-fdf639cb-69ce-477d-8e4c-c4d137dfd20b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362899725 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.362899725
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.648241538
Short name T98
Test name
Test status
Simulation time 15208021 ps
CPU time 0.61 seconds
Started Jul 10 04:49:25 PM PDT 24
Finished Jul 10 04:49:27 PM PDT 24
Peak memory 195084 kb
Host smart-665668b2-9325-4bdf-b9f2-c78dbd13fb50
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648241538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.648241538
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3633070630
Short name T726
Test name
Test status
Simulation time 12602280 ps
CPU time 0.59 seconds
Started Jul 10 04:49:32 PM PDT 24
Finished Jul 10 04:49:35 PM PDT 24
Peak memory 194848 kb
Host smart-a0af2d99-bcab-4750-bb36-ede2bc28c739
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633070630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3633070630
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3442523014
Short name T103
Test name
Test status
Simulation time 31719155 ps
CPU time 0.7 seconds
Started Jul 10 04:49:32 PM PDT 24
Finished Jul 10 04:49:35 PM PDT 24
Peak memory 196480 kb
Host smart-3a54d407-0fdd-4775-bd27-a212553abd46
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442523014 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3442523014
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.453875414
Short name T841
Test name
Test status
Simulation time 145190990 ps
CPU time 2.49 seconds
Started Jul 10 04:49:32 PM PDT 24
Finished Jul 10 04:49:36 PM PDT 24
Peak memory 198560 kb
Host smart-a80c1f28-ded0-4f8e-9555-7f8e1418e870
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453875414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.453875414
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1147327942
Short name T785
Test name
Test status
Simulation time 192547041 ps
CPU time 0.91 seconds
Started Jul 10 04:49:31 PM PDT 24
Finished Jul 10 04:49:34 PM PDT 24
Peak memory 197628 kb
Host smart-e7f0d127-4f53-42fe-9d80-4e2761a97cc1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147327942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1147327942
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1075758210
Short name T813
Test name
Test status
Simulation time 65887524 ps
CPU time 0.95 seconds
Started Jul 10 04:49:33 PM PDT 24
Finished Jul 10 04:49:35 PM PDT 24
Peak memory 198496 kb
Host smart-5515f2de-4606-4bdc-a998-e9396e6ff773
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075758210 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1075758210
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3620673684
Short name T99
Test name
Test status
Simulation time 42034280 ps
CPU time 0.61 seconds
Started Jul 10 04:49:35 PM PDT 24
Finished Jul 10 04:49:36 PM PDT 24
Peak memory 193876 kb
Host smart-7c9aa531-bbd2-4b54-a4be-c4f9530e5ffa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620673684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3620673684
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2278484937
Short name T789
Test name
Test status
Simulation time 64535097 ps
CPU time 0.63 seconds
Started Jul 10 04:49:30 PM PDT 24
Finished Jul 10 04:49:31 PM PDT 24
Peak memory 194944 kb
Host smart-671e7f58-cab2-42d6-a4e2-bd04caf8a232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278484937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2278484937
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.381493267
Short name T786
Test name
Test status
Simulation time 33873218 ps
CPU time 0.89 seconds
Started Jul 10 04:49:33 PM PDT 24
Finished Jul 10 04:49:35 PM PDT 24
Peak memory 196716 kb
Host smart-6b291ff1-2708-47fd-bd0e-110b84cf6875
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381493267 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.381493267
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.714086510
Short name T760
Test name
Test status
Simulation time 39179137 ps
CPU time 1.17 seconds
Started Jul 10 04:49:32 PM PDT 24
Finished Jul 10 04:49:35 PM PDT 24
Peak memory 198588 kb
Host smart-f6134447-7741-4f16-984d-b6c174c00aca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714086510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.714086510
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2917741758
Short name T33
Test name
Test status
Simulation time 1312465427 ps
CPU time 1.38 seconds
Started Jul 10 04:49:35 PM PDT 24
Finished Jul 10 04:49:37 PM PDT 24
Peak memory 198204 kb
Host smart-eb8d6b56-f69c-4fa7-a548-65c9a66a76af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917741758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2917741758
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1244376002
Short name T541
Test name
Test status
Simulation time 22628580 ps
CPU time 0.55 seconds
Started Jul 10 05:33:46 PM PDT 24
Finished Jul 10 05:33:47 PM PDT 24
Peak memory 194696 kb
Host smart-ecc67804-4cd6-4a61-accc-facddd52e732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244376002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1244376002
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1703598392
Short name T535
Test name
Test status
Simulation time 42220888 ps
CPU time 0.79 seconds
Started Jul 10 05:33:29 PM PDT 24
Finished Jul 10 05:33:31 PM PDT 24
Peak memory 195928 kb
Host smart-05475fe8-e5de-4581-b833-a941a3715cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703598392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1703598392
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.4100149261
Short name T707
Test name
Test status
Simulation time 285606995 ps
CPU time 8.97 seconds
Started Jul 10 05:33:34 PM PDT 24
Finished Jul 10 05:33:44 PM PDT 24
Peak memory 197312 kb
Host smart-980e4f89-dbc0-4b5f-98bc-d48feecbb111
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100149261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.4100149261
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.668561912
Short name T490
Test name
Test status
Simulation time 82035856 ps
CPU time 0.72 seconds
Started Jul 10 05:33:35 PM PDT 24
Finished Jul 10 05:33:36 PM PDT 24
Peak memory 197140 kb
Host smart-38c528dc-c7e5-489e-9ba4-aacecefbe05e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668561912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.668561912
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2224616512
Short name T63
Test name
Test status
Simulation time 54351771 ps
CPU time 0.99 seconds
Started Jul 10 05:33:35 PM PDT 24
Finished Jul 10 05:33:36 PM PDT 24
Peak memory 196476 kb
Host smart-78d033da-69f7-4453-821c-a9e87a901e7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224616512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2224616512
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3349630390
Short name T637
Test name
Test status
Simulation time 248557535 ps
CPU time 2.81 seconds
Started Jul 10 05:33:36 PM PDT 24
Finished Jul 10 05:33:39 PM PDT 24
Peak memory 198784 kb
Host smart-0fc385af-cc48-4921-8876-8fd6a73033f3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349630390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3349630390
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1408877831
Short name T157
Test name
Test status
Simulation time 224693316 ps
CPU time 1.6 seconds
Started Jul 10 05:33:35 PM PDT 24
Finished Jul 10 05:33:37 PM PDT 24
Peak memory 196724 kb
Host smart-f96194a1-79e5-4219-9f64-ed3799eac3c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408877831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1408877831
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.289689503
Short name T191
Test name
Test status
Simulation time 22785534 ps
CPU time 0.73 seconds
Started Jul 10 05:33:29 PM PDT 24
Finished Jul 10 05:33:31 PM PDT 24
Peak memory 196760 kb
Host smart-6307014f-1680-4bbf-aea0-08b51040de39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289689503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.289689503
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.209417922
Short name T523
Test name
Test status
Simulation time 130150292 ps
CPU time 1.23 seconds
Started Jul 10 05:33:31 PM PDT 24
Finished Jul 10 05:33:33 PM PDT 24
Peak memory 197268 kb
Host smart-31b53329-957a-4288-87a4-1d859836bc2e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209417922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.209417922
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2335287507
Short name T152
Test name
Test status
Simulation time 84032016 ps
CPU time 3.93 seconds
Started Jul 10 05:33:35 PM PDT 24
Finished Jul 10 05:33:39 PM PDT 24
Peak memory 198576 kb
Host smart-2716aa03-4cbe-4783-b996-37e8980a879e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335287507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2335287507
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.497398935
Short name T37
Test name
Test status
Simulation time 595537150 ps
CPU time 0.82 seconds
Started Jul 10 05:33:35 PM PDT 24
Finished Jul 10 05:33:36 PM PDT 24
Peak memory 214188 kb
Host smart-c7bc2d50-6f50-4b2f-a95e-b1d2cc2efe0a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497398935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.497398935
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.959787671
Short name T307
Test name
Test status
Simulation time 39935820 ps
CPU time 0.97 seconds
Started Jul 10 05:33:30 PM PDT 24
Finished Jul 10 05:33:31 PM PDT 24
Peak memory 197068 kb
Host smart-46ee4a4a-1040-4f19-ad69-3c7980e1991f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959787671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.959787671
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3796498214
Short name T271
Test name
Test status
Simulation time 373002689 ps
CPU time 1.43 seconds
Started Jul 10 05:33:29 PM PDT 24
Finished Jul 10 05:33:31 PM PDT 24
Peak memory 197364 kb
Host smart-3c868209-1e3e-49ec-8a57-a8653e5c36e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796498214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3796498214
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2152472946
Short name T601
Test name
Test status
Simulation time 5395025171 ps
CPU time 93.11 seconds
Started Jul 10 05:33:35 PM PDT 24
Finished Jul 10 05:35:09 PM PDT 24
Peak memory 198780 kb
Host smart-b49daf6a-950f-45a2-9e63-6f1c4661c534
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152472946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2152472946
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.3713444313
Short name T60
Test name
Test status
Simulation time 1860654734202 ps
CPU time 2998.16 seconds
Started Jul 10 05:33:36 PM PDT 24
Finished Jul 10 06:23:35 PM PDT 24
Peak memory 198904 kb
Host smart-d93367c5-bb78-4c65-8023-abd18176f539
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3713444313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.3713444313
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1939746796
Short name T358
Test name
Test status
Simulation time 16514397 ps
CPU time 0.64 seconds
Started Jul 10 05:33:59 PM PDT 24
Finished Jul 10 05:34:00 PM PDT 24
Peak memory 195284 kb
Host smart-77f6307a-6c48-41df-b21c-1151a4c0dd93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939746796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1939746796
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3997860339
Short name T415
Test name
Test status
Simulation time 41804664 ps
CPU time 0.86 seconds
Started Jul 10 05:33:47 PM PDT 24
Finished Jul 10 05:33:49 PM PDT 24
Peak memory 196896 kb
Host smart-fa458847-ed07-4c2e-be45-d892dcb12135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997860339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3997860339
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1066532382
Short name T578
Test name
Test status
Simulation time 657860437 ps
CPU time 22.48 seconds
Started Jul 10 05:33:49 PM PDT 24
Finished Jul 10 05:34:12 PM PDT 24
Peak memory 197440 kb
Host smart-1ad51bad-9f7b-4ea5-9387-7979746c8092
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066532382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1066532382
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2205420627
Short name T20
Test name
Test status
Simulation time 191682642 ps
CPU time 0.9 seconds
Started Jul 10 05:33:46 PM PDT 24
Finished Jul 10 05:33:47 PM PDT 24
Peak memory 197384 kb
Host smart-b5021ebb-0235-4974-a981-d145f03a4e18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205420627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2205420627
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1816807951
Short name T296
Test name
Test status
Simulation time 146292460 ps
CPU time 1.19 seconds
Started Jul 10 05:33:47 PM PDT 24
Finished Jul 10 05:33:49 PM PDT 24
Peak memory 196776 kb
Host smart-1a95aa1a-8924-42c1-9138-9656ed673909
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816807951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1816807951
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.427618445
Short name T263
Test name
Test status
Simulation time 147187494 ps
CPU time 1.22 seconds
Started Jul 10 05:33:47 PM PDT 24
Finished Jul 10 05:33:49 PM PDT 24
Peak memory 197264 kb
Host smart-f1fa77b2-56f4-4a69-b380-b030e128e9c6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427618445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.427618445
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.299990240
Short name T162
Test name
Test status
Simulation time 112532486 ps
CPU time 3.76 seconds
Started Jul 10 05:33:47 PM PDT 24
Finished Jul 10 05:33:52 PM PDT 24
Peak memory 197556 kb
Host smart-7527e7da-40d7-4de5-9fbe-5b7ebf679fee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299990240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.299990240
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.340287630
Short name T277
Test name
Test status
Simulation time 73768077 ps
CPU time 1.34 seconds
Started Jul 10 05:33:47 PM PDT 24
Finished Jul 10 05:33:49 PM PDT 24
Peak memory 197604 kb
Host smart-d4355ae0-008e-4db6-855a-077579a53f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340287630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.340287630
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.4096546039
Short name T301
Test name
Test status
Simulation time 29522811 ps
CPU time 1.1 seconds
Started Jul 10 05:33:48 PM PDT 24
Finished Jul 10 05:33:50 PM PDT 24
Peak memory 196480 kb
Host smart-23c8dc31-bd55-448e-a810-a05bf00c79dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096546039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.4096546039
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3922735375
Short name T547
Test name
Test status
Simulation time 280001008 ps
CPU time 3.55 seconds
Started Jul 10 05:33:46 PM PDT 24
Finished Jul 10 05:33:50 PM PDT 24
Peak memory 198672 kb
Host smart-c2e06af4-aca9-4536-baa1-0b495d827d2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922735375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3922735375
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.371677667
Short name T48
Test name
Test status
Simulation time 204245803 ps
CPU time 0.9 seconds
Started Jul 10 05:33:56 PM PDT 24
Finished Jul 10 05:33:58 PM PDT 24
Peak memory 214352 kb
Host smart-0f43ce77-8750-4c90-9647-d94218c2ee08
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371677667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.371677667
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2302349799
Short name T262
Test name
Test status
Simulation time 35687854 ps
CPU time 1.06 seconds
Started Jul 10 05:33:47 PM PDT 24
Finished Jul 10 05:33:49 PM PDT 24
Peak memory 196560 kb
Host smart-0333efb5-8c03-4fd6-96a4-537ed5707581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302349799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2302349799
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2000768536
Short name T120
Test name
Test status
Simulation time 341911498 ps
CPU time 1 seconds
Started Jul 10 05:33:47 PM PDT 24
Finished Jul 10 05:33:49 PM PDT 24
Peak memory 196928 kb
Host smart-a53d718f-4658-4584-8a11-1592c6e87d35
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000768536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2000768536
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.332546033
Short name T550
Test name
Test status
Simulation time 113013471713 ps
CPU time 226.92 seconds
Started Jul 10 05:33:47 PM PDT 24
Finished Jul 10 05:37:35 PM PDT 24
Peak memory 198784 kb
Host smart-08df05a0-2a6e-44e0-876d-b7ff928c59d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332546033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.332546033
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.468387510
Short name T571
Test name
Test status
Simulation time 172417882261 ps
CPU time 1257.38 seconds
Started Jul 10 05:33:59 PM PDT 24
Finished Jul 10 05:54:57 PM PDT 24
Peak memory 198880 kb
Host smart-15688b39-1731-4e50-a0a8-70e8ae42f98f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=468387510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.468387510
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1090070377
Short name T684
Test name
Test status
Simulation time 42291140 ps
CPU time 0.59 seconds
Started Jul 10 05:35:17 PM PDT 24
Finished Jul 10 05:35:19 PM PDT 24
Peak memory 194644 kb
Host smart-a328ab54-9521-447e-b4af-240ea6a12092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090070377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1090070377
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.460763256
Short name T68
Test name
Test status
Simulation time 49186170 ps
CPU time 0.85 seconds
Started Jul 10 05:35:24 PM PDT 24
Finished Jul 10 05:35:26 PM PDT 24
Peak memory 195996 kb
Host smart-ce76ea44-bbb6-4dc5-a7ee-11f143386426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460763256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.460763256
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.4088443695
Short name T139
Test name
Test status
Simulation time 2572231602 ps
CPU time 18.21 seconds
Started Jul 10 05:35:12 PM PDT 24
Finished Jul 10 05:35:31 PM PDT 24
Peak memory 198068 kb
Host smart-3289ae9e-3cfe-4e14-a42b-47e06a561d3e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088443695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.4088443695
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2131487523
Short name T297
Test name
Test status
Simulation time 50818740 ps
CPU time 0.69 seconds
Started Jul 10 05:35:19 PM PDT 24
Finished Jul 10 05:35:21 PM PDT 24
Peak memory 195220 kb
Host smart-00a2ffcf-ea0a-4c96-9b22-b5f54de4425d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131487523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2131487523
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3259892199
Short name T64
Test name
Test status
Simulation time 50707851 ps
CPU time 0.93 seconds
Started Jul 10 05:35:13 PM PDT 24
Finished Jul 10 05:35:14 PM PDT 24
Peak memory 197464 kb
Host smart-74241bd4-903d-4bb8-a6cc-febc0173014f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259892199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3259892199
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1134114430
Short name T557
Test name
Test status
Simulation time 92659427 ps
CPU time 3.81 seconds
Started Jul 10 05:35:24 PM PDT 24
Finished Jul 10 05:35:29 PM PDT 24
Peak memory 198704 kb
Host smart-6314894a-b562-4fa2-974b-3b55e604cd51
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134114430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1134114430
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1952036083
Short name T424
Test name
Test status
Simulation time 705320523 ps
CPU time 3.17 seconds
Started Jul 10 05:35:13 PM PDT 24
Finished Jul 10 05:35:18 PM PDT 24
Peak memory 198688 kb
Host smart-7829c591-42f2-433c-b581-44d2429cb972
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952036083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1952036083
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3173170623
Short name T633
Test name
Test status
Simulation time 21128630 ps
CPU time 0.97 seconds
Started Jul 10 05:35:24 PM PDT 24
Finished Jul 10 05:35:26 PM PDT 24
Peak memory 197224 kb
Host smart-6bc4fee4-f4ae-4c51-bfc5-f6b9f283651f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173170623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3173170623
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2113493524
Short name T672
Test name
Test status
Simulation time 33367005 ps
CPU time 1.24 seconds
Started Jul 10 05:35:14 PM PDT 24
Finished Jul 10 05:35:16 PM PDT 24
Peak memory 198712 kb
Host smart-86cb7d7b-cf1b-48c8-9c8b-692d7e9a65d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113493524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2113493524
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3471274084
Short name T17
Test name
Test status
Simulation time 145568143 ps
CPU time 2.87 seconds
Started Jul 10 05:35:19 PM PDT 24
Finished Jul 10 05:35:24 PM PDT 24
Peak memory 198636 kb
Host smart-1bf830a2-d1dc-4d04-b440-636ccdfce722
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471274084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3471274084
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3546442782
Short name T206
Test name
Test status
Simulation time 207894020 ps
CPU time 1.55 seconds
Started Jul 10 05:35:24 PM PDT 24
Finished Jul 10 05:35:26 PM PDT 24
Peak memory 197444 kb
Host smart-819e94ea-3dc4-48c0-8d81-1136725ae0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546442782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3546442782
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2245397819
Short name T719
Test name
Test status
Simulation time 70613466 ps
CPU time 1.36 seconds
Started Jul 10 05:35:23 PM PDT 24
Finished Jul 10 05:35:26 PM PDT 24
Peak memory 197416 kb
Host smart-76ef33c9-78c2-47e8-820d-ccec91d8f1a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245397819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2245397819
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.489373351
Short name T338
Test name
Test status
Simulation time 3402149266 ps
CPU time 49.83 seconds
Started Jul 10 05:35:24 PM PDT 24
Finished Jul 10 05:36:15 PM PDT 24
Peak memory 198780 kb
Host smart-6a350437-1f36-4afe-9bf6-6712e06b5c61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489373351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.489373351
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2937904248
Short name T674
Test name
Test status
Simulation time 34437728 ps
CPU time 0.58 seconds
Started Jul 10 05:35:26 PM PDT 24
Finished Jul 10 05:35:28 PM PDT 24
Peak memory 194636 kb
Host smart-c672ca51-b4e0-4747-9b3e-065fa5b8ba1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937904248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2937904248
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2751864931
Short name T149
Test name
Test status
Simulation time 230223769 ps
CPU time 0.85 seconds
Started Jul 10 05:35:18 PM PDT 24
Finished Jul 10 05:35:20 PM PDT 24
Peak memory 197160 kb
Host smart-09180b10-d00b-477f-a152-89e4df778c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751864931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2751864931
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2704320269
Short name T654
Test name
Test status
Simulation time 477418703 ps
CPU time 23.21 seconds
Started Jul 10 05:35:17 PM PDT 24
Finished Jul 10 05:35:42 PM PDT 24
Peak memory 197656 kb
Host smart-9c1cab54-5f19-4db0-9357-a708cf3ab307
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704320269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2704320269
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.376670907
Short name T167
Test name
Test status
Simulation time 238442236 ps
CPU time 0.98 seconds
Started Jul 10 05:35:27 PM PDT 24
Finished Jul 10 05:35:29 PM PDT 24
Peak memory 197868 kb
Host smart-c42de5b5-ffba-4064-a2ae-36e0c1a45f65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376670907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.376670907
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.20373602
Short name T164
Test name
Test status
Simulation time 80280694 ps
CPU time 1.07 seconds
Started Jul 10 05:35:19 PM PDT 24
Finished Jul 10 05:35:22 PM PDT 24
Peak memory 196480 kb
Host smart-48825584-e7fc-4cf2-a446-92093cac43bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20373602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.20373602
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1496727287
Short name T232
Test name
Test status
Simulation time 105896271 ps
CPU time 1.23 seconds
Started Jul 10 05:35:24 PM PDT 24
Finished Jul 10 05:35:26 PM PDT 24
Peak memory 197348 kb
Host smart-6185897c-851f-4ed1-9cd2-1fae07119d92
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496727287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1496727287
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.259946848
Short name T691
Test name
Test status
Simulation time 156313059 ps
CPU time 1.04 seconds
Started Jul 10 05:35:17 PM PDT 24
Finished Jul 10 05:35:20 PM PDT 24
Peak memory 196868 kb
Host smart-55ea5142-353d-49fc-b4d1-d96f2c0c8354
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259946848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
259946848
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3473688707
Short name T339
Test name
Test status
Simulation time 55729346 ps
CPU time 1.09 seconds
Started Jul 10 05:35:17 PM PDT 24
Finished Jul 10 05:35:19 PM PDT 24
Peak memory 196700 kb
Host smart-77967091-cfbe-4670-a677-76bf8a99ee2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473688707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3473688707
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3057675374
Short name T670
Test name
Test status
Simulation time 412756601 ps
CPU time 1.04 seconds
Started Jul 10 05:35:18 PM PDT 24
Finished Jul 10 05:35:21 PM PDT 24
Peak memory 197408 kb
Host smart-6c308beb-acc5-4b1d-9500-73d1cd4b3e8f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057675374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3057675374
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3739704372
Short name T10
Test name
Test status
Simulation time 3463888529 ps
CPU time 6.45 seconds
Started Jul 10 05:35:25 PM PDT 24
Finished Jul 10 05:35:33 PM PDT 24
Peak memory 198680 kb
Host smart-a34b3007-3905-4f7b-9f86-8b4b59673587
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739704372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3739704372
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.940583533
Short name T487
Test name
Test status
Simulation time 79014779 ps
CPU time 1.24 seconds
Started Jul 10 05:35:18 PM PDT 24
Finished Jul 10 05:35:21 PM PDT 24
Peak memory 197448 kb
Host smart-c4946245-e5c6-440b-a48d-00c9d3418b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940583533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.940583533
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3877287068
Short name T396
Test name
Test status
Simulation time 41932542 ps
CPU time 1.16 seconds
Started Jul 10 05:35:18 PM PDT 24
Finished Jul 10 05:35:20 PM PDT 24
Peak memory 196484 kb
Host smart-22343974-cdee-4b67-a602-4c0579e13a15
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877287068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3877287068
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.2225022948
Short name T378
Test name
Test status
Simulation time 5962695130 ps
CPU time 150.59 seconds
Started Jul 10 05:35:25 PM PDT 24
Finished Jul 10 05:37:57 PM PDT 24
Peak memory 198704 kb
Host smart-b4391fab-4402-4857-8fea-43096fae18e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225022948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2225022948
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2598759129
Short name T332
Test name
Test status
Simulation time 32215909 ps
CPU time 0.57 seconds
Started Jul 10 05:35:40 PM PDT 24
Finished Jul 10 05:35:41 PM PDT 24
Peak memory 194664 kb
Host smart-7da1e81c-d20c-4dd4-8198-085eb345efd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598759129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2598759129
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.269066985
Short name T588
Test name
Test status
Simulation time 271228267 ps
CPU time 0.65 seconds
Started Jul 10 05:35:30 PM PDT 24
Finished Jul 10 05:35:31 PM PDT 24
Peak memory 194676 kb
Host smart-53030ce3-4a8c-4005-8b1f-2ceb5b06ceb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269066985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.269066985
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1199223660
Short name T481
Test name
Test status
Simulation time 540436228 ps
CPU time 29.57 seconds
Started Jul 10 05:35:31 PM PDT 24
Finished Jul 10 05:36:01 PM PDT 24
Peak memory 197712 kb
Host smart-71c42173-8467-4423-87dc-bc2323e8bc31
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199223660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1199223660
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2000725630
Short name T385
Test name
Test status
Simulation time 243007450 ps
CPU time 0.75 seconds
Started Jul 10 05:35:32 PM PDT 24
Finished Jul 10 05:35:34 PM PDT 24
Peak memory 196084 kb
Host smart-cfc78445-db23-4232-bd6c-1755c94dc5e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000725630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2000725630
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2900459085
Short name T692
Test name
Test status
Simulation time 52793372 ps
CPU time 0.77 seconds
Started Jul 10 05:35:33 PM PDT 24
Finished Jul 10 05:35:35 PM PDT 24
Peak memory 196852 kb
Host smart-3493e350-aee4-41ee-a2f1-49729321b416
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900459085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2900459085
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.206890109
Short name T313
Test name
Test status
Simulation time 99651971 ps
CPU time 2.08 seconds
Started Jul 10 05:35:32 PM PDT 24
Finished Jul 10 05:35:35 PM PDT 24
Peak memory 198684 kb
Host smart-ae0bff9a-9ec1-4aa7-8493-3bf97785202e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206890109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.206890109
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2008965766
Short name T590
Test name
Test status
Simulation time 236303114 ps
CPU time 2.84 seconds
Started Jul 10 05:35:32 PM PDT 24
Finished Jul 10 05:35:36 PM PDT 24
Peak memory 198664 kb
Host smart-7776a203-f620-4d87-ae0d-fad6e6d859a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008965766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2008965766
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.514165427
Short name T512
Test name
Test status
Simulation time 33301572 ps
CPU time 0.84 seconds
Started Jul 10 05:35:24 PM PDT 24
Finished Jul 10 05:35:26 PM PDT 24
Peak memory 196184 kb
Host smart-7d16f1a6-e849-49ba-ba9d-6a72b5a11276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514165427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.514165427
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1030325638
Short name T143
Test name
Test status
Simulation time 125120390 ps
CPU time 1.14 seconds
Started Jul 10 05:35:27 PM PDT 24
Finished Jul 10 05:35:29 PM PDT 24
Peak memory 197504 kb
Host smart-e1b0a9ce-a67a-4404-9ab0-ccb2aaedf0e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030325638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1030325638
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1732832352
Short name T631
Test name
Test status
Simulation time 529428805 ps
CPU time 3.59 seconds
Started Jul 10 05:35:31 PM PDT 24
Finished Jul 10 05:35:35 PM PDT 24
Peak memory 198572 kb
Host smart-10270124-b31f-45fd-8b2f-b081126636c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732832352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1732832352
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3655440111
Short name T50
Test name
Test status
Simulation time 265520386 ps
CPU time 0.83 seconds
Started Jul 10 05:35:27 PM PDT 24
Finished Jul 10 05:35:29 PM PDT 24
Peak memory 196032 kb
Host smart-5cfa7ea4-ea98-4727-8378-a09dbf3191db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655440111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3655440111
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.4104281778
Short name T596
Test name
Test status
Simulation time 144912486 ps
CPU time 1.23 seconds
Started Jul 10 05:35:26 PM PDT 24
Finished Jul 10 05:35:28 PM PDT 24
Peak memory 197044 kb
Host smart-6bd21b55-085d-4efe-997c-31c7b5a92f64
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104281778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.4104281778
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1675489004
Short name T7
Test name
Test status
Simulation time 1994254207 ps
CPU time 24.46 seconds
Started Jul 10 05:35:32 PM PDT 24
Finished Jul 10 05:35:57 PM PDT 24
Peak memory 198704 kb
Host smart-3944b00c-0fdf-4bfd-b846-f8e7cf959e00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675489004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1675489004
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.853513967
Short name T356
Test name
Test status
Simulation time 64755805484 ps
CPU time 1510.71 seconds
Started Jul 10 05:35:32 PM PDT 24
Finished Jul 10 06:00:44 PM PDT 24
Peak memory 198872 kb
Host smart-3f33accc-6b2c-42da-ab41-e3456e0f6030
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=853513967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.853513967
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.4063061585
Short name T712
Test name
Test status
Simulation time 41880673 ps
CPU time 0.58 seconds
Started Jul 10 05:35:45 PM PDT 24
Finished Jul 10 05:35:47 PM PDT 24
Peak memory 194608 kb
Host smart-dbef853a-8e1c-40b9-ba9a-859093346678
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063061585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.4063061585
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2354703962
Short name T350
Test name
Test status
Simulation time 99039357 ps
CPU time 0.86 seconds
Started Jul 10 05:35:38 PM PDT 24
Finished Jul 10 05:35:40 PM PDT 24
Peak memory 196664 kb
Host smart-bb56799b-f051-4422-9920-7947fb6e73f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354703962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2354703962
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.4191385820
Short name T341
Test name
Test status
Simulation time 844080790 ps
CPU time 5.23 seconds
Started Jul 10 05:35:40 PM PDT 24
Finished Jul 10 05:35:46 PM PDT 24
Peak memory 197772 kb
Host smart-b0b1b42c-ab68-4766-b003-db38f7941249
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191385820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.4191385820
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3261118749
Short name T591
Test name
Test status
Simulation time 103354544 ps
CPU time 0.75 seconds
Started Jul 10 05:35:45 PM PDT 24
Finished Jul 10 05:35:47 PM PDT 24
Peak memory 197276 kb
Host smart-a6d6d3e8-3f13-47a9-8186-4ecdd165b30a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261118749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3261118749
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1694621579
Short name T127
Test name
Test status
Simulation time 222017624 ps
CPU time 1.1 seconds
Started Jul 10 05:35:38 PM PDT 24
Finished Jul 10 05:35:39 PM PDT 24
Peak memory 196648 kb
Host smart-bd83e422-ff59-418b-9214-0af28c6ebd0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694621579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1694621579
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2547413360
Short name T537
Test name
Test status
Simulation time 195355102 ps
CPU time 1.93 seconds
Started Jul 10 05:35:40 PM PDT 24
Finished Jul 10 05:35:43 PM PDT 24
Peak memory 198724 kb
Host smart-4acbebe9-685e-46fc-870d-ad3c68ecde15
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547413360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2547413360
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.66827948
Short name T281
Test name
Test status
Simulation time 88348776 ps
CPU time 0.94 seconds
Started Jul 10 05:35:38 PM PDT 24
Finished Jul 10 05:35:39 PM PDT 24
Peak memory 196236 kb
Host smart-681d5149-bff5-4494-a303-13c0c9aa4236
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66827948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.66827948
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2400857525
Short name T353
Test name
Test status
Simulation time 37073392 ps
CPU time 0.98 seconds
Started Jul 10 05:35:41 PM PDT 24
Finished Jul 10 05:35:42 PM PDT 24
Peak memory 197428 kb
Host smart-4a96569f-16d8-40ac-9a21-5830cc1d1861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400857525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2400857525
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.439120000
Short name T268
Test name
Test status
Simulation time 20865009 ps
CPU time 0.68 seconds
Started Jul 10 05:35:39 PM PDT 24
Finished Jul 10 05:35:41 PM PDT 24
Peak memory 194920 kb
Host smart-b7a116ed-7c8b-4c08-9978-f3f6c2b19a7e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439120000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.439120000
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3116458399
Short name T348
Test name
Test status
Simulation time 249263890 ps
CPU time 5.53 seconds
Started Jul 10 05:35:45 PM PDT 24
Finished Jul 10 05:35:51 PM PDT 24
Peak memory 198812 kb
Host smart-53b65aea-5238-41fb-8bca-60315103c1e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116458399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3116458399
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.29685313
Short name T492
Test name
Test status
Simulation time 700383292 ps
CPU time 1.37 seconds
Started Jul 10 05:35:31 PM PDT 24
Finished Jul 10 05:35:33 PM PDT 24
Peak memory 197436 kb
Host smart-40927781-a2a2-4ae6-bfb4-cc8e07291f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29685313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.29685313
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1092710444
Short name T176
Test name
Test status
Simulation time 40416477 ps
CPU time 0.98 seconds
Started Jul 10 05:35:31 PM PDT 24
Finished Jul 10 05:35:33 PM PDT 24
Peak memory 195856 kb
Host smart-33d87611-9b1a-4bee-b66f-98d579ddd946
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092710444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1092710444
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.3391265691
Short name T303
Test name
Test status
Simulation time 15159591332 ps
CPU time 157.89 seconds
Started Jul 10 05:35:45 PM PDT 24
Finished Jul 10 05:38:25 PM PDT 24
Peak memory 198692 kb
Host smart-5443a0bf-e8f8-460d-8bb3-e8e4df8f3b7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391265691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.3391265691
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.412656161
Short name T627
Test name
Test status
Simulation time 26081890 ps
CPU time 0.8 seconds
Started Jul 10 05:35:51 PM PDT 24
Finished Jul 10 05:35:53 PM PDT 24
Peak memory 197804 kb
Host smart-2c8cdd0e-cc7a-416d-a8bd-8e36f531c6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412656161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.412656161
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.858212537
Short name T347
Test name
Test status
Simulation time 2301575518 ps
CPU time 16.41 seconds
Started Jul 10 05:35:51 PM PDT 24
Finished Jul 10 05:36:09 PM PDT 24
Peak memory 197680 kb
Host smart-46871055-fe5d-48d8-9c50-610abf1af965
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858212537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.858212537
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.4123211296
Short name T423
Test name
Test status
Simulation time 61479788 ps
CPU time 0.7 seconds
Started Jul 10 05:35:53 PM PDT 24
Finished Jul 10 05:35:55 PM PDT 24
Peak memory 195296 kb
Host smart-2a18d131-8ac4-4ea4-8507-f00292aa4d84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123211296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.4123211296
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3811896944
Short name T133
Test name
Test status
Simulation time 475220804 ps
CPU time 1.14 seconds
Started Jul 10 05:35:51 PM PDT 24
Finished Jul 10 05:35:53 PM PDT 24
Peak memory 196808 kb
Host smart-da2cefa4-470d-421e-bb4d-2422b7c85615
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811896944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3811896944
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.789157214
Short name T308
Test name
Test status
Simulation time 57782189 ps
CPU time 2.47 seconds
Started Jul 10 05:35:49 PM PDT 24
Finished Jul 10 05:35:52 PM PDT 24
Peak memory 198724 kb
Host smart-7b8992ba-bf8b-4154-a589-5754d68bf9d4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789157214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.789157214
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1107505492
Short name T75
Test name
Test status
Simulation time 80103172 ps
CPU time 1.45 seconds
Started Jul 10 05:35:53 PM PDT 24
Finished Jul 10 05:35:56 PM PDT 24
Peak memory 196448 kb
Host smart-a38c4e43-e9c9-44a6-8200-cb8ed2a491d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107505492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1107505492
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3080411175
Short name T652
Test name
Test status
Simulation time 101416152 ps
CPU time 0.89 seconds
Started Jul 10 05:35:45 PM PDT 24
Finished Jul 10 05:35:47 PM PDT 24
Peak memory 196872 kb
Host smart-8fb60c66-45e5-4a91-844d-1de136ea1518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080411175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3080411175
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1859645467
Short name T113
Test name
Test status
Simulation time 27516616 ps
CPU time 0.76 seconds
Started Jul 10 05:35:51 PM PDT 24
Finished Jul 10 05:35:53 PM PDT 24
Peak memory 196064 kb
Host smart-51855270-cdc5-402a-80ad-f86dba5e540d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859645467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1859645467
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1314425876
Short name T283
Test name
Test status
Simulation time 110076822 ps
CPU time 2.12 seconds
Started Jul 10 05:35:49 PM PDT 24
Finished Jul 10 05:35:52 PM PDT 24
Peak memory 198592 kb
Host smart-158e8dc9-5c58-4673-9b19-acb789fee67a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314425876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1314425876
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1782997092
Short name T390
Test name
Test status
Simulation time 43363944 ps
CPU time 1.29 seconds
Started Jul 10 05:35:46 PM PDT 24
Finished Jul 10 05:35:49 PM PDT 24
Peak memory 196564 kb
Host smart-728d6610-1414-4853-987e-df564e99742b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782997092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1782997092
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.136272440
Short name T173
Test name
Test status
Simulation time 266811939 ps
CPU time 1.06 seconds
Started Jul 10 05:35:46 PM PDT 24
Finished Jul 10 05:35:48 PM PDT 24
Peak memory 196132 kb
Host smart-f74e6ae4-b43f-482c-a53b-1f8129336ebf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136272440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.136272440
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1097950451
Short name T364
Test name
Test status
Simulation time 4411276660 ps
CPU time 128.5 seconds
Started Jul 10 05:35:52 PM PDT 24
Finished Jul 10 05:38:02 PM PDT 24
Peak memory 198632 kb
Host smart-8d232be2-3227-499f-a17b-56a989918842
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097950451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1097950451
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.3664361288
Short name T426
Test name
Test status
Simulation time 252923911700 ps
CPU time 792.24 seconds
Started Jul 10 05:35:50 PM PDT 24
Finished Jul 10 05:49:03 PM PDT 24
Peak memory 198924 kb
Host smart-1bb39f85-ec48-4883-8e30-5eb9b6eeeacd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3664361288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.3664361288
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.4146745775
Short name T606
Test name
Test status
Simulation time 39791846 ps
CPU time 0.56 seconds
Started Jul 10 05:35:56 PM PDT 24
Finished Jul 10 05:35:57 PM PDT 24
Peak memory 194632 kb
Host smart-e88cad26-fd48-4d43-b7ef-b8e04aca32c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146745775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.4146745775
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2712447757
Short name T389
Test name
Test status
Simulation time 83236914 ps
CPU time 0.83 seconds
Started Jul 10 05:35:53 PM PDT 24
Finished Jul 10 05:35:55 PM PDT 24
Peak memory 196876 kb
Host smart-ece6c5b9-b5a5-46c3-a749-afce13a84a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712447757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2712447757
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2059438229
Short name T555
Test name
Test status
Simulation time 123511830 ps
CPU time 6.66 seconds
Started Jul 10 05:35:55 PM PDT 24
Finished Jul 10 05:36:02 PM PDT 24
Peak memory 197720 kb
Host smart-817560d1-3e70-4c10-af31-73d20943d664
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059438229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2059438229
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1231354550
Short name T507
Test name
Test status
Simulation time 357154622 ps
CPU time 1.2 seconds
Started Jul 10 05:35:56 PM PDT 24
Finished Jul 10 05:35:58 PM PDT 24
Peak memory 198476 kb
Host smart-603d8e8c-2895-40e1-a638-001c156428f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231354550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1231354550
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.1961256871
Short name T498
Test name
Test status
Simulation time 34343479 ps
CPU time 1.02 seconds
Started Jul 10 05:35:56 PM PDT 24
Finished Jul 10 05:35:58 PM PDT 24
Peak memory 196736 kb
Host smart-6fe24253-a5ac-42ae-866e-8b269ad2789f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961256871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.1961256871
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2648537986
Short name T711
Test name
Test status
Simulation time 83454885 ps
CPU time 1.82 seconds
Started Jul 10 05:35:56 PM PDT 24
Finished Jul 10 05:35:59 PM PDT 24
Peak memory 197120 kb
Host smart-3820c99c-ec8a-4ddb-b5c2-a108c94c136a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648537986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2648537986
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.4151425677
Short name T556
Test name
Test status
Simulation time 93234954 ps
CPU time 2.16 seconds
Started Jul 10 05:35:56 PM PDT 24
Finished Jul 10 05:35:58 PM PDT 24
Peak memory 198104 kb
Host smart-2b2dbe00-f69d-428e-a51c-c045d2f388a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151425677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.4151425677
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2534926114
Short name T677
Test name
Test status
Simulation time 38247394 ps
CPU time 0.89 seconds
Started Jul 10 05:35:54 PM PDT 24
Finished Jul 10 05:35:56 PM PDT 24
Peak memory 197316 kb
Host smart-a9e7fa98-4f4e-44cd-946d-35a2bf2276e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534926114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2534926114
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3689850350
Short name T636
Test name
Test status
Simulation time 83514346 ps
CPU time 0.78 seconds
Started Jul 10 05:35:57 PM PDT 24
Finished Jul 10 05:35:59 PM PDT 24
Peak memory 196732 kb
Host smart-b5a068ce-3e77-41e1-9348-301a53a0471a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689850350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3689850350
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.4269464928
Short name T12
Test name
Test status
Simulation time 580429107 ps
CPU time 5.66 seconds
Started Jul 10 05:35:58 PM PDT 24
Finished Jul 10 05:36:05 PM PDT 24
Peak memory 198588 kb
Host smart-349b9e6a-701f-424c-a69d-0c1619b21796
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269464928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.4269464928
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.594595926
Short name T302
Test name
Test status
Simulation time 29414171 ps
CPU time 0.81 seconds
Started Jul 10 05:35:51 PM PDT 24
Finished Jul 10 05:35:53 PM PDT 24
Peak memory 195860 kb
Host smart-6c6e7058-25e5-4584-9d80-d243e1651dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594595926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.594595926
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.918409843
Short name T374
Test name
Test status
Simulation time 161154622 ps
CPU time 1.54 seconds
Started Jul 10 05:35:50 PM PDT 24
Finished Jul 10 05:35:53 PM PDT 24
Peak memory 198704 kb
Host smart-0171ef08-b06f-4a11-be0f-c10e5237fa98
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918409843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.918409843
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.58741174
Short name T585
Test name
Test status
Simulation time 18359000995 ps
CPU time 571.43 seconds
Started Jul 10 05:35:57 PM PDT 24
Finished Jul 10 05:45:30 PM PDT 24
Peak memory 198892 kb
Host smart-e69a1cf9-b2c4-425b-8c46-ef480d6c5a10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=58741174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.58741174
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1089667369
Short name T340
Test name
Test status
Simulation time 18379473 ps
CPU time 0.58 seconds
Started Jul 10 05:36:02 PM PDT 24
Finished Jul 10 05:36:05 PM PDT 24
Peak memory 194652 kb
Host smart-1f8cd0fc-ef67-4f46-9f42-fdca9130127a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089667369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1089667369
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3580876914
Short name T480
Test name
Test status
Simulation time 209699516 ps
CPU time 0.69 seconds
Started Jul 10 05:36:02 PM PDT 24
Finished Jul 10 05:36:06 PM PDT 24
Peak memory 195432 kb
Host smart-704ce7c5-eed4-49ec-ba28-a4990a40abdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580876914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3580876914
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2977443462
Short name T721
Test name
Test status
Simulation time 3851371879 ps
CPU time 27.58 seconds
Started Jul 10 05:36:00 PM PDT 24
Finished Jul 10 05:36:29 PM PDT 24
Peak memory 197520 kb
Host smart-e5c5f706-2300-4cc6-8793-c5d91c11920a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977443462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2977443462
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.4229031985
Short name T660
Test name
Test status
Simulation time 998412307 ps
CPU time 1.05 seconds
Started Jul 10 05:36:02 PM PDT 24
Finished Jul 10 05:36:04 PM PDT 24
Peak memory 198468 kb
Host smart-256ef8e8-682a-47a1-9dd4-e794655f832e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229031985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.4229031985
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3712056445
Short name T708
Test name
Test status
Simulation time 24075501 ps
CPU time 0.7 seconds
Started Jul 10 05:36:02 PM PDT 24
Finished Jul 10 05:36:05 PM PDT 24
Peak memory 194956 kb
Host smart-26c1988a-fef7-4285-8f0a-9178dd8d284f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712056445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3712056445
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1258547830
Short name T603
Test name
Test status
Simulation time 28330045 ps
CPU time 1.22 seconds
Started Jul 10 05:36:03 PM PDT 24
Finished Jul 10 05:36:07 PM PDT 24
Peak memory 197900 kb
Host smart-a8d83a29-aa54-40ce-98a0-52fe26148e3f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258547830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1258547830
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.4286596980
Short name T455
Test name
Test status
Simulation time 278419545 ps
CPU time 2.77 seconds
Started Jul 10 05:36:03 PM PDT 24
Finished Jul 10 05:36:09 PM PDT 24
Peak memory 197580 kb
Host smart-0c5d76a8-fcb6-4717-ac91-cf31ad665482
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286596980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.4286596980
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3661419440
Short name T398
Test name
Test status
Simulation time 473257897 ps
CPU time 0.84 seconds
Started Jul 10 05:36:00 PM PDT 24
Finished Jul 10 05:36:02 PM PDT 24
Peak memory 196800 kb
Host smart-6d048470-8c9c-4837-8153-6a8f7270cc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661419440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3661419440
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3000748980
Short name T379
Test name
Test status
Simulation time 99745021 ps
CPU time 1.22 seconds
Started Jul 10 05:36:03 PM PDT 24
Finished Jul 10 05:36:07 PM PDT 24
Peak memory 196656 kb
Host smart-33d0c865-72a7-45a0-876e-c4a15cb7ca2f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000748980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3000748980
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1745485413
Short name T509
Test name
Test status
Simulation time 209410943 ps
CPU time 2.97 seconds
Started Jul 10 05:36:02 PM PDT 24
Finished Jul 10 05:36:06 PM PDT 24
Peak memory 198640 kb
Host smart-d1c11a11-d69c-46b0-a5b5-2e506b5f8f48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745485413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1745485413
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3554583713
Short name T159
Test name
Test status
Simulation time 39145805 ps
CPU time 1.24 seconds
Started Jul 10 05:36:02 PM PDT 24
Finished Jul 10 05:36:06 PM PDT 24
Peak memory 196392 kb
Host smart-be7eb807-ec78-4066-bddb-d80a8d4ba71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554583713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3554583713
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2400058507
Short name T148
Test name
Test status
Simulation time 135137845 ps
CPU time 1.38 seconds
Started Jul 10 05:36:02 PM PDT 24
Finished Jul 10 05:36:05 PM PDT 24
Peak memory 196208 kb
Host smart-af4c47f9-6884-42e8-ba3a-ac6708337b8f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400058507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2400058507
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2994018502
Short name T77
Test name
Test status
Simulation time 7866796306 ps
CPU time 212.59 seconds
Started Jul 10 05:36:03 PM PDT 24
Finished Jul 10 05:39:39 PM PDT 24
Peak memory 198780 kb
Host smart-d441d9e2-b75f-4e49-9b9e-9b2438d12c6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994018502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2994018502
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1926854032
Short name T253
Test name
Test status
Simulation time 14938240 ps
CPU time 0.58 seconds
Started Jul 10 05:36:12 PM PDT 24
Finished Jul 10 05:36:14 PM PDT 24
Peak memory 195536 kb
Host smart-824ca3e4-25f0-4fab-a1e5-c2c3ae5810a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926854032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1926854032
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2584152256
Short name T485
Test name
Test status
Simulation time 223697217 ps
CPU time 0.97 seconds
Started Jul 10 05:36:07 PM PDT 24
Finished Jul 10 05:36:09 PM PDT 24
Peak memory 197120 kb
Host smart-0970d162-4487-4828-a680-654553f3f099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584152256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2584152256
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.1588974053
Short name T696
Test name
Test status
Simulation time 1704858974 ps
CPU time 12.88 seconds
Started Jul 10 05:36:07 PM PDT 24
Finished Jul 10 05:36:21 PM PDT 24
Peak memory 197496 kb
Host smart-e9b56c4d-0309-400c-bc71-c9cf0a8b4ed5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588974053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.1588974053
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1557662047
Short name T559
Test name
Test status
Simulation time 212806557 ps
CPU time 0.83 seconds
Started Jul 10 05:36:09 PM PDT 24
Finished Jul 10 05:36:11 PM PDT 24
Peak memory 196696 kb
Host smart-59250986-074b-4eef-9cf9-da20f1b623f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557662047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1557662047
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2516433731
Short name T611
Test name
Test status
Simulation time 60226557 ps
CPU time 1.14 seconds
Started Jul 10 05:36:08 PM PDT 24
Finished Jul 10 05:36:11 PM PDT 24
Peak memory 197276 kb
Host smart-4fc8f662-34be-46a3-8f55-7f65e2b94429
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516433731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2516433731
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.2824914883
Short name T459
Test name
Test status
Simulation time 63605027 ps
CPU time 2.16 seconds
Started Jul 10 05:36:08 PM PDT 24
Finished Jul 10 05:36:11 PM PDT 24
Peak memory 197956 kb
Host smart-6ae0b2e8-547d-4573-8a24-899b3447003c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824914883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.2824914883
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.4284004469
Short name T291
Test name
Test status
Simulation time 175810538 ps
CPU time 1.14 seconds
Started Jul 10 05:36:08 PM PDT 24
Finished Jul 10 05:36:10 PM PDT 24
Peak memory 196540 kb
Host smart-06dc70ba-15f6-4b01-b805-71e8e5dac373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284004469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.4284004469
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2529786800
Short name T562
Test name
Test status
Simulation time 435103873 ps
CPU time 1.36 seconds
Started Jul 10 05:36:09 PM PDT 24
Finished Jul 10 05:36:11 PM PDT 24
Peak memory 196500 kb
Host smart-41a4e7ca-0f13-4841-9cd3-dd12e5f9e4cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529786800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2529786800
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1268607111
Short name T473
Test name
Test status
Simulation time 484022211 ps
CPU time 1.9 seconds
Started Jul 10 05:36:08 PM PDT 24
Finished Jul 10 05:36:10 PM PDT 24
Peak memory 198480 kb
Host smart-1c46f79b-f003-42fc-8b7d-e88b3156b202
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268607111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1268607111
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3911461530
Short name T520
Test name
Test status
Simulation time 113677637 ps
CPU time 1.09 seconds
Started Jul 10 05:36:00 PM PDT 24
Finished Jul 10 05:36:03 PM PDT 24
Peak memory 196428 kb
Host smart-ca167b8d-b894-46b1-938d-41e36a8eae67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911461530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3911461530
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3204342791
Short name T187
Test name
Test status
Simulation time 45134232 ps
CPU time 1.1 seconds
Started Jul 10 05:36:02 PM PDT 24
Finished Jul 10 05:36:06 PM PDT 24
Peak memory 197188 kb
Host smart-9b67d808-443d-4b30-a22b-7a80fd778ce5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204342791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3204342791
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.579323151
Short name T640
Test name
Test status
Simulation time 9288568088 ps
CPU time 51.09 seconds
Started Jul 10 05:36:10 PM PDT 24
Finished Jul 10 05:37:02 PM PDT 24
Peak memory 198700 kb
Host smart-4e7cd2a0-6e24-4f43-9c49-bcde14d5a91b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579323151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.g
pio_stress_all.579323151
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.967962965
Short name T375
Test name
Test status
Simulation time 42633847 ps
CPU time 0.58 seconds
Started Jul 10 05:36:19 PM PDT 24
Finished Jul 10 05:36:20 PM PDT 24
Peak memory 194828 kb
Host smart-ca13d416-f14d-4641-aa9c-0d4ab2aaca41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967962965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.967962965
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.250653876
Short name T647
Test name
Test status
Simulation time 19988438 ps
CPU time 0.67 seconds
Started Jul 10 05:36:12 PM PDT 24
Finished Jul 10 05:36:13 PM PDT 24
Peak memory 194708 kb
Host smart-55e1a691-82b4-458f-8db4-fb4a538c42c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250653876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.250653876
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.3701980464
Short name T457
Test name
Test status
Simulation time 376389610 ps
CPU time 18.96 seconds
Started Jul 10 05:36:20 PM PDT 24
Finished Jul 10 05:36:40 PM PDT 24
Peak memory 197440 kb
Host smart-3a80aef4-773b-4080-8bb9-651d4eec25d1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701980464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.3701980464
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1844053423
Short name T624
Test name
Test status
Simulation time 45597175 ps
CPU time 0.7 seconds
Started Jul 10 05:36:19 PM PDT 24
Finished Jul 10 05:36:20 PM PDT 24
Peak memory 195376 kb
Host smart-98c8ddb1-f232-44ad-af3d-ba5cda79ca82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844053423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1844053423
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1784693678
Short name T208
Test name
Test status
Simulation time 79407274 ps
CPU time 1.05 seconds
Started Jul 10 05:36:14 PM PDT 24
Finished Jul 10 05:36:16 PM PDT 24
Peak memory 196684 kb
Host smart-c2eca146-a8b2-499b-aa9a-ec000d6da0b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784693678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1784693678
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2503846889
Short name T310
Test name
Test status
Simulation time 148176894 ps
CPU time 1.74 seconds
Started Jul 10 05:36:18 PM PDT 24
Finished Jul 10 05:36:21 PM PDT 24
Peak memory 197412 kb
Host smart-7f53b9f0-58c1-411c-9649-df6a4c39868d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503846889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2503846889
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.4212999798
Short name T702
Test name
Test status
Simulation time 247959531 ps
CPU time 2.45 seconds
Started Jul 10 05:36:13 PM PDT 24
Finished Jul 10 05:36:16 PM PDT 24
Peak memory 196496 kb
Host smart-4171dc94-24d3-4005-9127-f45473e5ec7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212999798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.4212999798
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3893211219
Short name T445
Test name
Test status
Simulation time 171984230 ps
CPU time 1.21 seconds
Started Jul 10 05:36:14 PM PDT 24
Finished Jul 10 05:36:16 PM PDT 24
Peak memory 196692 kb
Host smart-0343f004-a708-4e70-860b-64b0558ffeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893211219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3893211219
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1557717367
Short name T125
Test name
Test status
Simulation time 59901070 ps
CPU time 1.24 seconds
Started Jul 10 05:36:15 PM PDT 24
Finished Jul 10 05:36:17 PM PDT 24
Peak memory 197684 kb
Host smart-139e95b0-eb71-4512-b505-44d7390f6248
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557717367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1557717367
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1083206376
Short name T210
Test name
Test status
Simulation time 83900805 ps
CPU time 1.48 seconds
Started Jul 10 05:36:18 PM PDT 24
Finished Jul 10 05:36:20 PM PDT 24
Peak memory 198604 kb
Host smart-6259d382-d997-474f-8765-52e17e76c213
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083206376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1083206376
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2455524415
Short name T238
Test name
Test status
Simulation time 306514380 ps
CPU time 1.31 seconds
Started Jul 10 05:36:14 PM PDT 24
Finished Jul 10 05:36:16 PM PDT 24
Peak memory 197280 kb
Host smart-43987c30-f1bd-4eed-9fb0-91077b441b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455524415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2455524415
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.4084197763
Short name T360
Test name
Test status
Simulation time 184106940 ps
CPU time 1.01 seconds
Started Jul 10 05:36:12 PM PDT 24
Finished Jul 10 05:36:14 PM PDT 24
Peak memory 196328 kb
Host smart-2f30774a-8df9-4014-becd-926cc1057567
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084197763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.4084197763
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.547930123
Short name T399
Test name
Test status
Simulation time 41749290007 ps
CPU time 157.88 seconds
Started Jul 10 05:36:22 PM PDT 24
Finished Jul 10 05:39:00 PM PDT 24
Peak memory 198824 kb
Host smart-b2854dbe-7889-4470-ac78-7e4e23721045
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547930123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.547930123
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.66271197
Short name T608
Test name
Test status
Simulation time 28620358 ps
CPU time 0.56 seconds
Started Jul 10 05:36:24 PM PDT 24
Finished Jul 10 05:36:26 PM PDT 24
Peak memory 194680 kb
Host smart-eeef77f8-35c8-48c8-9b9f-c92d62e37cc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66271197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.66271197
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.4031227250
Short name T16
Test name
Test status
Simulation time 19270306 ps
CPU time 0.72 seconds
Started Jul 10 05:38:58 PM PDT 24
Finished Jul 10 05:39:00 PM PDT 24
Peak memory 196560 kb
Host smart-c8cd2ce2-d57a-4442-a2ac-80b34be66243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031227250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.4031227250
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3122813448
Short name T56
Test name
Test status
Simulation time 672720799 ps
CPU time 17.54 seconds
Started Jul 10 05:36:26 PM PDT 24
Finished Jul 10 05:36:45 PM PDT 24
Peak memory 197828 kb
Host smart-2957cd5d-07c3-492f-8209-78b76230cffa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122813448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3122813448
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.420709625
Short name T368
Test name
Test status
Simulation time 81198884 ps
CPU time 1.14 seconds
Started Jul 10 05:36:26 PM PDT 24
Finished Jul 10 05:36:28 PM PDT 24
Peak memory 197212 kb
Host smart-0504f8a4-aeb1-4226-8bc3-de16e0faf3bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420709625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.420709625
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2306522125
Short name T72
Test name
Test status
Simulation time 56116014 ps
CPU time 1.14 seconds
Started Jul 10 05:36:29 PM PDT 24
Finished Jul 10 05:36:31 PM PDT 24
Peak memory 197556 kb
Host smart-5a97320c-0704-4a97-9098-e0c4ecf53ad2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306522125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2306522125
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1778131659
Short name T212
Test name
Test status
Simulation time 338057016 ps
CPU time 3.8 seconds
Started Jul 10 05:36:26 PM PDT 24
Finished Jul 10 05:36:30 PM PDT 24
Peak memory 198636 kb
Host smart-46699551-1fb8-4e2f-91d3-8612873340f5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778131659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1778131659
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.565980831
Short name T69
Test name
Test status
Simulation time 132382777 ps
CPU time 1.16 seconds
Started Jul 10 05:36:26 PM PDT 24
Finished Jul 10 05:36:28 PM PDT 24
Peak memory 196360 kb
Host smart-9d521fe1-10ee-40d9-ae10-0c7bbb5ccd75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565980831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
565980831
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.4159793670
Short name T630
Test name
Test status
Simulation time 64928145 ps
CPU time 1.25 seconds
Started Jul 10 05:36:20 PM PDT 24
Finished Jul 10 05:36:21 PM PDT 24
Peak memory 198680 kb
Host smart-5422a3ad-f4dd-4004-8a88-861729662dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159793670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.4159793670
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2016550274
Short name T602
Test name
Test status
Simulation time 328988523 ps
CPU time 1.21 seconds
Started Jul 10 05:36:26 PM PDT 24
Finished Jul 10 05:36:28 PM PDT 24
Peak memory 197560 kb
Host smart-8c4840c5-bd31-441a-8631-1c711003ddcd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016550274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2016550274
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2135149561
Short name T270
Test name
Test status
Simulation time 151308367 ps
CPU time 1.97 seconds
Started Jul 10 05:36:28 PM PDT 24
Finished Jul 10 05:36:30 PM PDT 24
Peak memory 198588 kb
Host smart-311a642f-c40c-4660-ac3e-3cabec2a6e8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135149561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2135149561
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1485502748
Short name T161
Test name
Test status
Simulation time 110559585 ps
CPU time 1.29 seconds
Started Jul 10 05:36:21 PM PDT 24
Finished Jul 10 05:36:23 PM PDT 24
Peak memory 197116 kb
Host smart-f146c0a6-cc4a-4451-a674-e51d0c4359da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485502748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1485502748
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2529224853
Short name T276
Test name
Test status
Simulation time 227245811 ps
CPU time 1.32 seconds
Started Jul 10 05:36:21 PM PDT 24
Finished Jul 10 05:36:23 PM PDT 24
Peak memory 196476 kb
Host smart-0c67255d-8562-449b-91b3-e85d3484d1c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529224853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2529224853
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1988299535
Short name T294
Test name
Test status
Simulation time 6009255334 ps
CPU time 41.6 seconds
Started Jul 10 05:36:25 PM PDT 24
Finished Jul 10 05:37:08 PM PDT 24
Peak memory 198764 kb
Host smart-b909ac44-38c3-40fe-bf35-93693ba258a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988299535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1988299535
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.4231212616
Short name T59
Test name
Test status
Simulation time 246080080529 ps
CPU time 2496.9 seconds
Started Jul 10 05:36:25 PM PDT 24
Finished Jul 10 06:18:03 PM PDT 24
Peak memory 198904 kb
Host smart-c1fd710c-8840-4870-9f1a-6c78100b6c3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4231212616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.4231212616
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2276334580
Short name T667
Test name
Test status
Simulation time 19622783 ps
CPU time 0.6 seconds
Started Jul 10 05:34:13 PM PDT 24
Finished Jul 10 05:34:15 PM PDT 24
Peak memory 194856 kb
Host smart-cfe0fc9a-b132-4f6d-8aea-d081321afb7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276334580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2276334580
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1519576583
Short name T186
Test name
Test status
Simulation time 73586236 ps
CPU time 0.81 seconds
Started Jul 10 05:33:58 PM PDT 24
Finished Jul 10 05:34:00 PM PDT 24
Peak memory 196692 kb
Host smart-d3654712-ab84-477c-aff6-fb12ebe7c0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519576583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1519576583
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2464966087
Short name T710
Test name
Test status
Simulation time 357412475 ps
CPU time 10.46 seconds
Started Jul 10 05:34:06 PM PDT 24
Finished Jul 10 05:34:17 PM PDT 24
Peak memory 197496 kb
Host smart-b43e8925-71cf-4d78-b6cf-fa0d8fdc176c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464966087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2464966087
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.223468545
Short name T343
Test name
Test status
Simulation time 41091277 ps
CPU time 0.6 seconds
Started Jul 10 05:34:08 PM PDT 24
Finished Jul 10 05:34:10 PM PDT 24
Peak memory 194984 kb
Host smart-eea24602-7d9d-4ce0-bc10-b0894290387a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223468545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.223468545
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1913591534
Short name T326
Test name
Test status
Simulation time 74303000 ps
CPU time 1 seconds
Started Jul 10 05:33:58 PM PDT 24
Finished Jul 10 05:34:00 PM PDT 24
Peak memory 196784 kb
Host smart-3aee38e5-795b-4d1a-a884-0d60b365c88f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913591534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1913591534
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1943817355
Short name T448
Test name
Test status
Simulation time 457235001 ps
CPU time 3.53 seconds
Started Jul 10 05:34:09 PM PDT 24
Finished Jul 10 05:34:13 PM PDT 24
Peak memory 198712 kb
Host smart-a100e595-0039-4b53-b655-af21cb358ddb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943817355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1943817355
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3165408449
Short name T434
Test name
Test status
Simulation time 85679428 ps
CPU time 0.86 seconds
Started Jul 10 05:34:05 PM PDT 24
Finished Jul 10 05:34:06 PM PDT 24
Peak memory 195060 kb
Host smart-31d87156-cb49-49dd-bbcd-f877b5add54f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165408449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3165408449
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.503013978
Short name T504
Test name
Test status
Simulation time 105580313 ps
CPU time 0.79 seconds
Started Jul 10 05:33:55 PM PDT 24
Finished Jul 10 05:33:57 PM PDT 24
Peak memory 196396 kb
Host smart-b3e756a2-ffcd-45c3-a56d-db5d41abef03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503013978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.503013978
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2794506433
Short name T409
Test name
Test status
Simulation time 61352678 ps
CPU time 1.41 seconds
Started Jul 10 05:33:58 PM PDT 24
Finished Jul 10 05:34:00 PM PDT 24
Peak memory 197576 kb
Host smart-a07ac576-bec6-478d-8e9b-e6239d0132ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794506433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2794506433
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.2556275518
Short name T671
Test name
Test status
Simulation time 126102989 ps
CPU time 5.52 seconds
Started Jul 10 05:34:04 PM PDT 24
Finished Jul 10 05:34:11 PM PDT 24
Peak memory 198552 kb
Host smart-51f9c8b7-a31e-4fd8-8bb4-5cb2024d0162
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556275518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.2556275518
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_smoke.2258717411
Short name T306
Test name
Test status
Simulation time 42765146 ps
CPU time 1.25 seconds
Started Jul 10 05:33:55 PM PDT 24
Finished Jul 10 05:33:57 PM PDT 24
Peak memory 196508 kb
Host smart-1e0802f3-5f4e-4e92-96cd-fef5fa0c6a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258717411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2258717411
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3835466201
Short name T178
Test name
Test status
Simulation time 35124261 ps
CPU time 0.74 seconds
Started Jul 10 05:33:57 PM PDT 24
Finished Jul 10 05:33:59 PM PDT 24
Peak memory 194812 kb
Host smart-4a44c65a-ca5d-4414-82e9-a97c3268e0d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835466201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3835466201
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.965417969
Short name T561
Test name
Test status
Simulation time 10716705387 ps
CPU time 118.85 seconds
Started Jul 10 05:34:04 PM PDT 24
Finished Jul 10 05:36:03 PM PDT 24
Peak memory 198708 kb
Host smart-18d1e73b-81d5-4694-8dab-ba77e1c60c21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965417969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.965417969
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1185921647
Short name T38
Test name
Test status
Simulation time 21061062 ps
CPU time 0.58 seconds
Started Jul 10 05:36:32 PM PDT 24
Finished Jul 10 05:36:33 PM PDT 24
Peak memory 194868 kb
Host smart-a0ed2736-fedd-4e44-9d48-290c6c5c79a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185921647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1185921647
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.240956105
Short name T583
Test name
Test status
Simulation time 94028873 ps
CPU time 0.71 seconds
Started Jul 10 05:36:31 PM PDT 24
Finished Jul 10 05:36:32 PM PDT 24
Peak memory 194788 kb
Host smart-ea65366a-eef1-48be-bd57-1017c4f4db35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240956105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.240956105
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.860503843
Short name T664
Test name
Test status
Simulation time 394078505 ps
CPU time 21.29 seconds
Started Jul 10 05:36:35 PM PDT 24
Finished Jul 10 05:36:57 PM PDT 24
Peak memory 196940 kb
Host smart-c5aee6a1-84e2-43a4-9c88-1f1fd7cf96d9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860503843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.860503843
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3313255415
Short name T662
Test name
Test status
Simulation time 232491601 ps
CPU time 0.96 seconds
Started Jul 10 05:36:31 PM PDT 24
Finished Jul 10 05:36:33 PM PDT 24
Peak memory 198440 kb
Host smart-b60212d6-2a04-49c9-b446-a0cca8163a0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313255415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3313255415
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.93095602
Short name T256
Test name
Test status
Simulation time 194422237 ps
CPU time 1.35 seconds
Started Jul 10 05:36:31 PM PDT 24
Finished Jul 10 05:36:33 PM PDT 24
Peak memory 197452 kb
Host smart-bbe9aa23-c63d-4b4f-b8e4-2cb83b165089
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93095602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.93095602
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1462382997
Short name T55
Test name
Test status
Simulation time 319462022 ps
CPU time 2.51 seconds
Started Jul 10 05:36:32 PM PDT 24
Finished Jul 10 05:36:36 PM PDT 24
Peak memory 198504 kb
Host smart-c2363abd-8062-48c5-ab45-729611ff1dad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462382997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1462382997
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1310922920
Short name T234
Test name
Test status
Simulation time 123177091 ps
CPU time 2.91 seconds
Started Jul 10 05:36:31 PM PDT 24
Finished Jul 10 05:36:34 PM PDT 24
Peak memory 198768 kb
Host smart-6af38010-0007-43ed-b424-477db5363d2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310922920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1310922920
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.84199280
Short name T315
Test name
Test status
Simulation time 21534632 ps
CPU time 0.7 seconds
Started Jul 10 05:36:32 PM PDT 24
Finished Jul 10 05:36:33 PM PDT 24
Peak memory 196032 kb
Host smart-eca9e5bd-b66e-424e-8c83-81a0e335615f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84199280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.84199280
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3152719486
Short name T634
Test name
Test status
Simulation time 116978205 ps
CPU time 1.43 seconds
Started Jul 10 05:36:35 PM PDT 24
Finished Jul 10 05:36:37 PM PDT 24
Peak memory 197772 kb
Host smart-78895be9-c899-453c-977f-fdd62c489c1a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152719486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3152719486
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2893492578
Short name T600
Test name
Test status
Simulation time 567890960 ps
CPU time 6.78 seconds
Started Jul 10 05:36:30 PM PDT 24
Finished Jul 10 05:36:37 PM PDT 24
Peak memory 198592 kb
Host smart-7ce75b5b-fa5e-4570-aa1c-91c6df321d85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893492578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2893492578
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3401100662
Short name T678
Test name
Test status
Simulation time 139218628 ps
CPU time 1.07 seconds
Started Jul 10 05:36:32 PM PDT 24
Finished Jul 10 05:36:34 PM PDT 24
Peak memory 196404 kb
Host smart-bae838b0-98bf-4770-acd3-6b5c0eafed31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401100662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3401100662
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3665466853
Short name T344
Test name
Test status
Simulation time 59538801 ps
CPU time 1.25 seconds
Started Jul 10 05:36:32 PM PDT 24
Finished Jul 10 05:36:35 PM PDT 24
Peak memory 198464 kb
Host smart-dec16282-c1b4-47e0-a6bb-13def7f6fe90
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665466853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3665466853
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1283308759
Short name T612
Test name
Test status
Simulation time 24817409628 ps
CPU time 166.16 seconds
Started Jul 10 05:36:32 PM PDT 24
Finished Jul 10 05:39:19 PM PDT 24
Peak memory 198816 kb
Host smart-2c020aa5-6623-4f8d-9e7c-3d3f28c6db56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283308759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1283308759
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1884151347
Short name T39
Test name
Test status
Simulation time 15295993 ps
CPU time 0.59 seconds
Started Jul 10 05:36:39 PM PDT 24
Finished Jul 10 05:36:40 PM PDT 24
Peak memory 194636 kb
Host smart-774784f8-6873-4892-8b87-04753e98a1c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884151347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1884151347
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.221669359
Short name T119
Test name
Test status
Simulation time 154985741 ps
CPU time 0.74 seconds
Started Jul 10 05:36:38 PM PDT 24
Finished Jul 10 05:36:39 PM PDT 24
Peak memory 195880 kb
Host smart-b17449ea-4fdd-4116-9242-e496979433f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221669359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.221669359
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3586204408
Short name T689
Test name
Test status
Simulation time 313298823 ps
CPU time 9.12 seconds
Started Jul 10 05:36:37 PM PDT 24
Finished Jul 10 05:36:47 PM PDT 24
Peak memory 197496 kb
Host smart-b31fc804-dc0f-4fac-9cee-54817d20454b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586204408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3586204408
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.414906351
Short name T676
Test name
Test status
Simulation time 73335933 ps
CPU time 0.69 seconds
Started Jul 10 05:36:38 PM PDT 24
Finished Jul 10 05:36:39 PM PDT 24
Peak memory 195212 kb
Host smart-1e705417-8534-4d8c-87de-eb3f5c0876ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414906351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.414906351
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.467544835
Short name T563
Test name
Test status
Simulation time 115256750 ps
CPU time 1.44 seconds
Started Jul 10 05:36:43 PM PDT 24
Finished Jul 10 05:36:45 PM PDT 24
Peak memory 198640 kb
Host smart-67969d11-8526-427e-8936-9b54d5a8cec6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467544835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.467544835
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3146713169
Short name T400
Test name
Test status
Simulation time 72801810 ps
CPU time 2.82 seconds
Started Jul 10 05:36:43 PM PDT 24
Finished Jul 10 05:36:47 PM PDT 24
Peak memory 198580 kb
Host smart-32b2ddf7-6b63-41f1-a54c-7556dd65a14a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146713169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3146713169
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3428759570
Short name T205
Test name
Test status
Simulation time 207900528 ps
CPU time 2.62 seconds
Started Jul 10 05:36:39 PM PDT 24
Finished Jul 10 05:36:43 PM PDT 24
Peak memory 197744 kb
Host smart-99db47b8-af41-4aa9-91d6-35e7acb99d71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428759570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3428759570
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3569894698
Short name T25
Test name
Test status
Simulation time 138030848 ps
CPU time 1.01 seconds
Started Jul 10 05:36:31 PM PDT 24
Finished Jul 10 05:36:33 PM PDT 24
Peak memory 196488 kb
Host smart-2ed30ba4-e211-4555-a793-05f21b0cc5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569894698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3569894698
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.253820408
Short name T405
Test name
Test status
Simulation time 48335493 ps
CPU time 1.22 seconds
Started Jul 10 05:36:39 PM PDT 24
Finished Jul 10 05:36:41 PM PDT 24
Peak memory 196492 kb
Host smart-e700ebea-35cb-4d26-8636-453f44527f93
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253820408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.253820408
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2290676235
Short name T495
Test name
Test status
Simulation time 406968736 ps
CPU time 7.21 seconds
Started Jul 10 05:36:40 PM PDT 24
Finished Jul 10 05:36:48 PM PDT 24
Peak memory 198620 kb
Host smart-d75523ec-0912-46da-bbbc-0cda9bdd688f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290676235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2290676235
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2530180440
Short name T134
Test name
Test status
Simulation time 170355349 ps
CPU time 1 seconds
Started Jul 10 05:36:32 PM PDT 24
Finished Jul 10 05:36:34 PM PDT 24
Peak memory 196136 kb
Host smart-952f582b-cd3b-4e25-83a3-5ce50946e85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530180440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2530180440
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1154557716
Short name T357
Test name
Test status
Simulation time 171331531 ps
CPU time 1.2 seconds
Started Jul 10 05:36:32 PM PDT 24
Finished Jul 10 05:36:35 PM PDT 24
Peak memory 196208 kb
Host smart-a29e52a5-f1fe-4a13-b194-47ad9a8d94c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154557716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1154557716
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2558105745
Short name T266
Test name
Test status
Simulation time 104517050063 ps
CPU time 226.12 seconds
Started Jul 10 05:36:38 PM PDT 24
Finished Jul 10 05:40:25 PM PDT 24
Peak memory 198776 kb
Host smart-b2d93c14-ba34-4464-911c-eadc164518a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558105745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2558105745
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.599263155
Short name T336
Test name
Test status
Simulation time 94385700805 ps
CPU time 2147.69 seconds
Started Jul 10 05:36:41 PM PDT 24
Finished Jul 10 06:12:30 PM PDT 24
Peak memory 198976 kb
Host smart-2059dfa8-07fd-4062-9673-6789a1f52053
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=599263155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.599263155
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.235071731
Short name T124
Test name
Test status
Simulation time 25731699 ps
CPU time 0.59 seconds
Started Jul 10 05:36:45 PM PDT 24
Finished Jul 10 05:36:47 PM PDT 24
Peak memory 195552 kb
Host smart-6ae86be6-e2e7-471a-9929-48be38551b42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235071731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.235071731
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3525020878
Short name T441
Test name
Test status
Simulation time 138371237 ps
CPU time 0.98 seconds
Started Jul 10 05:36:44 PM PDT 24
Finished Jul 10 05:36:47 PM PDT 24
Peak memory 197004 kb
Host smart-8e9a5b09-5003-49d5-a003-1118a42fad2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525020878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3525020878
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.4246440330
Short name T533
Test name
Test status
Simulation time 673429156 ps
CPU time 23.43 seconds
Started Jul 10 05:36:45 PM PDT 24
Finished Jul 10 05:37:10 PM PDT 24
Peak memory 198616 kb
Host smart-8e8b2ba7-561c-457e-a37c-699efdad1bc3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246440330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.4246440330
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1903529837
Short name T538
Test name
Test status
Simulation time 312788673 ps
CPU time 0.9 seconds
Started Jul 10 05:36:45 PM PDT 24
Finished Jul 10 05:36:47 PM PDT 24
Peak memory 197524 kb
Host smart-fb7deda5-037e-4ff7-8142-ad89ce8c7bc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903529837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1903529837
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3070739574
Short name T717
Test name
Test status
Simulation time 268923902 ps
CPU time 1.16 seconds
Started Jul 10 05:36:46 PM PDT 24
Finished Jul 10 05:36:49 PM PDT 24
Peak memory 197388 kb
Host smart-892615e3-f8e0-4d37-a2e8-74a3ddf38852
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070739574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3070739574
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1365046289
Short name T192
Test name
Test status
Simulation time 166055991 ps
CPU time 3.21 seconds
Started Jul 10 05:36:45 PM PDT 24
Finished Jul 10 05:36:50 PM PDT 24
Peak memory 196972 kb
Host smart-950ede45-c583-4931-9dbd-5cfadff1a0a8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365046289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1365046289
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1259742352
Short name T644
Test name
Test status
Simulation time 58368315 ps
CPU time 2.01 seconds
Started Jul 10 05:36:45 PM PDT 24
Finished Jul 10 05:36:48 PM PDT 24
Peak memory 196464 kb
Host smart-72a77748-a214-43d3-bbf6-5e03c35b4a28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259742352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1259742352
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3950654808
Short name T337
Test name
Test status
Simulation time 49878285 ps
CPU time 0.77 seconds
Started Jul 10 05:36:37 PM PDT 24
Finished Jul 10 05:36:39 PM PDT 24
Peak memory 196808 kb
Host smart-fbdab0a4-6a4b-4c83-96cf-01a3b36bc3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950654808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3950654808
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3120189077
Short name T658
Test name
Test status
Simulation time 101487970 ps
CPU time 1.26 seconds
Started Jul 10 05:36:37 PM PDT 24
Finished Jul 10 05:36:39 PM PDT 24
Peak memory 197768 kb
Host smart-7052d988-c371-4ed5-a7fd-5cc4f2caa4a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120189077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3120189077
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.60544883
Short name T629
Test name
Test status
Simulation time 10198198542 ps
CPU time 6.35 seconds
Started Jul 10 05:36:45 PM PDT 24
Finished Jul 10 05:36:53 PM PDT 24
Peak memory 198608 kb
Host smart-e2d258c0-3ac5-4afd-a838-f5ff23812053
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60544883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand
om_long_reg_writes_reg_reads.60544883
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3682058957
Short name T251
Test name
Test status
Simulation time 63534191 ps
CPU time 1.2 seconds
Started Jul 10 05:36:39 PM PDT 24
Finished Jul 10 05:36:41 PM PDT 24
Peak memory 196220 kb
Host smart-8266d728-8e54-4427-b290-e0d61efdb747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682058957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3682058957
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.4156627520
Short name T354
Test name
Test status
Simulation time 65488220 ps
CPU time 1.24 seconds
Started Jul 10 05:36:38 PM PDT 24
Finished Jul 10 05:36:41 PM PDT 24
Peak memory 196888 kb
Host smart-6eee262b-2e32-4961-b58e-80d99c77a7f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156627520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.4156627520
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.1392376417
Short name T193
Test name
Test status
Simulation time 14868496201 ps
CPU time 134.66 seconds
Started Jul 10 05:36:45 PM PDT 24
Finished Jul 10 05:39:00 PM PDT 24
Peak memory 198768 kb
Host smart-c1472abf-9a1b-4a45-abed-64b1b86ceb4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392376417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.1392376417
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1482680432
Short name T160
Test name
Test status
Simulation time 14911280 ps
CPU time 0.58 seconds
Started Jul 10 05:36:51 PM PDT 24
Finished Jul 10 05:36:53 PM PDT 24
Peak memory 194684 kb
Host smart-b83efb77-eb05-4778-9bb7-94c32da63efb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482680432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1482680432
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1265454893
Short name T314
Test name
Test status
Simulation time 35052651 ps
CPU time 0.66 seconds
Started Jul 10 05:36:45 PM PDT 24
Finished Jul 10 05:36:47 PM PDT 24
Peak memory 194688 kb
Host smart-2ef37179-595a-478d-9223-47ea8a6e3401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265454893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1265454893
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.3842826412
Short name T204
Test name
Test status
Simulation time 1887377361 ps
CPU time 13.3 seconds
Started Jul 10 05:36:51 PM PDT 24
Finished Jul 10 05:37:06 PM PDT 24
Peak memory 196944 kb
Host smart-21209bc1-c448-47b8-957e-3033fa9a36d6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842826412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.3842826412
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.937869751
Short name T546
Test name
Test status
Simulation time 121520677 ps
CPU time 0.73 seconds
Started Jul 10 05:36:54 PM PDT 24
Finished Jul 10 05:36:56 PM PDT 24
Peak memory 195324 kb
Host smart-1cd69235-4c31-41d9-ae03-67f43d0a5e6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937869751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.937869751
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.693339433
Short name T151
Test name
Test status
Simulation time 351867650 ps
CPU time 0.93 seconds
Started Jul 10 05:36:49 PM PDT 24
Finished Jul 10 05:36:51 PM PDT 24
Peak memory 196268 kb
Host smart-68b3972d-a37b-42fb-bb3d-edcf4bba2253
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693339433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.693339433
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2362592690
Short name T568
Test name
Test status
Simulation time 163745228 ps
CPU time 1.93 seconds
Started Jul 10 05:36:51 PM PDT 24
Finished Jul 10 05:36:54 PM PDT 24
Peak memory 198652 kb
Host smart-4892cbba-fe87-47df-be97-68afd2cc22e0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362592690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2362592690
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.1678623659
Short name T136
Test name
Test status
Simulation time 69642160 ps
CPU time 1.51 seconds
Started Jul 10 05:36:44 PM PDT 24
Finished Jul 10 05:36:47 PM PDT 24
Peak memory 196632 kb
Host smart-aa44010b-f9a3-49ac-92bb-c4813452b0d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678623659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.1678623659
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1330090832
Short name T369
Test name
Test status
Simulation time 46029390 ps
CPU time 0.95 seconds
Started Jul 10 05:36:44 PM PDT 24
Finished Jul 10 05:36:46 PM PDT 24
Peak memory 197040 kb
Host smart-97e08cf0-603c-4e83-9121-f63eee6a01d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330090832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1330090832
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.877132622
Short name T189
Test name
Test status
Simulation time 46632217 ps
CPU time 0.68 seconds
Started Jul 10 05:36:44 PM PDT 24
Finished Jul 10 05:36:46 PM PDT 24
Peak memory 194832 kb
Host smart-27041368-eed9-4b91-9efc-f435a01edb59
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877132622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.877132622
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3450219303
Short name T304
Test name
Test status
Simulation time 67106114 ps
CPU time 1.31 seconds
Started Jul 10 05:36:52 PM PDT 24
Finished Jul 10 05:36:54 PM PDT 24
Peak memory 198728 kb
Host smart-1095671d-32d9-4d87-8cb7-ae6b21373d7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450219303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3450219303
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1763415019
Short name T14
Test name
Test status
Simulation time 50229431 ps
CPU time 0.91 seconds
Started Jul 10 05:36:46 PM PDT 24
Finished Jul 10 05:36:48 PM PDT 24
Peak memory 196996 kb
Host smart-bfa7fa26-621d-47f9-88ce-2dd2c6db2770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763415019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1763415019
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1330952123
Short name T539
Test name
Test status
Simulation time 322374012 ps
CPU time 1.66 seconds
Started Jul 10 05:36:44 PM PDT 24
Finished Jul 10 05:36:47 PM PDT 24
Peak memory 196244 kb
Host smart-7f1f2400-910d-4964-814c-8c7194fa68fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330952123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1330952123
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2593466784
Short name T395
Test name
Test status
Simulation time 77087494344 ps
CPU time 208.18 seconds
Started Jul 10 05:36:52 PM PDT 24
Finished Jul 10 05:40:21 PM PDT 24
Peak memory 198800 kb
Host smart-99921f14-6b09-4fa3-a858-087a552ebb9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593466784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2593466784
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.2897035589
Short name T615
Test name
Test status
Simulation time 17576072823 ps
CPU time 605.04 seconds
Started Jul 10 05:36:53 PM PDT 24
Finished Jul 10 05:46:59 PM PDT 24
Peak memory 198916 kb
Host smart-487f3d6f-de19-4248-b04a-6e9e44a21f75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2897035589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.2897035589
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3598928193
Short name T587
Test name
Test status
Simulation time 24160407 ps
CPU time 0.57 seconds
Started Jul 10 05:36:59 PM PDT 24
Finished Jul 10 05:37:01 PM PDT 24
Peak memory 195544 kb
Host smart-e21c3602-57b9-4c2d-bf5d-b32350106ba4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598928193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3598928193
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2001636225
Short name T286
Test name
Test status
Simulation time 41431751 ps
CPU time 0.76 seconds
Started Jul 10 05:36:56 PM PDT 24
Finished Jul 10 05:36:57 PM PDT 24
Peak memory 195600 kb
Host smart-e6870323-0363-4831-9038-5b97ebc6bcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001636225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2001636225
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1856136156
Short name T518
Test name
Test status
Simulation time 3088721905 ps
CPU time 26.59 seconds
Started Jul 10 05:36:59 PM PDT 24
Finished Jul 10 05:37:27 PM PDT 24
Peak memory 196516 kb
Host smart-9716dd76-d046-4f4c-846d-884ec91f2097
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856136156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1856136156
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.2731502551
Short name T474
Test name
Test status
Simulation time 29192822 ps
CPU time 0.74 seconds
Started Jul 10 05:36:59 PM PDT 24
Finished Jul 10 05:37:00 PM PDT 24
Peak memory 195292 kb
Host smart-70c986dc-6414-43e5-bfd7-dad6ac054cba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731502551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2731502551
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3909896698
Short name T246
Test name
Test status
Simulation time 63617112 ps
CPU time 1.12 seconds
Started Jul 10 05:36:50 PM PDT 24
Finished Jul 10 05:36:52 PM PDT 24
Peak memory 196760 kb
Host smart-3e16820f-dc95-4bca-bf34-e8dc6529459d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909896698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3909896698
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3484052314
Short name T607
Test name
Test status
Simulation time 150769199 ps
CPU time 3.27 seconds
Started Jul 10 05:36:59 PM PDT 24
Finished Jul 10 05:37:03 PM PDT 24
Peak memory 198604 kb
Host smart-99a295bd-cc18-46fb-af53-3323af3f38c0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484052314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3484052314
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.2639494164
Short name T254
Test name
Test status
Simulation time 233702624 ps
CPU time 2.69 seconds
Started Jul 10 05:36:55 PM PDT 24
Finished Jul 10 05:36:59 PM PDT 24
Peak memory 197904 kb
Host smart-ac4c0f2e-b4f7-4a7f-814b-a592bbc4b37a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639494164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.2639494164
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1895065212
Short name T452
Test name
Test status
Simulation time 108617128 ps
CPU time 1.2 seconds
Started Jul 10 05:36:52 PM PDT 24
Finished Jul 10 05:36:54 PM PDT 24
Peak memory 197296 kb
Host smart-181df6dd-48ac-4412-9b93-3d6f4c9aedd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895065212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1895065212
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.589611387
Short name T500
Test name
Test status
Simulation time 113618096 ps
CPU time 0.75 seconds
Started Jul 10 05:36:53 PM PDT 24
Finished Jul 10 05:36:55 PM PDT 24
Peak memory 196672 kb
Host smart-308e8589-7b33-4ac4-8e0b-74e14752f8d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589611387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.589611387
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1019866452
Short name T342
Test name
Test status
Simulation time 331259561 ps
CPU time 4.39 seconds
Started Jul 10 05:36:58 PM PDT 24
Finished Jul 10 05:37:03 PM PDT 24
Peak memory 198692 kb
Host smart-e0eb14bc-5e90-4137-9e22-28c54f75647b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019866452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1019866452
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2546917675
Short name T709
Test name
Test status
Simulation time 25031533 ps
CPU time 0.91 seconds
Started Jul 10 05:36:51 PM PDT 24
Finished Jul 10 05:36:53 PM PDT 24
Peak memory 197780 kb
Host smart-77ff1be1-d66d-4a6b-b7f1-d94a8f62d06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546917675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2546917675
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2922579152
Short name T116
Test name
Test status
Simulation time 101848163 ps
CPU time 1.39 seconds
Started Jul 10 05:36:52 PM PDT 24
Finished Jul 10 05:36:54 PM PDT 24
Peak memory 197460 kb
Host smart-ca0d2ec8-0ba2-4c85-8be5-1ff7f40ed4ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922579152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2922579152
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3779841849
Short name T245
Test name
Test status
Simulation time 9894439546 ps
CPU time 122.88 seconds
Started Jul 10 05:36:59 PM PDT 24
Finished Jul 10 05:39:03 PM PDT 24
Peak memory 198764 kb
Host smart-ac28ca57-d40a-41d4-9354-c1d2e39de9de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779841849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3779841849
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2769930970
Short name T30
Test name
Test status
Simulation time 58834351636 ps
CPU time 1425.36 seconds
Started Jul 10 05:37:01 PM PDT 24
Finished Jul 10 06:00:47 PM PDT 24
Peak memory 198904 kb
Host smart-2a893ba9-2004-4c67-a523-a5c87c12846f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2769930970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.2769930970
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1948587031
Short name T638
Test name
Test status
Simulation time 12117438 ps
CPU time 0.6 seconds
Started Jul 10 05:37:08 PM PDT 24
Finished Jul 10 05:37:10 PM PDT 24
Peak memory 194664 kb
Host smart-d086929f-12f6-4d98-a900-0474037fbab3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948587031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1948587031
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.166244770
Short name T623
Test name
Test status
Simulation time 18537935 ps
CPU time 0.6 seconds
Started Jul 10 05:36:56 PM PDT 24
Finished Jul 10 05:36:58 PM PDT 24
Peak memory 195232 kb
Host smart-2944f42d-f1ef-4eb9-ae7d-601d6db2ef2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166244770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.166244770
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3884467125
Short name T316
Test name
Test status
Simulation time 659373298 ps
CPU time 4.42 seconds
Started Jul 10 05:37:07 PM PDT 24
Finished Jul 10 05:37:13 PM PDT 24
Peak memory 196236 kb
Host smart-a8feee28-17e0-4e39-9ed2-5347a70bb350
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884467125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3884467125
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2840660594
Short name T177
Test name
Test status
Simulation time 262999159 ps
CPU time 0.94 seconds
Started Jul 10 05:37:08 PM PDT 24
Finished Jul 10 05:37:10 PM PDT 24
Peak memory 198480 kb
Host smart-f1abf6b4-0463-4283-82a8-82659e45ea28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840660594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2840660594
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.189365958
Short name T367
Test name
Test status
Simulation time 40653424 ps
CPU time 0.93 seconds
Started Jul 10 05:37:08 PM PDT 24
Finished Jul 10 05:37:10 PM PDT 24
Peak memory 196348 kb
Host smart-ec1e549e-a639-4613-b9e4-2747f24e99d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189365958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.189365958
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.644374740
Short name T569
Test name
Test status
Simulation time 84598664 ps
CPU time 1.94 seconds
Started Jul 10 05:37:06 PM PDT 24
Finished Jul 10 05:37:08 PM PDT 24
Peak memory 198744 kb
Host smart-3a7b7a27-2a8b-4293-8e5b-7d95b76295eb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644374740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.644374740
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.2871776985
Short name T349
Test name
Test status
Simulation time 357326921 ps
CPU time 3.46 seconds
Started Jul 10 05:37:07 PM PDT 24
Finished Jul 10 05:37:12 PM PDT 24
Peak memory 196480 kb
Host smart-c3e5f6b3-c7e0-44bf-b6af-5d3b7853485d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871776985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.2871776985
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.802760502
Short name T422
Test name
Test status
Simulation time 347178881 ps
CPU time 1.12 seconds
Started Jul 10 05:36:58 PM PDT 24
Finished Jul 10 05:37:00 PM PDT 24
Peak memory 196500 kb
Host smart-ed4c60e9-bffb-43da-8ccf-21118fa5f964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802760502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.802760502
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.186347258
Short name T359
Test name
Test status
Simulation time 65523704 ps
CPU time 0.67 seconds
Started Jul 10 05:36:58 PM PDT 24
Finished Jul 10 05:36:59 PM PDT 24
Peak memory 194940 kb
Host smart-efdab433-a7ba-416e-8fe5-274a2dd9dcfc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186347258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.186347258
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3732869828
Short name T4
Test name
Test status
Simulation time 872113612 ps
CPU time 5.25 seconds
Started Jul 10 05:37:07 PM PDT 24
Finished Jul 10 05:37:13 PM PDT 24
Peak memory 198604 kb
Host smart-b99faf1a-5d6e-481d-8ca0-4e6963b2d1d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732869828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3732869828
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.4257053699
Short name T172
Test name
Test status
Simulation time 119097533 ps
CPU time 1.13 seconds
Started Jul 10 05:36:58 PM PDT 24
Finished Jul 10 05:37:00 PM PDT 24
Peak memory 197268 kb
Host smart-2c8bf97b-565a-4739-840a-2f92fe4e9eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257053699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.4257053699
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1776199199
Short name T261
Test name
Test status
Simulation time 37564655 ps
CPU time 0.95 seconds
Started Jul 10 05:36:59 PM PDT 24
Finished Jul 10 05:37:01 PM PDT 24
Peak memory 197132 kb
Host smart-e9556801-d9f4-40c4-8bee-bebb473463e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776199199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1776199199
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.808284656
Short name T419
Test name
Test status
Simulation time 29011720931 ps
CPU time 142.07 seconds
Started Jul 10 05:37:08 PM PDT 24
Finished Jul 10 05:39:31 PM PDT 24
Peak memory 198980 kb
Host smart-b4e4407e-093e-4ecb-9869-23abe1364cd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808284656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.808284656
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.2512104705
Short name T62
Test name
Test status
Simulation time 364859245627 ps
CPU time 1854.02 seconds
Started Jul 10 05:37:10 PM PDT 24
Finished Jul 10 06:08:05 PM PDT 24
Peak memory 198888 kb
Host smart-8dce791d-6afd-4091-b589-2b802b1df1df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2512104705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.2512104705
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3779451471
Short name T128
Test name
Test status
Simulation time 64910636 ps
CPU time 0.6 seconds
Started Jul 10 05:37:12 PM PDT 24
Finished Jul 10 05:37:13 PM PDT 24
Peak memory 194644 kb
Host smart-05f0ecb1-816e-43dc-b61c-b9d71732816d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779451471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3779451471
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3234423712
Short name T147
Test name
Test status
Simulation time 102778013 ps
CPU time 0.91 seconds
Started Jul 10 05:37:15 PM PDT 24
Finished Jul 10 05:37:16 PM PDT 24
Peak memory 196888 kb
Host smart-5538fa39-50ea-49b4-9686-c785f2a761c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234423712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3234423712
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1760209180
Short name T372
Test name
Test status
Simulation time 420221448 ps
CPU time 22.09 seconds
Started Jul 10 05:37:13 PM PDT 24
Finished Jul 10 05:37:36 PM PDT 24
Peak memory 198652 kb
Host smart-d69142ad-0121-412a-9417-4246de8d463d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760209180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1760209180
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.541905307
Short name T552
Test name
Test status
Simulation time 47813755 ps
CPU time 0.7 seconds
Started Jul 10 05:37:14 PM PDT 24
Finished Jul 10 05:37:15 PM PDT 24
Peak memory 195268 kb
Host smart-d723996b-d1ef-4047-bc00-b702880c9909
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541905307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.541905307
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3231999601
Short name T431
Test name
Test status
Simulation time 29751299 ps
CPU time 0.73 seconds
Started Jul 10 05:37:15 PM PDT 24
Finished Jul 10 05:37:16 PM PDT 24
Peak memory 195020 kb
Host smart-c3729e2a-5bdf-46c6-a78b-55b12365aba1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231999601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3231999601
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.81810577
Short name T109
Test name
Test status
Simulation time 132256271 ps
CPU time 1.07 seconds
Started Jul 10 05:37:15 PM PDT 24
Finished Jul 10 05:37:17 PM PDT 24
Peak memory 197012 kb
Host smart-55633bbe-bd11-4fa8-8e72-5db29716c246
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81810577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.gpio_intr_with_filter_rand_intr_event.81810577
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2479496947
Short name T516
Test name
Test status
Simulation time 157890407 ps
CPU time 3.37 seconds
Started Jul 10 05:37:12 PM PDT 24
Finished Jul 10 05:37:16 PM PDT 24
Peak memory 197924 kb
Host smart-53dc88b8-5d54-4e6f-b7ff-d544d634d36e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479496947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2479496947
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.4003187208
Short name T142
Test name
Test status
Simulation time 77596509 ps
CPU time 0.99 seconds
Started Jul 10 05:37:09 PM PDT 24
Finished Jul 10 05:37:11 PM PDT 24
Peak memory 196676 kb
Host smart-237976e5-e92b-47ba-84e2-b9e6d8bf8b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003187208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.4003187208
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3916455227
Short name T112
Test name
Test status
Simulation time 131019591 ps
CPU time 1.12 seconds
Started Jul 10 05:37:14 PM PDT 24
Finished Jul 10 05:37:16 PM PDT 24
Peak memory 197448 kb
Host smart-5aca7107-eb2d-4f8e-aca0-fb9f09aab089
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916455227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3916455227
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1874759373
Short name T163
Test name
Test status
Simulation time 100367838 ps
CPU time 4.4 seconds
Started Jul 10 05:37:16 PM PDT 24
Finished Jul 10 05:37:22 PM PDT 24
Peak memory 198284 kb
Host smart-5fc4dfa3-211b-4bb2-8292-4c2fee0c6337
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874759373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1874759373
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1234286447
Short name T565
Test name
Test status
Simulation time 230748363 ps
CPU time 1.01 seconds
Started Jul 10 05:37:07 PM PDT 24
Finished Jul 10 05:37:09 PM PDT 24
Peak memory 196176 kb
Host smart-49c7e3f9-f198-47b0-9ae1-d7330773d77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234286447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1234286447
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.365978518
Short name T530
Test name
Test status
Simulation time 37715607 ps
CPU time 0.93 seconds
Started Jul 10 05:37:09 PM PDT 24
Finished Jul 10 05:37:10 PM PDT 24
Peak memory 196616 kb
Host smart-ce4bd664-bcc2-42ba-be5f-24626d5bdd8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365978518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.365978518
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1232177779
Short name T333
Test name
Test status
Simulation time 8003750128 ps
CPU time 219.53 seconds
Started Jul 10 05:37:14 PM PDT 24
Finished Jul 10 05:40:54 PM PDT 24
Peak memory 198712 kb
Host smart-ca34257f-45f1-4f72-b6f0-b3732c46c331
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232177779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1232177779
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.478727470
Short name T598
Test name
Test status
Simulation time 240790798294 ps
CPU time 1508.02 seconds
Started Jul 10 05:37:15 PM PDT 24
Finished Jul 10 06:02:24 PM PDT 24
Peak memory 206976 kb
Host smart-cd274f39-217f-43e9-bb11-a7d26c7f1015
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=478727470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.478727470
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3811575564
Short name T649
Test name
Test status
Simulation time 32856836 ps
CPU time 0.6 seconds
Started Jul 10 05:37:19 PM PDT 24
Finished Jul 10 05:37:20 PM PDT 24
Peak memory 195544 kb
Host smart-d15d17fd-9032-42ff-994a-754b9497b57e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811575564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3811575564
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.4282787964
Short name T244
Test name
Test status
Simulation time 83412704 ps
CPU time 0.7 seconds
Started Jul 10 05:37:16 PM PDT 24
Finished Jul 10 05:37:17 PM PDT 24
Peak memory 194652 kb
Host smart-f812705a-fa26-4a9c-a57d-26f19561c84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282787964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.4282787964
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3052482649
Short name T532
Test name
Test status
Simulation time 483141843 ps
CPU time 16.63 seconds
Started Jul 10 05:37:17 PM PDT 24
Finished Jul 10 05:37:35 PM PDT 24
Peak memory 197408 kb
Host smart-b7c53bcb-92a4-4f6b-8ca3-ce7f710b26b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052482649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3052482649
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.2734556844
Short name T252
Test name
Test status
Simulation time 244972545 ps
CPU time 0.87 seconds
Started Jul 10 05:37:22 PM PDT 24
Finished Jul 10 05:37:24 PM PDT 24
Peak memory 197368 kb
Host smart-efe2190f-6541-4223-9bbb-c326b5421552
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734556844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2734556844
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.4200000628
Short name T275
Test name
Test status
Simulation time 61233570 ps
CPU time 1.13 seconds
Started Jul 10 05:37:16 PM PDT 24
Finished Jul 10 05:37:18 PM PDT 24
Peak memory 196532 kb
Host smart-76ba38d2-324b-494b-a39a-86f6739bd3c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200000628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.4200000628
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2256808148
Short name T185
Test name
Test status
Simulation time 85941445 ps
CPU time 3.29 seconds
Started Jul 10 05:37:14 PM PDT 24
Finished Jul 10 05:37:18 PM PDT 24
Peak memory 196944 kb
Host smart-7a1b82e5-6051-4da3-b47b-2510b000279e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256808148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2256808148
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.4266983186
Short name T373
Test name
Test status
Simulation time 311515293 ps
CPU time 1.87 seconds
Started Jul 10 05:37:14 PM PDT 24
Finished Jul 10 05:37:16 PM PDT 24
Peak memory 196780 kb
Host smart-795f39ea-ee9d-460e-956b-11aa79073188
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266983186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.4266983186
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1041498362
Short name T118
Test name
Test status
Simulation time 33380326 ps
CPU time 0.81 seconds
Started Jul 10 05:37:12 PM PDT 24
Finished Jul 10 05:37:14 PM PDT 24
Peak memory 196020 kb
Host smart-138aa2e2-3005-4298-8955-404e7b5de130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041498362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1041498362
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1557398809
Short name T544
Test name
Test status
Simulation time 37378624 ps
CPU time 0.99 seconds
Started Jul 10 05:37:15 PM PDT 24
Finished Jul 10 05:37:16 PM PDT 24
Peak memory 196480 kb
Host smart-c9d9a9ac-202a-4c3c-8c48-e2ede34ca2d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557398809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1557398809
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2126766892
Short name T8
Test name
Test status
Simulation time 788994265 ps
CPU time 2.49 seconds
Started Jul 10 05:37:20 PM PDT 24
Finished Jul 10 05:37:23 PM PDT 24
Peak memory 198640 kb
Host smart-f5350b21-3be4-43c3-a8cf-6d5d3394d500
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126766892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2126766892
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.960573440
Short name T284
Test name
Test status
Simulation time 29101478 ps
CPU time 0.97 seconds
Started Jul 10 05:37:14 PM PDT 24
Finished Jul 10 05:37:16 PM PDT 24
Peak memory 196228 kb
Host smart-b5720f82-8264-4e06-ab40-58b5357b5c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960573440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.960573440
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3389217302
Short name T439
Test name
Test status
Simulation time 41040183 ps
CPU time 1.12 seconds
Started Jul 10 05:37:15 PM PDT 24
Finished Jul 10 05:37:17 PM PDT 24
Peak memory 196440 kb
Host smart-796e2c2a-5113-4f73-bc61-179260042355
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389217302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3389217302
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.940029916
Short name T361
Test name
Test status
Simulation time 26734312779 ps
CPU time 214.6 seconds
Started Jul 10 05:37:20 PM PDT 24
Finished Jul 10 05:40:55 PM PDT 24
Peak memory 198772 kb
Host smart-b6c98cff-0249-4000-ab8b-4299700eb1e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940029916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.g
pio_stress_all.940029916
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3325705902
Short name T510
Test name
Test status
Simulation time 33680435 ps
CPU time 0.55 seconds
Started Jul 10 05:37:25 PM PDT 24
Finished Jul 10 05:37:27 PM PDT 24
Peak memory 194576 kb
Host smart-6318d6b5-35be-46ba-b012-e17641233a85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325705902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3325705902
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1460768418
Short name T384
Test name
Test status
Simulation time 56911292 ps
CPU time 0.81 seconds
Started Jul 10 05:37:18 PM PDT 24
Finished Jul 10 05:37:20 PM PDT 24
Peak memory 196476 kb
Host smart-b02d11ee-fe2f-437a-afc7-94d1f60862ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460768418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1460768418
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.4149165199
Short name T413
Test name
Test status
Simulation time 2131050185 ps
CPU time 23.85 seconds
Started Jul 10 05:37:20 PM PDT 24
Finished Jul 10 05:37:45 PM PDT 24
Peak memory 198688 kb
Host smart-a2101b33-ad05-4a1a-8cdf-a84d9facfa37
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149165199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.4149165199
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2198525639
Short name T515
Test name
Test status
Simulation time 33539074 ps
CPU time 0.71 seconds
Started Jul 10 05:37:23 PM PDT 24
Finished Jul 10 05:37:24 PM PDT 24
Peak memory 196092 kb
Host smart-b74a2ea0-5e93-4517-beb3-32d06829e7f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198525639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2198525639
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.571362980
Short name T155
Test name
Test status
Simulation time 164798723 ps
CPU time 1.08 seconds
Started Jul 10 05:37:24 PM PDT 24
Finished Jul 10 05:37:26 PM PDT 24
Peak memory 196808 kb
Host smart-221a5fe5-48ce-4ab8-ac5f-fc0b9f94a778
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571362980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.571362980
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3247603269
Short name T697
Test name
Test status
Simulation time 163557346 ps
CPU time 3.35 seconds
Started Jul 10 05:37:22 PM PDT 24
Finished Jul 10 05:37:26 PM PDT 24
Peak memory 198644 kb
Host smart-080557c0-55c5-4f7a-b077-c8a4ce84b6e4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247603269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3247603269
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.946913946
Short name T536
Test name
Test status
Simulation time 161823038 ps
CPU time 1.21 seconds
Started Jul 10 05:37:21 PM PDT 24
Finished Jul 10 05:37:22 PM PDT 24
Peak memory 196324 kb
Host smart-a5464c8e-0c69-4cfe-8893-68aa420f3eab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946913946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
946913946
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3566193695
Short name T138
Test name
Test status
Simulation time 310861771 ps
CPU time 1.39 seconds
Started Jul 10 05:37:19 PM PDT 24
Finished Jul 10 05:37:21 PM PDT 24
Peak memory 197644 kb
Host smart-6465b7c9-756e-4637-9ed4-970012fbce90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566193695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3566193695
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1477304168
Short name T243
Test name
Test status
Simulation time 57169315 ps
CPU time 0.88 seconds
Started Jul 10 05:37:22 PM PDT 24
Finished Jul 10 05:37:23 PM PDT 24
Peak memory 197104 kb
Host smart-d74611a4-f23d-450a-b8ec-66d8a3c4af00
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477304168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1477304168
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.282258209
Short name T194
Test name
Test status
Simulation time 948066651 ps
CPU time 2.71 seconds
Started Jul 10 05:37:27 PM PDT 24
Finished Jul 10 05:37:31 PM PDT 24
Peak memory 198040 kb
Host smart-daf426b6-02cd-48af-9407-9087bb028402
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282258209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.282258209
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3422566141
Short name T213
Test name
Test status
Simulation time 112747497 ps
CPU time 1.09 seconds
Started Jul 10 05:37:22 PM PDT 24
Finished Jul 10 05:37:24 PM PDT 24
Peak memory 196584 kb
Host smart-dfa6b47b-bc99-4a46-8a65-ccf3cc7bdd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422566141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3422566141
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2230674283
Short name T645
Test name
Test status
Simulation time 65143609 ps
CPU time 1.16 seconds
Started Jul 10 05:37:27 PM PDT 24
Finished Jul 10 05:37:29 PM PDT 24
Peak memory 196912 kb
Host smart-a197b207-f218-40ea-8f2a-c1a2da81a42a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230674283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2230674283
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1803361652
Short name T519
Test name
Test status
Simulation time 15791736828 ps
CPU time 229.96 seconds
Started Jul 10 05:37:27 PM PDT 24
Finished Jul 10 05:41:18 PM PDT 24
Peak memory 198348 kb
Host smart-140198f5-05db-4c93-8240-f5d414d7754b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803361652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1803361652
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3533400420
Short name T70
Test name
Test status
Simulation time 14784426752 ps
CPU time 495.34 seconds
Started Jul 10 05:37:19 PM PDT 24
Finished Jul 10 05:45:36 PM PDT 24
Peak memory 198888 kb
Host smart-e10506b4-717f-47ee-91f3-63d7910b776e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3533400420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3533400420
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.4198875435
Short name T247
Test name
Test status
Simulation time 15324850 ps
CPU time 0.6 seconds
Started Jul 10 05:37:26 PM PDT 24
Finished Jul 10 05:37:27 PM PDT 24
Peak memory 195484 kb
Host smart-5bb1014a-70ec-419d-8d61-231e9c5edf48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198875435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.4198875435
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1202611094
Short name T126
Test name
Test status
Simulation time 102789822 ps
CPU time 0.84 seconds
Started Jul 10 05:37:29 PM PDT 24
Finished Jul 10 05:37:30 PM PDT 24
Peak memory 197092 kb
Host smart-14796973-373e-424f-b7ac-70d9e278d68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202611094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1202611094
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3016358076
Short name T432
Test name
Test status
Simulation time 320890710 ps
CPU time 9.83 seconds
Started Jul 10 05:37:25 PM PDT 24
Finished Jul 10 05:37:35 PM PDT 24
Peak memory 197548 kb
Host smart-3044e1dc-95ac-4a36-8dc8-8204c0391f3d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016358076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3016358076
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3595789403
Short name T66
Test name
Test status
Simulation time 130566564 ps
CPU time 0.6 seconds
Started Jul 10 05:37:26 PM PDT 24
Finished Jul 10 05:37:27 PM PDT 24
Peak memory 195252 kb
Host smart-fded2c18-8cf3-4581-ba09-7038c4967eb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595789403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3595789403
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.905159353
Short name T352
Test name
Test status
Simulation time 176277193 ps
CPU time 1.27 seconds
Started Jul 10 05:37:26 PM PDT 24
Finished Jul 10 05:37:28 PM PDT 24
Peak memory 197824 kb
Host smart-a88f3d16-8b0d-4a7b-bf06-2d8fa62fb82e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905159353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.905159353
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3554944593
Short name T673
Test name
Test status
Simulation time 110530973 ps
CPU time 1.2 seconds
Started Jul 10 05:37:27 PM PDT 24
Finished Jul 10 05:37:29 PM PDT 24
Peak memory 198472 kb
Host smart-56f33589-85db-4430-8ad7-c4ace929a5ec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554944593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3554944593
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2686201315
Short name T491
Test name
Test status
Simulation time 162608380 ps
CPU time 1.3 seconds
Started Jul 10 05:37:25 PM PDT 24
Finished Jul 10 05:37:28 PM PDT 24
Peak memory 197496 kb
Host smart-b5693426-e19d-4792-bed2-79c8c675978b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686201315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2686201315
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.4158077262
Short name T240
Test name
Test status
Simulation time 46854399 ps
CPU time 1.24 seconds
Started Jul 10 05:37:26 PM PDT 24
Finished Jul 10 05:37:28 PM PDT 24
Peak memory 196524 kb
Host smart-fac533c2-4319-4fb5-bbc5-2ab92705ab85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158077262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.4158077262
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3288236432
Short name T506
Test name
Test status
Simulation time 46438340 ps
CPU time 0.8 seconds
Started Jul 10 05:37:26 PM PDT 24
Finished Jul 10 05:37:27 PM PDT 24
Peak memory 196044 kb
Host smart-5297d09b-7412-4389-a534-e07701e0f601
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288236432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3288236432
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1664584002
Short name T427
Test name
Test status
Simulation time 215193516 ps
CPU time 3.09 seconds
Started Jul 10 05:37:27 PM PDT 24
Finished Jul 10 05:37:32 PM PDT 24
Peak memory 198612 kb
Host smart-6df680a4-c5db-446a-8495-546c1e901a6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664584002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1664584002
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3278223839
Short name T497
Test name
Test status
Simulation time 155478077 ps
CPU time 1.08 seconds
Started Jul 10 05:37:27 PM PDT 24
Finished Jul 10 05:37:29 PM PDT 24
Peak memory 197192 kb
Host smart-ec746689-a193-4f6e-b890-e49925525e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278223839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3278223839
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.745829014
Short name T524
Test name
Test status
Simulation time 53870017 ps
CPU time 0.67 seconds
Started Jul 10 05:37:25 PM PDT 24
Finished Jul 10 05:37:27 PM PDT 24
Peak memory 194732 kb
Host smart-d859aedc-e52b-4d54-ad60-9bf23c50c7d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745829014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.745829014
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2505320799
Short name T484
Test name
Test status
Simulation time 11250135535 ps
CPU time 151.13 seconds
Started Jul 10 05:37:29 PM PDT 24
Finished Jul 10 05:40:01 PM PDT 24
Peak memory 198688 kb
Host smart-3a3c66cd-5b74-4141-a446-135ab76a8374
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505320799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2505320799
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2738431782
Short name T179
Test name
Test status
Simulation time 23073457 ps
CPU time 0.58 seconds
Started Jul 10 05:34:23 PM PDT 24
Finished Jul 10 05:34:24 PM PDT 24
Peak memory 194540 kb
Host smart-4618a690-56ec-46fb-8a0c-b7f8ba9ff6ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738431782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2738431782
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3877607429
Short name T298
Test name
Test status
Simulation time 24341441 ps
CPU time 0.93 seconds
Started Jul 10 05:34:11 PM PDT 24
Finished Jul 10 05:34:13 PM PDT 24
Peak memory 197128 kb
Host smart-59863537-a7b1-48d8-b4e9-4e026c37bf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877607429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3877607429
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.4952484
Short name T154
Test name
Test status
Simulation time 558985850 ps
CPU time 23.31 seconds
Started Jul 10 05:34:15 PM PDT 24
Finished Jul 10 05:34:39 PM PDT 24
Peak memory 197468 kb
Host smart-76b2af11-549b-478e-bf8a-6592ce0f5831
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4952484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_s
tress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress.4952484
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1468308129
Short name T393
Test name
Test status
Simulation time 107135854 ps
CPU time 0.96 seconds
Started Jul 10 05:34:20 PM PDT 24
Finished Jul 10 05:34:22 PM PDT 24
Peak memory 197704 kb
Host smart-cff0f323-2ab0-4b43-ae83-4872ac81987c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468308129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1468308129
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3350257810
Short name T388
Test name
Test status
Simulation time 49616494 ps
CPU time 0.88 seconds
Started Jul 10 05:34:12 PM PDT 24
Finished Jul 10 05:34:13 PM PDT 24
Peak memory 197440 kb
Host smart-2a4d1d3b-ea3b-4fa7-8b21-1ddeb28df26d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350257810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3350257810
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1759296307
Short name T229
Test name
Test status
Simulation time 341506833 ps
CPU time 1.28 seconds
Started Jul 10 05:34:13 PM PDT 24
Finished Jul 10 05:34:15 PM PDT 24
Peak memory 196892 kb
Host smart-c89fa621-5467-4ad5-a9c1-179b12501ebc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759296307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1759296307
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2927035578
Short name T153
Test name
Test status
Simulation time 53932558 ps
CPU time 1.71 seconds
Started Jul 10 05:34:13 PM PDT 24
Finished Jul 10 05:34:16 PM PDT 24
Peak memory 196724 kb
Host smart-552c19ad-c991-447f-8a19-8c3a72a8000e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927035578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2927035578
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3936883293
Short name T237
Test name
Test status
Simulation time 21953994 ps
CPU time 0.71 seconds
Started Jul 10 05:34:11 PM PDT 24
Finished Jul 10 05:34:13 PM PDT 24
Peak memory 196772 kb
Host smart-6e030098-c299-4d1d-8e5d-beff94bddec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936883293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3936883293
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1327316987
Short name T493
Test name
Test status
Simulation time 219987715 ps
CPU time 1.1 seconds
Started Jul 10 05:34:18 PM PDT 24
Finished Jul 10 05:34:19 PM PDT 24
Peak memory 196500 kb
Host smart-cff77381-1921-4221-b217-05b51a3843fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327316987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1327316987
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3720992818
Short name T651
Test name
Test status
Simulation time 376621867 ps
CPU time 4.2 seconds
Started Jul 10 05:34:13 PM PDT 24
Finished Jul 10 05:34:18 PM PDT 24
Peak memory 198600 kb
Host smart-840b502f-355a-4f27-87e9-2e046d678a7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720992818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3720992818
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2403787023
Short name T36
Test name
Test status
Simulation time 152337159 ps
CPU time 0.94 seconds
Started Jul 10 05:34:22 PM PDT 24
Finished Jul 10 05:34:25 PM PDT 24
Peak memory 215340 kb
Host smart-d24ffa48-6a0c-4b72-a5b0-451bbdf1c30c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403787023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2403787023
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.4223492893
Short name T661
Test name
Test status
Simulation time 62131932 ps
CPU time 1.23 seconds
Started Jul 10 05:34:13 PM PDT 24
Finished Jul 10 05:34:15 PM PDT 24
Peak memory 196456 kb
Host smart-8b4837f8-3b7f-4d48-be3d-002f6ccaea57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223492893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.4223492893
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1591080966
Short name T428
Test name
Test status
Simulation time 302775642 ps
CPU time 1.4 seconds
Started Jul 10 05:34:11 PM PDT 24
Finished Jul 10 05:34:14 PM PDT 24
Peak memory 196212 kb
Host smart-aaac0e4b-a30a-4366-9144-fd45d3cba991
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591080966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1591080966
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.4174224637
Short name T227
Test name
Test status
Simulation time 2278385433 ps
CPU time 68.98 seconds
Started Jul 10 05:34:22 PM PDT 24
Finished Jul 10 05:35:32 PM PDT 24
Peak memory 198764 kb
Host smart-a788de7c-8785-4371-866c-763492bb2bb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174224637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.4174224637
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.2177141193
Short name T377
Test name
Test status
Simulation time 235044891937 ps
CPU time 2414.07 seconds
Started Jul 10 05:34:23 PM PDT 24
Finished Jul 10 06:14:38 PM PDT 24
Peak memory 198976 kb
Host smart-13592579-cf8b-4a65-9fbb-f29c715026f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2177141193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.2177141193
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2578924806
Short name T129
Test name
Test status
Simulation time 14237612 ps
CPU time 0.54 seconds
Started Jul 10 05:37:31 PM PDT 24
Finished Jul 10 05:37:32 PM PDT 24
Peak memory 194636 kb
Host smart-cf507d26-9fee-4ab5-8a0f-69aedd9ea16e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578924806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2578924806
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3697841881
Short name T511
Test name
Test status
Simulation time 29527041 ps
CPU time 0.97 seconds
Started Jul 10 05:37:27 PM PDT 24
Finished Jul 10 05:37:29 PM PDT 24
Peak memory 197852 kb
Host smart-326de242-f4dc-46e8-a907-628deb044dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697841881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3697841881
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2678593348
Short name T403
Test name
Test status
Simulation time 1260139733 ps
CPU time 17.19 seconds
Started Jul 10 05:37:32 PM PDT 24
Finished Jul 10 05:37:50 PM PDT 24
Peak memory 198628 kb
Host smart-ada556c2-155d-4ff7-a1c9-2c04d476dd02
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678593348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2678593348
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2764620554
Short name T166
Test name
Test status
Simulation time 80692608 ps
CPU time 0.81 seconds
Started Jul 10 05:37:32 PM PDT 24
Finished Jul 10 05:37:34 PM PDT 24
Peak memory 196500 kb
Host smart-97b92dc3-5508-402f-b327-bd302a92f0b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764620554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2764620554
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.829355019
Short name T554
Test name
Test status
Simulation time 129397791 ps
CPU time 1.07 seconds
Started Jul 10 05:37:32 PM PDT 24
Finished Jul 10 05:37:34 PM PDT 24
Peak memory 196388 kb
Host smart-8358801f-c3b2-4d8e-b7f2-68bd3754906f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829355019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.829355019
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1127755885
Short name T236
Test name
Test status
Simulation time 164399733 ps
CPU time 2.42 seconds
Started Jul 10 05:37:31 PM PDT 24
Finished Jul 10 05:37:35 PM PDT 24
Peak memory 198584 kb
Host smart-e3cc2801-9f29-4fca-b5ec-8db0322108e8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127755885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1127755885
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1868875435
Short name T196
Test name
Test status
Simulation time 142703907 ps
CPU time 1.97 seconds
Started Jul 10 05:37:30 PM PDT 24
Finished Jul 10 05:37:32 PM PDT 24
Peak memory 196464 kb
Host smart-99adfb91-dbba-484f-88e5-1c084179a82d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868875435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1868875435
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1589209608
Short name T267
Test name
Test status
Simulation time 136291461 ps
CPU time 0.75 seconds
Started Jul 10 05:37:25 PM PDT 24
Finished Jul 10 05:37:26 PM PDT 24
Peak memory 196776 kb
Host smart-3cfd6bd3-fb48-4b17-a328-143d2c733bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589209608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1589209608
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3028181219
Short name T278
Test name
Test status
Simulation time 117793461 ps
CPU time 0.74 seconds
Started Jul 10 05:37:28 PM PDT 24
Finished Jul 10 05:37:30 PM PDT 24
Peak memory 196108 kb
Host smart-1902c515-b9a6-433e-af4d-7dfd4a67c6e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028181219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3028181219
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2094562753
Short name T3
Test name
Test status
Simulation time 3203076880 ps
CPU time 5.21 seconds
Started Jul 10 05:37:32 PM PDT 24
Finished Jul 10 05:37:38 PM PDT 24
Peak memory 197984 kb
Host smart-eaca7e05-af22-40ff-ba08-2469315b2f71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094562753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2094562753
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1416197739
Short name T54
Test name
Test status
Simulation time 30739099 ps
CPU time 1.07 seconds
Started Jul 10 05:37:27 PM PDT 24
Finished Jul 10 05:37:29 PM PDT 24
Peak memory 196908 kb
Host smart-ec04d5bf-ebd4-4ba1-8879-230edb1aa9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416197739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1416197739
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3063976592
Short name T170
Test name
Test status
Simulation time 36619726 ps
CPU time 1.18 seconds
Started Jul 10 05:37:24 PM PDT 24
Finished Jul 10 05:37:26 PM PDT 24
Peak memory 196264 kb
Host smart-2b22f1b0-d3db-486b-937f-e5bfeea50beb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063976592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3063976592
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3829644050
Short name T548
Test name
Test status
Simulation time 15100211836 ps
CPU time 189.82 seconds
Started Jul 10 05:37:33 PM PDT 24
Finished Jul 10 05:40:43 PM PDT 24
Peak memory 198808 kb
Host smart-3e1f7c37-9078-4aaa-9e20-2cd87ec7fec8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829644050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3829644050
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.3225949808
Short name T668
Test name
Test status
Simulation time 344385667281 ps
CPU time 836.12 seconds
Started Jul 10 05:37:35 PM PDT 24
Finished Jul 10 05:51:32 PM PDT 24
Peak memory 207100 kb
Host smart-0030e8a2-dc22-4e96-8345-edad96af9f36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3225949808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.3225949808
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.426362444
Short name T581
Test name
Test status
Simulation time 46554150 ps
CPU time 0.58 seconds
Started Jul 10 05:37:39 PM PDT 24
Finished Jul 10 05:37:40 PM PDT 24
Peak memory 194640 kb
Host smart-bbdf6cb0-a09c-40d8-a335-7cb89aedff0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426362444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.426362444
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2294169644
Short name T525
Test name
Test status
Simulation time 52348177 ps
CPU time 0.65 seconds
Started Jul 10 05:37:38 PM PDT 24
Finished Jul 10 05:37:39 PM PDT 24
Peak memory 195372 kb
Host smart-bb9e6d63-8136-43d0-91d0-4fe5bc5c6c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294169644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2294169644
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2481670187
Short name T209
Test name
Test status
Simulation time 1526529200 ps
CPU time 14.52 seconds
Started Jul 10 05:37:37 PM PDT 24
Finished Jul 10 05:37:53 PM PDT 24
Peak memory 197508 kb
Host smart-bc91d781-48af-41b6-9aa4-1331b0bf865b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481670187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2481670187
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3796090590
Short name T436
Test name
Test status
Simulation time 73333385 ps
CPU time 0.75 seconds
Started Jul 10 05:37:40 PM PDT 24
Finished Jul 10 05:37:42 PM PDT 24
Peak memory 196544 kb
Host smart-22860a88-5ed4-4c2a-b822-521a80ea1d54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796090590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3796090590
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3351841870
Short name T653
Test name
Test status
Simulation time 61114324 ps
CPU time 1.03 seconds
Started Jul 10 05:37:39 PM PDT 24
Finished Jul 10 05:37:41 PM PDT 24
Peak memory 196744 kb
Host smart-9fdb6b8f-14ce-4a3a-96a8-fbd041db64c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351841870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3351841870
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3074635673
Short name T508
Test name
Test status
Simulation time 58242575 ps
CPU time 1.49 seconds
Started Jul 10 05:37:37 PM PDT 24
Finished Jul 10 05:37:39 PM PDT 24
Peak memory 197376 kb
Host smart-d6a616e1-e543-4b6a-a365-2a2b472927fd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074635673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3074635673
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1061360644
Short name T527
Test name
Test status
Simulation time 481464063 ps
CPU time 2.62 seconds
Started Jul 10 05:37:38 PM PDT 24
Finished Jul 10 05:37:42 PM PDT 24
Peak memory 198752 kb
Host smart-50b16c65-23f8-43d4-b17a-6428eb519a1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061360644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1061360644
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.4181883881
Short name T635
Test name
Test status
Simulation time 25171492 ps
CPU time 0.96 seconds
Started Jul 10 05:37:31 PM PDT 24
Finished Jul 10 05:37:33 PM PDT 24
Peak memory 196500 kb
Host smart-e2996c24-809d-4ff2-882b-9bf5041d2495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181883881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.4181883881
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3423054842
Short name T255
Test name
Test status
Simulation time 34969756 ps
CPU time 1.29 seconds
Started Jul 10 05:37:33 PM PDT 24
Finished Jul 10 05:37:35 PM PDT 24
Peak memory 198700 kb
Host smart-d35e4993-af31-4f3d-a2b1-d3039811dd27
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423054842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3423054842
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2175603653
Short name T293
Test name
Test status
Simulation time 538090099 ps
CPU time 4.48 seconds
Started Jul 10 05:37:37 PM PDT 24
Finished Jul 10 05:37:42 PM PDT 24
Peak memory 198652 kb
Host smart-741f502b-abe0-4936-b02e-ed503354d0ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175603653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2175603653
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1764169672
Short name T475
Test name
Test status
Simulation time 36433296 ps
CPU time 1.11 seconds
Started Jul 10 05:37:33 PM PDT 24
Finished Jul 10 05:37:35 PM PDT 24
Peak memory 196388 kb
Host smart-47d2e423-8a8e-4018-a3a3-89e0a0dc7663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764169672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1764169672
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2715131439
Short name T394
Test name
Test status
Simulation time 52952544 ps
CPU time 1.11 seconds
Started Jul 10 05:37:34 PM PDT 24
Finished Jul 10 05:37:37 PM PDT 24
Peak memory 196412 kb
Host smart-460fda79-a2c9-40fb-8d91-72c0a0a4b3b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715131439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2715131439
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3418081553
Short name T15
Test name
Test status
Simulation time 2479732301 ps
CPU time 73.63 seconds
Started Jul 10 05:37:38 PM PDT 24
Finished Jul 10 05:38:52 PM PDT 24
Peak memory 198776 kb
Host smart-32a7d5f0-6954-4ba4-986d-73bcde9313e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418081553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3418081553
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.846816759
Short name T503
Test name
Test status
Simulation time 43693869 ps
CPU time 0.57 seconds
Started Jul 10 05:37:48 PM PDT 24
Finished Jul 10 05:37:49 PM PDT 24
Peak memory 195364 kb
Host smart-d135be46-0565-41d3-a765-827d79157db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846816759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.846816759
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2714694310
Short name T476
Test name
Test status
Simulation time 18939246 ps
CPU time 0.67 seconds
Started Jul 10 05:37:43 PM PDT 24
Finished Jul 10 05:37:44 PM PDT 24
Peak memory 195380 kb
Host smart-1b12cef4-4400-43ab-9367-f066cb13b5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714694310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2714694310
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1869393319
Short name T666
Test name
Test status
Simulation time 4166410160 ps
CPU time 13.43 seconds
Started Jul 10 05:37:44 PM PDT 24
Finished Jul 10 05:37:58 PM PDT 24
Peak memory 197616 kb
Host smart-66dfc3cd-afc6-40f4-9343-7de9ba27a0c6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869393319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1869393319
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1351933073
Short name T693
Test name
Test status
Simulation time 61824001 ps
CPU time 0.92 seconds
Started Jul 10 05:37:52 PM PDT 24
Finished Jul 10 05:37:54 PM PDT 24
Peak memory 197792 kb
Host smart-b7caa305-ec0d-4f07-b756-d412dabf92d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351933073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1351933073
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2606088095
Short name T407
Test name
Test status
Simulation time 785889894 ps
CPU time 1.57 seconds
Started Jul 10 05:37:42 PM PDT 24
Finished Jul 10 05:37:44 PM PDT 24
Peak memory 197744 kb
Host smart-e8888d6d-9174-442b-8351-307b17586358
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606088095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2606088095
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2374616032
Short name T499
Test name
Test status
Simulation time 59025860 ps
CPU time 2.59 seconds
Started Jul 10 05:37:47 PM PDT 24
Finished Jul 10 05:37:50 PM PDT 24
Peak memory 198648 kb
Host smart-68dc627e-29f9-4bfb-83fd-d5ff93155ef6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374616032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2374616032
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2934803471
Short name T202
Test name
Test status
Simulation time 280788679 ps
CPU time 1.24 seconds
Started Jul 10 05:37:43 PM PDT 24
Finished Jul 10 05:37:45 PM PDT 24
Peak memory 197184 kb
Host smart-253ba83f-9cb6-43de-ba76-59c0887dd91a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934803471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2934803471
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2811663447
Short name T453
Test name
Test status
Simulation time 29581051 ps
CPU time 0.95 seconds
Started Jul 10 05:37:46 PM PDT 24
Finished Jul 10 05:37:47 PM PDT 24
Peak memory 196640 kb
Host smart-755bafb1-57a9-40bb-b5bb-bffc15a0db67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811663447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2811663447
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.4114052359
Short name T613
Test name
Test status
Simulation time 133917177 ps
CPU time 0.95 seconds
Started Jul 10 05:37:43 PM PDT 24
Finished Jul 10 05:37:44 PM PDT 24
Peak memory 196404 kb
Host smart-b96a41c9-09bf-488d-871b-66f41e68927e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114052359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.4114052359
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.3131481450
Short name T526
Test name
Test status
Simulation time 612674058 ps
CPU time 4.09 seconds
Started Jul 10 05:37:52 PM PDT 24
Finished Jul 10 05:37:57 PM PDT 24
Peak memory 198608 kb
Host smart-df6d2bd6-30ee-44c2-a3d6-1ca30d57c5b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131481450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.3131481450
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.483644720
Short name T488
Test name
Test status
Simulation time 161615996 ps
CPU time 1.52 seconds
Started Jul 10 05:37:37 PM PDT 24
Finished Jul 10 05:37:39 PM PDT 24
Peak memory 198700 kb
Host smart-80b6cc9a-796f-4363-8a29-798b38d4f6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483644720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.483644720
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3069975086
Short name T27
Test name
Test status
Simulation time 102051784 ps
CPU time 1.52 seconds
Started Jul 10 05:37:37 PM PDT 24
Finished Jul 10 05:37:40 PM PDT 24
Peak memory 197384 kb
Host smart-cbf183b9-5c76-4eb1-b9bd-ce5eea45e003
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069975086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3069975086
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.835253322
Short name T78
Test name
Test status
Simulation time 4411777711 ps
CPU time 120.94 seconds
Started Jul 10 05:37:49 PM PDT 24
Finished Jul 10 05:39:50 PM PDT 24
Peak memory 198676 kb
Host smart-64263b03-b899-45d7-b68b-3ce06c3f1e29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835253322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.835253322
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.3489663828
Short name T381
Test name
Test status
Simulation time 43660957063 ps
CPU time 1216.96 seconds
Started Jul 10 05:37:49 PM PDT 24
Finished Jul 10 05:58:07 PM PDT 24
Peak memory 198900 kb
Host smart-edcb0f4f-c81e-49e5-b574-539d05902539
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3489663828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.3489663828
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2489351262
Short name T219
Test name
Test status
Simulation time 12787245 ps
CPU time 0.56 seconds
Started Jul 10 05:37:58 PM PDT 24
Finished Jul 10 05:38:00 PM PDT 24
Peak memory 195328 kb
Host smart-7234d2fe-b06c-40ef-ac54-2b597eaea29c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489351262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2489351262
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1185993865
Short name T220
Test name
Test status
Simulation time 93563073 ps
CPU time 0.62 seconds
Started Jul 10 05:37:49 PM PDT 24
Finished Jul 10 05:37:50 PM PDT 24
Peak memory 195032 kb
Host smart-8f7c69c1-5645-4d16-b7c8-e753081e082a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185993865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1185993865
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3581581452
Short name T597
Test name
Test status
Simulation time 1183163440 ps
CPU time 16.95 seconds
Started Jul 10 05:37:51 PM PDT 24
Finished Jul 10 05:38:09 PM PDT 24
Peak memory 197272 kb
Host smart-ad4e2161-fd43-439a-92cb-4dee9e70397f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581581452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3581581452
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.659423065
Short name T387
Test name
Test status
Simulation time 42041794 ps
CPU time 0.71 seconds
Started Jul 10 05:37:57 PM PDT 24
Finished Jul 10 05:37:59 PM PDT 24
Peak memory 195276 kb
Host smart-778a9f67-6752-477a-ad66-ce371cfef9de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659423065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.659423065
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.244177432
Short name T411
Test name
Test status
Simulation time 159551256 ps
CPU time 1.19 seconds
Started Jul 10 05:37:51 PM PDT 24
Finished Jul 10 05:37:54 PM PDT 24
Peak memory 196740 kb
Host smart-48528703-94e0-4a13-b240-adc5a1238fce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244177432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.244177432
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2003162941
Short name T392
Test name
Test status
Simulation time 87244044 ps
CPU time 3.64 seconds
Started Jul 10 05:37:51 PM PDT 24
Finished Jul 10 05:37:55 PM PDT 24
Peak memory 197112 kb
Host smart-2d2b012c-714a-4cd8-bfa6-18bf36eebe1a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003162941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2003162941
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3899571902
Short name T462
Test name
Test status
Simulation time 334980704 ps
CPU time 2.44 seconds
Started Jul 10 05:37:50 PM PDT 24
Finished Jul 10 05:37:54 PM PDT 24
Peak memory 197812 kb
Host smart-a08cf3f4-cd4c-4f7d-abec-8166f6d15ec9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899571902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3899571902
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.749477141
Short name T198
Test name
Test status
Simulation time 17278130 ps
CPU time 0.68 seconds
Started Jul 10 05:37:50 PM PDT 24
Finished Jul 10 05:37:52 PM PDT 24
Peak memory 194988 kb
Host smart-00ec1757-8f83-483d-8b2b-c58eaa002c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749477141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.749477141
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.4179171108
Short name T695
Test name
Test status
Simulation time 70527308 ps
CPU time 0.66 seconds
Started Jul 10 05:37:50 PM PDT 24
Finished Jul 10 05:37:52 PM PDT 24
Peak memory 195600 kb
Host smart-930cf1a9-108d-48fd-9087-2db5f171b9a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179171108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.4179171108
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2883962471
Short name T440
Test name
Test status
Simulation time 1415233084 ps
CPU time 3.2 seconds
Started Jul 10 05:37:57 PM PDT 24
Finished Jul 10 05:38:01 PM PDT 24
Peak memory 198664 kb
Host smart-d678eb6d-3f6d-4a55-983b-b8f7e2c13dcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883962471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2883962471
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.113004894
Short name T171
Test name
Test status
Simulation time 163210388 ps
CPU time 0.99 seconds
Started Jul 10 05:37:51 PM PDT 24
Finished Jul 10 05:37:53 PM PDT 24
Peak memory 196324 kb
Host smart-89e3770b-401f-4d5e-99f9-75b19542463f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113004894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.113004894
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1228554088
Short name T197
Test name
Test status
Simulation time 83152608 ps
CPU time 0.79 seconds
Started Jul 10 05:37:50 PM PDT 24
Finished Jul 10 05:37:52 PM PDT 24
Peak memory 195956 kb
Host smart-ccaf6d3a-bbae-4e8a-9626-1b96c88a31ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228554088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1228554088
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.2681565219
Short name T616
Test name
Test status
Simulation time 36830625820 ps
CPU time 180.51 seconds
Started Jul 10 05:37:56 PM PDT 24
Finished Jul 10 05:40:58 PM PDT 24
Peak memory 198708 kb
Host smart-c90eb0ea-93e1-4d13-ab3a-b25aa5283e0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681565219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.2681565219
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.868007699
Short name T53
Test name
Test status
Simulation time 19586003 ps
CPU time 0.59 seconds
Started Jul 10 05:37:57 PM PDT 24
Finished Jul 10 05:37:59 PM PDT 24
Peak memory 195272 kb
Host smart-2a2cb60a-1ca3-4e59-a7af-ffdc2a63879a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868007699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.868007699
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.4136583711
Short name T330
Test name
Test status
Simulation time 64495187 ps
CPU time 0.66 seconds
Started Jul 10 05:37:57 PM PDT 24
Finished Jul 10 05:37:59 PM PDT 24
Peak memory 195336 kb
Host smart-cfff134f-76a1-4be7-a882-23a4e1329a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136583711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.4136583711
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2423648503
Short name T648
Test name
Test status
Simulation time 1449008097 ps
CPU time 21.73 seconds
Started Jul 10 05:37:57 PM PDT 24
Finished Jul 10 05:38:20 PM PDT 24
Peak memory 198676 kb
Host smart-90d8084f-ece1-4f7e-b1bf-1cddfbe53b19
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423648503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2423648503
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.626747947
Short name T464
Test name
Test status
Simulation time 62421921 ps
CPU time 0.97 seconds
Started Jul 10 05:37:57 PM PDT 24
Finished Jul 10 05:38:00 PM PDT 24
Peak memory 197060 kb
Host smart-e0e6e186-b551-473a-b666-fa1bd130dde0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626747947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.626747947
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.4218348050
Short name T593
Test name
Test status
Simulation time 43560976 ps
CPU time 0.88 seconds
Started Jul 10 05:37:58 PM PDT 24
Finished Jul 10 05:38:00 PM PDT 24
Peak memory 196064 kb
Host smart-1a41691a-f32a-46ba-a825-31aee59813d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218348050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.4218348050
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.507255998
Short name T334
Test name
Test status
Simulation time 176423798 ps
CPU time 3.37 seconds
Started Jul 10 05:37:57 PM PDT 24
Finished Jul 10 05:38:02 PM PDT 24
Peak memory 198660 kb
Host smart-06c63958-3c73-4609-8a14-a4883b118246
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507255998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.gpio_intr_with_filter_rand_intr_event.507255998
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2859923636
Short name T575
Test name
Test status
Simulation time 146324339 ps
CPU time 1.02 seconds
Started Jul 10 05:37:57 PM PDT 24
Finished Jul 10 05:37:59 PM PDT 24
Peak memory 196484 kb
Host smart-026c829f-6be4-41b3-9dcc-eab3a45ae28b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859923636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2859923636
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3595770277
Short name T675
Test name
Test status
Simulation time 57517003 ps
CPU time 1.53 seconds
Started Jul 10 05:37:57 PM PDT 24
Finished Jul 10 05:38:00 PM PDT 24
Peak memory 197684 kb
Host smart-ef5c3512-be9a-4445-a923-eb0f934a5550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595770277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3595770277
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.565871270
Short name T460
Test name
Test status
Simulation time 583047703 ps
CPU time 1.33 seconds
Started Jul 10 05:37:57 PM PDT 24
Finished Jul 10 05:38:00 PM PDT 24
Peak memory 198676 kb
Host smart-d6d691c6-1162-47eb-adc1-c3f12becb642
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565871270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.565871270
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2914279462
Short name T553
Test name
Test status
Simulation time 153176160 ps
CPU time 5.75 seconds
Started Jul 10 05:37:56 PM PDT 24
Finished Jul 10 05:38:03 PM PDT 24
Peak memory 198640 kb
Host smart-52c9af35-4c01-4f2d-ad0d-1e732acee927
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914279462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2914279462
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2708367376
Short name T312
Test name
Test status
Simulation time 58024591 ps
CPU time 1.01 seconds
Started Jul 10 05:37:54 PM PDT 24
Finished Jul 10 05:37:56 PM PDT 24
Peak memory 196516 kb
Host smart-f53080d3-1225-4b78-96fc-f6c72cfa53ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708367376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2708367376
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3217451968
Short name T224
Test name
Test status
Simulation time 46356907 ps
CPU time 1.41 seconds
Started Jul 10 05:37:56 PM PDT 24
Finished Jul 10 05:37:59 PM PDT 24
Peak memory 197616 kb
Host smart-d4692013-66a7-4476-9eba-4de7a4828c13
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217451968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3217451968
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.150311630
Short name T5
Test name
Test status
Simulation time 6861343073 ps
CPU time 68.07 seconds
Started Jul 10 05:37:55 PM PDT 24
Finished Jul 10 05:39:04 PM PDT 24
Peak memory 198812 kb
Host smart-caeedb5d-9265-4eb3-8f40-2565bfdd0079
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150311630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.150311630
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.3097955352
Short name T61
Test name
Test status
Simulation time 75178869717 ps
CPU time 1625.13 seconds
Started Jul 10 05:37:59 PM PDT 24
Finished Jul 10 06:05:05 PM PDT 24
Peak memory 198920 kb
Host smart-ad4b3a8f-f256-4cee-82e4-c62d16f63ec3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3097955352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.3097955352
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2833470769
Short name T641
Test name
Test status
Simulation time 18608216 ps
CPU time 0.61 seconds
Started Jul 10 05:38:00 PM PDT 24
Finished Jul 10 05:38:02 PM PDT 24
Peak memory 194768 kb
Host smart-d4668b81-b60b-47cf-a151-17c7a61b76ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833470769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2833470769
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3937587755
Short name T52
Test name
Test status
Simulation time 43881702 ps
CPU time 0.95 seconds
Started Jul 10 05:38:04 PM PDT 24
Finished Jul 10 05:38:06 PM PDT 24
Peak memory 196464 kb
Host smart-a78517eb-f234-46ff-8efe-b4ba7e572704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937587755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3937587755
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1642543159
Short name T190
Test name
Test status
Simulation time 381231759 ps
CPU time 20.7 seconds
Started Jul 10 05:38:06 PM PDT 24
Finished Jul 10 05:38:27 PM PDT 24
Peak memory 197800 kb
Host smart-02150c25-77ed-4d6f-87fe-f95399250d05
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642543159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1642543159
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2735714739
Short name T534
Test name
Test status
Simulation time 223176875 ps
CPU time 0.77 seconds
Started Jul 10 05:38:04 PM PDT 24
Finished Jul 10 05:38:06 PM PDT 24
Peak memory 197056 kb
Host smart-a31f563c-765c-46b8-af6d-ea5800d19339
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735714739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2735714739
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1465440133
Short name T449
Test name
Test status
Simulation time 235266856 ps
CPU time 0.94 seconds
Started Jul 10 05:38:03 PM PDT 24
Finished Jul 10 05:38:05 PM PDT 24
Peak memory 197476 kb
Host smart-c1d39b02-3289-4afd-84cb-df048c00e612
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465440133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1465440133
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1448388238
Short name T325
Test name
Test status
Simulation time 95138864 ps
CPU time 1.32 seconds
Started Jul 10 05:38:06 PM PDT 24
Finished Jul 10 05:38:08 PM PDT 24
Peak memory 198676 kb
Host smart-d3a60f84-3ac6-4267-ace1-c8a45d6c3ed3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448388238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1448388238
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2023638488
Short name T540
Test name
Test status
Simulation time 31604007 ps
CPU time 1.01 seconds
Started Jul 10 05:38:01 PM PDT 24
Finished Jul 10 05:38:03 PM PDT 24
Peak memory 196284 kb
Host smart-34d8d28c-aed1-4370-8970-96ef9df29fd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023638488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2023638488
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.776787406
Short name T461
Test name
Test status
Simulation time 26968006 ps
CPU time 0.83 seconds
Started Jul 10 05:38:03 PM PDT 24
Finished Jul 10 05:38:05 PM PDT 24
Peak memory 196788 kb
Host smart-d869a72b-5f14-42d1-9f1b-cd864ef0e69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776787406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.776787406
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3479548041
Short name T168
Test name
Test status
Simulation time 27557490 ps
CPU time 1.05 seconds
Started Jul 10 05:38:03 PM PDT 24
Finished Jul 10 05:38:05 PM PDT 24
Peak memory 196660 kb
Host smart-bad9d134-c24b-4411-8335-c1e3bb69fb4e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479548041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3479548041
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.346825106
Short name T331
Test name
Test status
Simulation time 27354200 ps
CPU time 1.34 seconds
Started Jul 10 05:38:02 PM PDT 24
Finished Jul 10 05:38:04 PM PDT 24
Peak memory 198696 kb
Host smart-e2baa9ca-935c-411c-bedd-29b4501e00dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346825106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.346825106
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3810133597
Short name T144
Test name
Test status
Simulation time 61965189 ps
CPU time 0.76 seconds
Started Jul 10 05:38:06 PM PDT 24
Finished Jul 10 05:38:08 PM PDT 24
Peak memory 195892 kb
Host smart-35bc8bac-a881-47f2-9ef6-cc242c3d2ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810133597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3810133597
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2883628634
Short name T22
Test name
Test status
Simulation time 164569837 ps
CPU time 1.28 seconds
Started Jul 10 05:38:03 PM PDT 24
Finished Jul 10 05:38:05 PM PDT 24
Peak memory 196424 kb
Host smart-1d8d0afe-cb9a-451d-966b-abedad346216
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883628634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2883628634
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2613127059
Short name T397
Test name
Test status
Simulation time 41035055218 ps
CPU time 121.62 seconds
Started Jul 10 05:38:03 PM PDT 24
Finished Jul 10 05:40:05 PM PDT 24
Peak memory 198684 kb
Host smart-f3ca2c02-f334-4d49-84e3-a3faf8b041f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613127059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2613127059
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.466950293
Short name T505
Test name
Test status
Simulation time 320426212313 ps
CPU time 1393.06 seconds
Started Jul 10 05:38:01 PM PDT 24
Finished Jul 10 06:01:15 PM PDT 24
Peak memory 198904 kb
Host smart-54abd296-bc09-4d46-97ce-3df24c9d8d38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=466950293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.466950293
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.943850283
Short name T463
Test name
Test status
Simulation time 23756187 ps
CPU time 0.55 seconds
Started Jul 10 05:38:08 PM PDT 24
Finished Jul 10 05:38:10 PM PDT 24
Peak memory 195328 kb
Host smart-3d909fac-a962-4ecd-a8f0-8caa67b5ca9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943850283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.943850283
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1919465269
Short name T429
Test name
Test status
Simulation time 15254313 ps
CPU time 0.64 seconds
Started Jul 10 05:38:06 PM PDT 24
Finished Jul 10 05:38:08 PM PDT 24
Peak memory 194612 kb
Host smart-d89bb725-ab5c-4a77-9f16-f16a25b4c856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919465269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1919465269
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.200297672
Short name T309
Test name
Test status
Simulation time 1619103787 ps
CPU time 26.28 seconds
Started Jul 10 05:38:08 PM PDT 24
Finished Jul 10 05:38:36 PM PDT 24
Peak memory 198652 kb
Host smart-b16bf601-6128-4b85-8c4e-bfb90ba5f6c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200297672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.200297672
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2410672475
Short name T622
Test name
Test status
Simulation time 146321152 ps
CPU time 1.09 seconds
Started Jul 10 05:38:09 PM PDT 24
Finished Jul 10 05:38:11 PM PDT 24
Peak memory 198648 kb
Host smart-e3efb50c-f088-4351-9f05-020c29da3870
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410672475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2410672475
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2563022220
Short name T482
Test name
Test status
Simulation time 39532970 ps
CPU time 0.79 seconds
Started Jul 10 05:38:06 PM PDT 24
Finished Jul 10 05:38:08 PM PDT 24
Peak memory 196136 kb
Host smart-28d6a82f-949b-449f-8c61-aa689ebfd61f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563022220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2563022220
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3345100727
Short name T650
Test name
Test status
Simulation time 91281694 ps
CPU time 3.99 seconds
Started Jul 10 05:38:07 PM PDT 24
Finished Jul 10 05:38:12 PM PDT 24
Peak memory 198672 kb
Host smart-6d734751-d3c1-4cf3-9abe-74e771f6e039
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345100727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3345100727
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.350030502
Short name T494
Test name
Test status
Simulation time 128712533 ps
CPU time 2.46 seconds
Started Jul 10 05:38:07 PM PDT 24
Finished Jul 10 05:38:11 PM PDT 24
Peak memory 196468 kb
Host smart-10e75df0-ff00-428c-9cbd-7424ead16015
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350030502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
350030502
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3687438172
Short name T599
Test name
Test status
Simulation time 51101798 ps
CPU time 1.1 seconds
Started Jul 10 05:38:08 PM PDT 24
Finished Jul 10 05:38:10 PM PDT 24
Peak memory 196588 kb
Host smart-a5451a53-bca6-4e50-bc9d-ed1a8f85149d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687438172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3687438172
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.329465235
Short name T140
Test name
Test status
Simulation time 45815269 ps
CPU time 0.96 seconds
Started Jul 10 05:38:08 PM PDT 24
Finished Jul 10 05:38:10 PM PDT 24
Peak memory 196668 kb
Host smart-33f89ffd-1dd1-45f1-b0aa-f46f725bd4d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329465235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.329465235
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2792149514
Short name T477
Test name
Test status
Simulation time 1154162467 ps
CPU time 6.51 seconds
Started Jul 10 05:38:08 PM PDT 24
Finished Jul 10 05:38:15 PM PDT 24
Peak memory 197820 kb
Host smart-95ff20f6-ea4f-428f-81dd-678878969353
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792149514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2792149514
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2123806034
Short name T158
Test name
Test status
Simulation time 245957758 ps
CPU time 0.89 seconds
Started Jul 10 05:38:01 PM PDT 24
Finished Jul 10 05:38:03 PM PDT 24
Peak memory 195812 kb
Host smart-526c67fb-aa22-4b3d-8409-034d6a05095c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123806034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2123806034
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3878053534
Short name T329
Test name
Test status
Simulation time 95233463 ps
CPU time 0.87 seconds
Started Jul 10 05:38:00 PM PDT 24
Finished Jul 10 05:38:02 PM PDT 24
Peak memory 196012 kb
Host smart-c900a726-5108-43c9-ba68-fc1534b9ee20
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878053534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3878053534
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3703765187
Short name T273
Test name
Test status
Simulation time 10512730839 ps
CPU time 73.98 seconds
Started Jul 10 05:38:08 PM PDT 24
Finished Jul 10 05:39:23 PM PDT 24
Peak memory 198732 kb
Host smart-67096dd9-6e2a-4051-b493-11c7eb8339f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703765187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3703765187
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3113504056
Short name T115
Test name
Test status
Simulation time 14547289 ps
CPU time 0.6 seconds
Started Jul 10 05:38:12 PM PDT 24
Finished Jul 10 05:38:14 PM PDT 24
Peak memory 194636 kb
Host smart-dba81a06-62cd-410d-b255-5a57338464ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113504056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3113504056
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2017726132
Short name T65
Test name
Test status
Simulation time 48252502 ps
CPU time 0.83 seconds
Started Jul 10 05:38:13 PM PDT 24
Finished Jul 10 05:38:15 PM PDT 24
Peak memory 196120 kb
Host smart-69ac36a9-842c-46b1-a658-810d7771848b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017726132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2017726132
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1024929867
Short name T150
Test name
Test status
Simulation time 1980557480 ps
CPU time 28.55 seconds
Started Jul 10 05:38:11 PM PDT 24
Finished Jul 10 05:38:41 PM PDT 24
Peak memory 197524 kb
Host smart-af6f4992-436a-4378-bf36-eb21ea00c25d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024929867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1024929867
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3138007125
Short name T700
Test name
Test status
Simulation time 75205584 ps
CPU time 0.99 seconds
Started Jul 10 05:38:14 PM PDT 24
Finished Jul 10 05:38:16 PM PDT 24
Peak memory 198472 kb
Host smart-59c6e774-8cbc-44f2-8d7a-33e86f341585
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138007125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3138007125
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2490400341
Short name T386
Test name
Test status
Simulation time 49526894 ps
CPU time 1.27 seconds
Started Jul 10 05:38:12 PM PDT 24
Finished Jul 10 05:38:15 PM PDT 24
Peak memory 197196 kb
Host smart-aa504554-5127-4c98-a733-13f7ea8f6c07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490400341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2490400341
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2320214877
Short name T574
Test name
Test status
Simulation time 48212435 ps
CPU time 1.92 seconds
Started Jul 10 05:38:13 PM PDT 24
Finished Jul 10 05:38:16 PM PDT 24
Peak memory 198428 kb
Host smart-1fea5330-db45-45c7-af81-48b2f9f44aac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320214877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2320214877
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2134649267
Short name T285
Test name
Test status
Simulation time 86317122 ps
CPU time 0.83 seconds
Started Jul 10 05:38:11 PM PDT 24
Finished Jul 10 05:38:14 PM PDT 24
Peak memory 195144 kb
Host smart-708a4d84-7758-43b8-88b5-66127bfb3456
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134649267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2134649267
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1129500010
Short name T619
Test name
Test status
Simulation time 148881341 ps
CPU time 1.43 seconds
Started Jul 10 05:38:08 PM PDT 24
Finished Jul 10 05:38:10 PM PDT 24
Peak memory 196540 kb
Host smart-6c90aea7-6dc0-49c4-ae9d-20c5848f722e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129500010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1129500010
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2156206767
Short name T156
Test name
Test status
Simulation time 53266985 ps
CPU time 1.25 seconds
Started Jul 10 05:38:07 PM PDT 24
Finished Jul 10 05:38:09 PM PDT 24
Peak memory 197396 kb
Host smart-642a1d95-a19f-441f-904d-a3655886fdd3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156206767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.2156206767
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1865946666
Short name T589
Test name
Test status
Simulation time 75499847 ps
CPU time 2.24 seconds
Started Jul 10 05:38:15 PM PDT 24
Finished Jul 10 05:38:18 PM PDT 24
Peak memory 198596 kb
Host smart-13f64ab9-8965-451e-b3d9-80072821e134
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865946666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1865946666
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3986578332
Short name T355
Test name
Test status
Simulation time 53598609 ps
CPU time 0.88 seconds
Started Jul 10 05:38:08 PM PDT 24
Finished Jul 10 05:38:10 PM PDT 24
Peak memory 197148 kb
Host smart-39862e29-178a-4f93-a5fc-824ce9f8ccb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986578332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3986578332
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1567613326
Short name T442
Test name
Test status
Simulation time 299766421 ps
CPU time 1.15 seconds
Started Jul 10 05:38:06 PM PDT 24
Finished Jul 10 05:38:08 PM PDT 24
Peak memory 196196 kb
Host smart-f2774f88-8f24-4768-b1fa-e823e4493d97
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567613326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1567613326
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1080031736
Short name T324
Test name
Test status
Simulation time 3089137445 ps
CPU time 79.31 seconds
Started Jul 10 05:38:12 PM PDT 24
Finished Jul 10 05:39:32 PM PDT 24
Peak memory 198788 kb
Host smart-0a17beb1-be63-47ca-93fd-04c742939650
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080031736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1080031736
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.3472358095
Short name T558
Test name
Test status
Simulation time 11970495 ps
CPU time 0.55 seconds
Started Jul 10 05:38:18 PM PDT 24
Finished Jul 10 05:38:19 PM PDT 24
Peak memory 194628 kb
Host smart-a457c573-ce1a-40ed-87b4-62d3c543ef3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472358095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3472358095
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.401283864
Short name T131
Test name
Test status
Simulation time 127972555 ps
CPU time 0.94 seconds
Started Jul 10 05:38:20 PM PDT 24
Finished Jul 10 05:38:22 PM PDT 24
Peak memory 197620 kb
Host smart-a2a7f3e9-4ee2-4b25-9378-b0e8f6d6d16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401283864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.401283864
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3567722208
Short name T215
Test name
Test status
Simulation time 490751616 ps
CPU time 23.11 seconds
Started Jul 10 05:38:22 PM PDT 24
Finished Jul 10 05:38:46 PM PDT 24
Peak memory 197720 kb
Host smart-346efb6c-bbab-4375-988c-494951de1e71
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567722208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3567722208
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3129301573
Short name T216
Test name
Test status
Simulation time 191990545 ps
CPU time 0.9 seconds
Started Jul 10 05:38:18 PM PDT 24
Finished Jul 10 05:38:20 PM PDT 24
Peak memory 196596 kb
Host smart-a9094313-f21c-441e-80d3-b11959561fe9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129301573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3129301573
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2978463205
Short name T380
Test name
Test status
Simulation time 72186236 ps
CPU time 0.77 seconds
Started Jul 10 05:38:20 PM PDT 24
Finished Jul 10 05:38:22 PM PDT 24
Peak memory 196096 kb
Host smart-ecb8f2b9-8c93-4e3f-91ba-b353e51f1ff7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978463205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2978463205
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1376424884
Short name T328
Test name
Test status
Simulation time 329638691 ps
CPU time 1.1 seconds
Started Jul 10 05:38:19 PM PDT 24
Finished Jul 10 05:38:22 PM PDT 24
Peak memory 198172 kb
Host smart-204d16ae-f859-4bba-acf5-bf759dd3cde0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376424884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1376424884
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.559785073
Short name T183
Test name
Test status
Simulation time 122098319 ps
CPU time 2.16 seconds
Started Jul 10 05:38:19 PM PDT 24
Finished Jul 10 05:38:23 PM PDT 24
Peak memory 196740 kb
Host smart-36782ae3-a240-4d5f-b6b9-93e7e8b28551
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559785073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
559785073
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2475479307
Short name T318
Test name
Test status
Simulation time 122133522 ps
CPU time 1.36 seconds
Started Jul 10 05:38:19 PM PDT 24
Finished Jul 10 05:38:21 PM PDT 24
Peak memory 196480 kb
Host smart-c7e1a9b2-17a8-4914-8fbb-4790ca763a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475479307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2475479307
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3907342200
Short name T169
Test name
Test status
Simulation time 43701675 ps
CPU time 1.01 seconds
Started Jul 10 05:38:21 PM PDT 24
Finished Jul 10 05:38:23 PM PDT 24
Peak memory 196528 kb
Host smart-1b6f360b-a214-49dc-b799-26010ea09c4a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907342200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3907342200
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2325152652
Short name T182
Test name
Test status
Simulation time 542417417 ps
CPU time 6.47 seconds
Started Jul 10 05:38:20 PM PDT 24
Finished Jul 10 05:38:28 PM PDT 24
Peak memory 198604 kb
Host smart-931481f8-d112-4b13-91d4-595e277e2538
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325152652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2325152652
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2750659431
Short name T469
Test name
Test status
Simulation time 216764425 ps
CPU time 1.02 seconds
Started Jul 10 05:38:12 PM PDT 24
Finished Jul 10 05:38:15 PM PDT 24
Peak memory 196200 kb
Host smart-ef90f4a5-d988-401c-a2b0-758457dfe18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750659431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2750659431
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.57117522
Short name T260
Test name
Test status
Simulation time 98340396 ps
CPU time 1 seconds
Started Jul 10 05:38:14 PM PDT 24
Finished Jul 10 05:38:16 PM PDT 24
Peak memory 196420 kb
Host smart-951c2c06-59bf-4206-8b11-9a07ea15c799
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57117522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.57117522
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.2658362862
Short name T438
Test name
Test status
Simulation time 28622530400 ps
CPU time 140.4 seconds
Started Jul 10 05:38:21 PM PDT 24
Finished Jul 10 05:40:43 PM PDT 24
Peak memory 198808 kb
Host smart-9f717306-20dd-47c0-83f6-1b8dbf52346a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658362862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2658362862
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.330579464
Short name T632
Test name
Test status
Simulation time 46663638 ps
CPU time 0.59 seconds
Started Jul 10 05:38:32 PM PDT 24
Finished Jul 10 05:38:33 PM PDT 24
Peak memory 194648 kb
Host smart-536bbe0a-c74b-4732-bbe1-4caba2638c67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330579464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.330579464
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1479336716
Short name T681
Test name
Test status
Simulation time 79657897 ps
CPU time 0.8 seconds
Started Jul 10 05:38:25 PM PDT 24
Finished Jul 10 05:38:27 PM PDT 24
Peak memory 195840 kb
Host smart-43441d00-c47b-4338-86f1-3c7ee15647e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479336716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1479336716
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.2129132150
Short name T222
Test name
Test status
Simulation time 6925698338 ps
CPU time 28.15 seconds
Started Jul 10 05:38:30 PM PDT 24
Finished Jul 10 05:38:59 PM PDT 24
Peak memory 198088 kb
Host smart-fcb8d490-641a-45e8-9f5d-2277ec7af040
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129132150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.2129132150
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3482043201
Short name T443
Test name
Test status
Simulation time 23305183 ps
CPU time 0.69 seconds
Started Jul 10 05:38:30 PM PDT 24
Finished Jul 10 05:38:31 PM PDT 24
Peak memory 195156 kb
Host smart-e5a8d04c-2410-4234-b507-56bbf04f2299
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482043201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3482043201
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3542877482
Short name T446
Test name
Test status
Simulation time 105387977 ps
CPU time 0.87 seconds
Started Jul 10 05:38:27 PM PDT 24
Finished Jul 10 05:38:28 PM PDT 24
Peak memory 197320 kb
Host smart-18c28fab-de79-4895-95d8-41c0dc7b3d4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542877482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3542877482
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3026780611
Short name T655
Test name
Test status
Simulation time 57617002 ps
CPU time 2.2 seconds
Started Jul 10 05:38:31 PM PDT 24
Finished Jul 10 05:38:34 PM PDT 24
Peak memory 198724 kb
Host smart-adb737e6-beb5-49ef-894f-02ca94a59cef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026780611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3026780611
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1340651775
Short name T716
Test name
Test status
Simulation time 35963233 ps
CPU time 1.06 seconds
Started Jul 10 05:38:32 PM PDT 24
Finished Jul 10 05:38:34 PM PDT 24
Peak memory 196076 kb
Host smart-a3fcac4c-46aa-4775-b5af-5d3090ffcfce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340651775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1340651775
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2303378283
Short name T679
Test name
Test status
Simulation time 40398620 ps
CPU time 1.02 seconds
Started Jul 10 05:38:23 PM PDT 24
Finished Jul 10 05:38:25 PM PDT 24
Peak memory 196596 kb
Host smart-4b2a613e-c07d-4f90-aced-a4cd8338fe29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303378283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2303378283
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3330036873
Short name T435
Test name
Test status
Simulation time 258318797 ps
CPU time 0.91 seconds
Started Jul 10 05:38:25 PM PDT 24
Finished Jul 10 05:38:27 PM PDT 24
Peak memory 197436 kb
Host smart-d8ebc0ba-ef0d-4d12-a1bf-8b6a5e3acd27
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330036873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3330036873
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2566662258
Short name T11
Test name
Test status
Simulation time 223385031 ps
CPU time 5.31 seconds
Started Jul 10 05:38:30 PM PDT 24
Finished Jul 10 05:38:37 PM PDT 24
Peak memory 198624 kb
Host smart-0cd78d9d-0b24-4264-b8bb-be7478f21d80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566662258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2566662258
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2897467812
Short name T417
Test name
Test status
Simulation time 31826002 ps
CPU time 0.96 seconds
Started Jul 10 05:38:23 PM PDT 24
Finished Jul 10 05:38:25 PM PDT 24
Peak memory 197044 kb
Host smart-a060584e-6a0b-4106-8103-f807d13fe8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897467812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2897467812
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1665670201
Short name T713
Test name
Test status
Simulation time 73335857 ps
CPU time 1.19 seconds
Started Jul 10 05:38:26 PM PDT 24
Finished Jul 10 05:38:28 PM PDT 24
Peak memory 196392 kb
Host smart-28d0e847-4cb7-4d40-84ba-34ade5141b37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665670201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1665670201
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.4088390494
Short name T706
Test name
Test status
Simulation time 8416546147 ps
CPU time 221.38 seconds
Started Jul 10 05:38:32 PM PDT 24
Finished Jul 10 05:42:14 PM PDT 24
Peak memory 198772 kb
Host smart-e638ad03-6cbe-4c48-9fb3-c32a7fa883c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088390494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.4088390494
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.4164513470
Short name T444
Test name
Test status
Simulation time 26546316 ps
CPU time 0.55 seconds
Started Jul 10 05:34:38 PM PDT 24
Finished Jul 10 05:34:39 PM PDT 24
Peak memory 193444 kb
Host smart-205b9404-b8e2-4a01-98f4-d9b3cb096306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164513470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.4164513470
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1341510571
Short name T73
Test name
Test status
Simulation time 113261996 ps
CPU time 0.89 seconds
Started Jul 10 05:34:27 PM PDT 24
Finished Jul 10 05:34:29 PM PDT 24
Peak memory 196664 kb
Host smart-cfe691c1-f750-4475-b72c-8e41b0e188d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341510571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1341510571
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2169536903
Short name T412
Test name
Test status
Simulation time 330863098 ps
CPU time 8.81 seconds
Started Jul 10 05:34:27 PM PDT 24
Finished Jul 10 05:34:37 PM PDT 24
Peak memory 197524 kb
Host smart-c0625516-1366-4bd2-b560-73587d297b7d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169536903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2169536903
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1726513104
Short name T195
Test name
Test status
Simulation time 26294436 ps
CPU time 0.68 seconds
Started Jul 10 05:34:34 PM PDT 24
Finished Jul 10 05:34:35 PM PDT 24
Peak memory 195140 kb
Host smart-a3396e41-3cf3-45f5-8b5b-0965aa8cfe8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726513104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1726513104
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1433704154
Short name T560
Test name
Test status
Simulation time 128240125 ps
CPU time 1.28 seconds
Started Jul 10 05:34:29 PM PDT 24
Finished Jul 10 05:34:32 PM PDT 24
Peak memory 196808 kb
Host smart-d594d625-388a-4ecc-b475-d30321b9af6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433704154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1433704154
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1248086529
Short name T79
Test name
Test status
Simulation time 133946262 ps
CPU time 1.65 seconds
Started Jul 10 05:34:27 PM PDT 24
Finished Jul 10 05:34:30 PM PDT 24
Peak memory 196940 kb
Host smart-5c9189c2-33fb-44c7-b126-4b126662e1b4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248086529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1248086529
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.4282683680
Short name T223
Test name
Test status
Simulation time 59644692 ps
CPU time 1.24 seconds
Started Jul 10 05:34:37 PM PDT 24
Finished Jul 10 05:34:39 PM PDT 24
Peak memory 197200 kb
Host smart-1fac78b8-4207-48f6-9bd5-dc60616f8e32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282683680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
4282683680
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.465828087
Short name T264
Test name
Test status
Simulation time 312625511 ps
CPU time 0.75 seconds
Started Jul 10 05:34:21 PM PDT 24
Finished Jul 10 05:34:22 PM PDT 24
Peak memory 196780 kb
Host smart-0e3ee15e-8117-4a84-bd0c-c12eea334678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465828087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.465828087
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3185900242
Short name T141
Test name
Test status
Simulation time 24134884 ps
CPU time 0.63 seconds
Started Jul 10 05:34:22 PM PDT 24
Finished Jul 10 05:34:23 PM PDT 24
Peak memory 194956 kb
Host smart-8dff592a-1d39-446b-aee3-29fec78ffe05
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185900242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3185900242
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.4189368534
Short name T317
Test name
Test status
Simulation time 183278110 ps
CPU time 1.9 seconds
Started Jul 10 05:34:27 PM PDT 24
Finished Jul 10 05:34:30 PM PDT 24
Peak memory 198548 kb
Host smart-e434bfe2-8422-4a3a-8ec5-5d5475cc8e79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189368534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.4189368534
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2979473721
Short name T49
Test name
Test status
Simulation time 37074353 ps
CPU time 0.81 seconds
Started Jul 10 05:34:36 PM PDT 24
Finished Jul 10 05:34:37 PM PDT 24
Peak memory 214324 kb
Host smart-3cb64520-98cf-4aad-9470-7f4a864fefa5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979473721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2979473721
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1742993429
Short name T690
Test name
Test status
Simulation time 63566808 ps
CPU time 0.97 seconds
Started Jul 10 05:34:23 PM PDT 24
Finished Jul 10 05:34:25 PM PDT 24
Peak memory 196628 kb
Host smart-a2efa2f4-85be-4970-9ce1-f69d70e717ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742993429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1742993429
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3687629955
Short name T496
Test name
Test status
Simulation time 152070533 ps
CPU time 1.29 seconds
Started Jul 10 05:34:22 PM PDT 24
Finished Jul 10 05:34:24 PM PDT 24
Peak memory 196116 kb
Host smart-225fd0d6-9856-4210-a97f-fdd43a82b285
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687629955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3687629955
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2353502041
Short name T371
Test name
Test status
Simulation time 14572695918 ps
CPU time 150.46 seconds
Started Jul 10 05:34:29 PM PDT 24
Finished Jul 10 05:37:01 PM PDT 24
Peak memory 198648 kb
Host smart-3abe0d01-ee4c-4e05-bf32-49740018fe0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353502041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2353502041
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.3467016076
Short name T714
Test name
Test status
Simulation time 71216705257 ps
CPU time 1617.01 seconds
Started Jul 10 05:34:28 PM PDT 24
Finished Jul 10 06:01:26 PM PDT 24
Peak memory 198856 kb
Host smart-5bf909a5-5219-4016-877f-a071e7429fc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3467016076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.3467016076
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1171139339
Short name T513
Test name
Test status
Simulation time 22651114 ps
CPU time 0.6 seconds
Started Jul 10 05:38:37 PM PDT 24
Finished Jul 10 05:38:39 PM PDT 24
Peak memory 195608 kb
Host smart-46ca2e01-42a4-4c7f-9e7a-eea17c7cbf3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171139339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1171139339
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1618580585
Short name T580
Test name
Test status
Simulation time 100835071 ps
CPU time 0.84 seconds
Started Jul 10 05:38:37 PM PDT 24
Finished Jul 10 05:38:40 PM PDT 24
Peak memory 195860 kb
Host smart-e0c66e43-b493-424f-ad78-1ff2c15fc06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618580585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1618580585
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1397427914
Short name T287
Test name
Test status
Simulation time 1143949580 ps
CPU time 19.56 seconds
Started Jul 10 05:38:38 PM PDT 24
Finished Jul 10 05:38:59 PM PDT 24
Peak memory 196104 kb
Host smart-ae52582c-6d72-4fda-b8f6-c52ea26835b3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397427914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1397427914
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3426641705
Short name T718
Test name
Test status
Simulation time 108701101 ps
CPU time 1 seconds
Started Jul 10 05:38:38 PM PDT 24
Finished Jul 10 05:38:40 PM PDT 24
Peak memory 196964 kb
Host smart-4cbf02cd-bcb0-4b3d-a856-574c8209e9bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426641705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3426641705
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3544101283
Short name T478
Test name
Test status
Simulation time 85045129 ps
CPU time 0.85 seconds
Started Jul 10 05:38:37 PM PDT 24
Finished Jul 10 05:38:39 PM PDT 24
Peak memory 196240 kb
Host smart-45205a70-d8ed-4736-a7a6-d4468afed8cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544101283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3544101283
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.770919817
Short name T447
Test name
Test status
Simulation time 74951196 ps
CPU time 2.95 seconds
Started Jul 10 05:38:37 PM PDT 24
Finished Jul 10 05:38:41 PM PDT 24
Peak memory 198704 kb
Host smart-ceff8b71-35de-4725-a19f-198ec8cad611
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770919817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.770919817
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.1708673892
Short name T230
Test name
Test status
Simulation time 228990579 ps
CPU time 2.41 seconds
Started Jul 10 05:38:36 PM PDT 24
Finished Jul 10 05:38:40 PM PDT 24
Peak memory 197928 kb
Host smart-a34f3547-09e7-4310-a94a-a931c35d8932
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708673892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.1708673892
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3815451567
Short name T521
Test name
Test status
Simulation time 48565838 ps
CPU time 0.88 seconds
Started Jul 10 05:38:29 PM PDT 24
Finished Jul 10 05:38:30 PM PDT 24
Peak memory 196584 kb
Host smart-a445131d-4335-42a5-8fb8-a18bd2697bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815451567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3815451567
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3857466269
Short name T289
Test name
Test status
Simulation time 203796127 ps
CPU time 1.24 seconds
Started Jul 10 05:38:36 PM PDT 24
Finished Jul 10 05:38:38 PM PDT 24
Peak memory 198708 kb
Host smart-9a06e810-e29c-4f5b-9837-b1a7b420a6db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857466269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3857466269
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.92041026
Short name T9
Test name
Test status
Simulation time 551002921 ps
CPU time 6.68 seconds
Started Jul 10 05:38:36 PM PDT 24
Finished Jul 10 05:38:44 PM PDT 24
Peak memory 198644 kb
Host smart-962bb795-f168-4da9-b42f-aaf941a2c2de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92041026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand
om_long_reg_writes_reg_reads.92041026
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3745181771
Short name T258
Test name
Test status
Simulation time 187948584 ps
CPU time 1.41 seconds
Started Jul 10 05:38:30 PM PDT 24
Finished Jul 10 05:38:33 PM PDT 24
Peak memory 197436 kb
Host smart-2cc50def-e519-418d-85d7-39ac58503d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745181771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3745181771
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.433005368
Short name T549
Test name
Test status
Simulation time 131503559 ps
CPU time 1.16 seconds
Started Jul 10 05:38:28 PM PDT 24
Finished Jul 10 05:38:30 PM PDT 24
Peak memory 197556 kb
Host smart-da7c503e-24d4-4837-8e02-7b0f4e8422b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433005368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.433005368
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3211056082
Short name T437
Test name
Test status
Simulation time 56229251124 ps
CPU time 183.97 seconds
Started Jul 10 05:38:38 PM PDT 24
Finished Jul 10 05:41:43 PM PDT 24
Peak memory 198800 kb
Host smart-dad1509f-4723-446d-aeb0-8d863d89dc1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211056082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3211056082
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.3616828111
Short name T57
Test name
Test status
Simulation time 258252335703 ps
CPU time 1407.83 seconds
Started Jul 10 05:38:37 PM PDT 24
Finished Jul 10 06:02:06 PM PDT 24
Peak memory 207088 kb
Host smart-ac1976b6-f28e-443a-8b51-050f62bb1777
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3616828111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.3616828111
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2489421530
Short name T572
Test name
Test status
Simulation time 13391389 ps
CPU time 0.59 seconds
Started Jul 10 05:38:44 PM PDT 24
Finished Jul 10 05:38:45 PM PDT 24
Peak memory 194628 kb
Host smart-4b486fb3-1a6a-4f5c-b1a5-866883509904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489421530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2489421530
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.374893222
Short name T135
Test name
Test status
Simulation time 16626535 ps
CPU time 0.62 seconds
Started Jul 10 05:38:37 PM PDT 24
Finished Jul 10 05:38:39 PM PDT 24
Peak memory 194560 kb
Host smart-de2bfd62-1e37-43a6-91c7-0c6271900639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374893222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.374893222
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3333803914
Short name T688
Test name
Test status
Simulation time 714605861 ps
CPU time 10.63 seconds
Started Jul 10 05:38:42 PM PDT 24
Finished Jul 10 05:38:54 PM PDT 24
Peak memory 196088 kb
Host smart-9ae1851e-b7db-4126-8612-8f4f845217f8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333803914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3333803914
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1232563799
Short name T425
Test name
Test status
Simulation time 41168460 ps
CPU time 0.82 seconds
Started Jul 10 05:38:43 PM PDT 24
Finished Jul 10 05:38:45 PM PDT 24
Peak memory 197296 kb
Host smart-03159a28-2aee-4bb5-b924-3550faa35d04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232563799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1232563799
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3188586314
Short name T682
Test name
Test status
Simulation time 22192464 ps
CPU time 0.78 seconds
Started Jul 10 05:38:41 PM PDT 24
Finished Jul 10 05:38:42 PM PDT 24
Peak memory 196060 kb
Host smart-1ca3c32f-68db-4b08-a03a-43eb1c805db6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188586314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3188586314
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.305399428
Short name T391
Test name
Test status
Simulation time 33919971 ps
CPU time 0.99 seconds
Started Jul 10 05:38:45 PM PDT 24
Finished Jul 10 05:38:47 PM PDT 24
Peak memory 196916 kb
Host smart-0f4d0634-7193-4d29-b6b3-9e21d26d5db4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305399428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.305399428
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3535464878
Short name T207
Test name
Test status
Simulation time 303806381 ps
CPU time 2.59 seconds
Started Jul 10 05:38:46 PM PDT 24
Finished Jul 10 05:38:49 PM PDT 24
Peak memory 197968 kb
Host smart-2c8a5473-8551-4704-ab84-a264b23d6ce9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535464878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3535464878
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.626762871
Short name T203
Test name
Test status
Simulation time 162187588 ps
CPU time 1.41 seconds
Started Jul 10 05:38:37 PM PDT 24
Finished Jul 10 05:38:39 PM PDT 24
Peak memory 198744 kb
Host smart-3649dc6f-6c09-4377-9cda-ee97078eb8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626762871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.626762871
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1400537193
Short name T174
Test name
Test status
Simulation time 51731799 ps
CPU time 1.14 seconds
Started Jul 10 05:38:35 PM PDT 24
Finished Jul 10 05:38:37 PM PDT 24
Peak memory 196528 kb
Host smart-074c320c-7b18-483d-97ef-d01195a96adf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400537193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1400537193
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.331356428
Short name T200
Test name
Test status
Simulation time 218630845 ps
CPU time 3.81 seconds
Started Jul 10 05:38:40 PM PDT 24
Finished Jul 10 05:38:45 PM PDT 24
Peak memory 198564 kb
Host smart-6799aa69-9023-42a3-9395-b831fa3146df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331356428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.331356428
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.753126299
Short name T610
Test name
Test status
Simulation time 116758039 ps
CPU time 1.02 seconds
Started Jul 10 05:38:36 PM PDT 24
Finished Jul 10 05:38:38 PM PDT 24
Peak memory 196440 kb
Host smart-2adc0677-4905-46cc-8f1d-bd1798b844ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753126299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.753126299
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.69779797
Short name T694
Test name
Test status
Simulation time 485267317 ps
CPU time 1.2 seconds
Started Jul 10 05:38:36 PM PDT 24
Finished Jul 10 05:38:38 PM PDT 24
Peak memory 196204 kb
Host smart-caf079e7-ad04-4ad6-aa6c-3c7b26ff5672
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69779797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.69779797
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.998299645
Short name T305
Test name
Test status
Simulation time 27308235622 ps
CPU time 182.11 seconds
Started Jul 10 05:38:42 PM PDT 24
Finished Jul 10 05:41:45 PM PDT 24
Peak memory 198804 kb
Host smart-acc2aff2-47f8-4285-bd1c-c7ba9a88ae20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998299645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.998299645
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3442985133
Short name T362
Test name
Test status
Simulation time 20701395 ps
CPU time 0.58 seconds
Started Jul 10 05:38:47 PM PDT 24
Finished Jul 10 05:38:48 PM PDT 24
Peak memory 194636 kb
Host smart-539197fa-9db6-4bbd-a679-2ad0004f114c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442985133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3442985133
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2243453707
Short name T663
Test name
Test status
Simulation time 76983414 ps
CPU time 0.84 seconds
Started Jul 10 05:38:42 PM PDT 24
Finished Jul 10 05:38:44 PM PDT 24
Peak memory 196092 kb
Host smart-aae02190-9792-4100-8af9-869abca82ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243453707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2243453707
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3585498136
Short name T250
Test name
Test status
Simulation time 3683000938 ps
CPU time 20.66 seconds
Started Jul 10 05:38:48 PM PDT 24
Finished Jul 10 05:39:09 PM PDT 24
Peak memory 197712 kb
Host smart-7c5d0cf9-0b0f-4ef8-b87a-3bd7f776f2de
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585498136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3585498136
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.4194556931
Short name T705
Test name
Test status
Simulation time 39871580 ps
CPU time 0.81 seconds
Started Jul 10 05:38:48 PM PDT 24
Finished Jul 10 05:38:49 PM PDT 24
Peak memory 197184 kb
Host smart-6267e576-9e4f-4f4b-9531-987a9e31aeb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194556931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.4194556931
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.4094441943
Short name T74
Test name
Test status
Simulation time 54044288 ps
CPU time 0.71 seconds
Started Jul 10 05:38:44 PM PDT 24
Finished Jul 10 05:38:45 PM PDT 24
Peak memory 194996 kb
Host smart-8ca9c5b3-8e07-41c7-bde6-cede6abfc682
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094441943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.4094441943
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3129577515
Short name T489
Test name
Test status
Simulation time 991812018 ps
CPU time 2.35 seconds
Started Jul 10 05:38:49 PM PDT 24
Finished Jul 10 05:38:52 PM PDT 24
Peak memory 198636 kb
Host smart-80095c1f-182c-4070-9d86-4c67fac51747
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129577515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3129577515
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.819032205
Short name T311
Test name
Test status
Simulation time 313137930 ps
CPU time 2.47 seconds
Started Jul 10 05:38:42 PM PDT 24
Finished Jul 10 05:38:46 PM PDT 24
Peak memory 197908 kb
Host smart-a3251bb6-1023-4b52-a360-13c13d204a6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819032205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
819032205
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3552499167
Short name T292
Test name
Test status
Simulation time 21965238 ps
CPU time 0.97 seconds
Started Jul 10 05:38:42 PM PDT 24
Finished Jul 10 05:38:44 PM PDT 24
Peak memory 197436 kb
Host smart-ca10e94c-056d-414f-92ac-470dc437cbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552499167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3552499167
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3971851548
Short name T594
Test name
Test status
Simulation time 74654029 ps
CPU time 0.91 seconds
Started Jul 10 05:38:44 PM PDT 24
Finished Jul 10 05:38:46 PM PDT 24
Peak memory 197956 kb
Host smart-14c0739b-6f28-4cdc-91fd-e72f18e9b657
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971851548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3971851548
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.828769947
Short name T2
Test name
Test status
Simulation time 658207440 ps
CPU time 2.91 seconds
Started Jul 10 05:38:48 PM PDT 24
Finished Jul 10 05:38:51 PM PDT 24
Peak memory 198628 kb
Host smart-224b7578-4e42-4cd5-85f9-e5d9594f12f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828769947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.828769947
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.199834628
Short name T366
Test name
Test status
Simulation time 33066429 ps
CPU time 0.91 seconds
Started Jul 10 05:38:41 PM PDT 24
Finished Jul 10 05:38:43 PM PDT 24
Peak memory 196732 kb
Host smart-e363786a-23ed-45fa-9c39-9230d1bf9a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199834628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.199834628
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1190102259
Short name T181
Test name
Test status
Simulation time 188175320 ps
CPU time 1.38 seconds
Started Jul 10 05:38:42 PM PDT 24
Finished Jul 10 05:38:45 PM PDT 24
Peak memory 198636 kb
Host smart-d47db21d-901f-490a-b1c8-8fc229672bde
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190102259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1190102259
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2672356970
Short name T265
Test name
Test status
Simulation time 163518497551 ps
CPU time 212.95 seconds
Started Jul 10 05:38:48 PM PDT 24
Finished Jul 10 05:42:22 PM PDT 24
Peak memory 198776 kb
Host smart-2c9a2e4f-7d10-4d48-af58-243322e29009
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672356970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2672356970
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.310623425
Short name T468
Test name
Test status
Simulation time 11159217 ps
CPU time 0.56 seconds
Started Jul 10 05:38:53 PM PDT 24
Finished Jul 10 05:38:54 PM PDT 24
Peak memory 193448 kb
Host smart-546d05fe-8276-48c3-8b4a-b41c4e84f369
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310623425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.310623425
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3650339892
Short name T466
Test name
Test status
Simulation time 13055651 ps
CPU time 0.63 seconds
Started Jul 10 05:38:49 PM PDT 24
Finished Jul 10 05:38:51 PM PDT 24
Peak memory 194680 kb
Host smart-04b42caf-1843-4f02-9124-93029dd3a4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650339892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3650339892
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1454517710
Short name T382
Test name
Test status
Simulation time 617292141 ps
CPU time 17.05 seconds
Started Jul 10 05:38:47 PM PDT 24
Finished Jul 10 05:39:05 PM PDT 24
Peak memory 197636 kb
Host smart-d47886e2-03d8-4b67-b671-41d6ec65b65c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454517710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1454517710
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2058854291
Short name T346
Test name
Test status
Simulation time 31544423 ps
CPU time 0.7 seconds
Started Jul 10 05:38:53 PM PDT 24
Finished Jul 10 05:38:54 PM PDT 24
Peak memory 195200 kb
Host smart-5e442251-f2f7-4af3-a052-6e2ad79005ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058854291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2058854291
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.96526784
Short name T659
Test name
Test status
Simulation time 77240728 ps
CPU time 1.12 seconds
Started Jul 10 05:38:48 PM PDT 24
Finished Jul 10 05:38:50 PM PDT 24
Peak memory 196468 kb
Host smart-1dd4e137-21da-4274-a700-a623c1d4fca4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96526784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.96526784
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2650433378
Short name T23
Test name
Test status
Simulation time 128675454 ps
CPU time 2.81 seconds
Started Jul 10 05:38:47 PM PDT 24
Finished Jul 10 05:38:50 PM PDT 24
Peak memory 198340 kb
Host smart-0acabb09-7672-4b36-8cce-ba30919e07c8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650433378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2650433378
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2274370392
Short name T365
Test name
Test status
Simulation time 96941743 ps
CPU time 2.12 seconds
Started Jul 10 05:38:48 PM PDT 24
Finished Jul 10 05:38:51 PM PDT 24
Peak memory 196772 kb
Host smart-84980b90-afae-4da8-a3f1-7406150ea984
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274370392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2274370392
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2073572037
Short name T528
Test name
Test status
Simulation time 35404710 ps
CPU time 1.24 seconds
Started Jul 10 05:38:48 PM PDT 24
Finished Jul 10 05:38:50 PM PDT 24
Peak memory 197740 kb
Host smart-01187613-d1b7-40d7-84ab-c278b6c48adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073572037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2073572037
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1630794357
Short name T110
Test name
Test status
Simulation time 75091298 ps
CPU time 0.85 seconds
Started Jul 10 05:38:48 PM PDT 24
Finished Jul 10 05:38:50 PM PDT 24
Peak memory 196588 kb
Host smart-6beaa5de-da2f-429c-aa1e-b2ff2622c923
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630794357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1630794357
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3115236211
Short name T421
Test name
Test status
Simulation time 534497094 ps
CPU time 4.43 seconds
Started Jul 10 05:38:46 PM PDT 24
Finished Jul 10 05:38:51 PM PDT 24
Peak memory 197780 kb
Host smart-287bb7ec-e3ee-4feb-925e-dd783d99b9e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115236211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3115236211
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.3255070738
Short name T486
Test name
Test status
Simulation time 147643921 ps
CPU time 1.13 seconds
Started Jul 10 05:38:49 PM PDT 24
Finished Jul 10 05:38:51 PM PDT 24
Peak memory 196940 kb
Host smart-f672c118-de6b-4ec7-b4b6-6e1ce72298a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255070738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3255070738
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1496444976
Short name T228
Test name
Test status
Simulation time 304164924 ps
CPU time 1.53 seconds
Started Jul 10 05:38:49 PM PDT 24
Finished Jul 10 05:38:52 PM PDT 24
Peak memory 198684 kb
Host smart-23f12b5d-7389-4095-93bf-faf7e698e73b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496444976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1496444976
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3697969167
Short name T146
Test name
Test status
Simulation time 29663228075 ps
CPU time 184.22 seconds
Started Jul 10 05:38:54 PM PDT 24
Finished Jul 10 05:41:59 PM PDT 24
Peak memory 198760 kb
Host smart-ee456f29-18a5-459b-880b-9348388719a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697969167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3697969167
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1980056499
Short name T319
Test name
Test status
Simulation time 29462590 ps
CPU time 0.62 seconds
Started Jul 10 05:39:03 PM PDT 24
Finished Jul 10 05:39:04 PM PDT 24
Peak memory 195360 kb
Host smart-6e570b9b-78a9-4133-8a19-32847d09734f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980056499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1980056499
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2222536419
Short name T76
Test name
Test status
Simulation time 64843433 ps
CPU time 0.94 seconds
Started Jul 10 05:38:54 PM PDT 24
Finished Jul 10 05:38:55 PM PDT 24
Peak memory 196544 kb
Host smart-bb510de5-e636-4538-b303-3b0ca07af916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222536419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2222536419
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.353467023
Short name T592
Test name
Test status
Simulation time 2053015925 ps
CPU time 17.49 seconds
Started Jul 10 05:38:54 PM PDT 24
Finished Jul 10 05:39:12 PM PDT 24
Peak memory 196192 kb
Host smart-ed903841-9d01-40c7-bd9d-3fac516dfb25
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353467023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.353467023
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.2289826835
Short name T21
Test name
Test status
Simulation time 422722886 ps
CPU time 1.12 seconds
Started Jul 10 05:38:59 PM PDT 24
Finished Jul 10 05:39:01 PM PDT 24
Peak memory 198368 kb
Host smart-63feced5-3b3a-4ee6-8e80-c396f3982d7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289826835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2289826835
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1682620017
Short name T582
Test name
Test status
Simulation time 534244870 ps
CPU time 1.25 seconds
Started Jul 10 05:38:56 PM PDT 24
Finished Jul 10 05:38:58 PM PDT 24
Peak memory 197468 kb
Host smart-ca886251-07af-47ec-ae63-a9c98d0ad32a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682620017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1682620017
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3797486638
Short name T514
Test name
Test status
Simulation time 50764306 ps
CPU time 2.11 seconds
Started Jul 10 05:38:54 PM PDT 24
Finished Jul 10 05:38:57 PM PDT 24
Peak memory 198800 kb
Host smart-2e005aa7-3396-4911-ae09-7870cfb24836
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797486638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3797486638
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.4186852463
Short name T323
Test name
Test status
Simulation time 251111637 ps
CPU time 1.76 seconds
Started Jul 10 05:38:53 PM PDT 24
Finished Jul 10 05:38:56 PM PDT 24
Peak memory 196452 kb
Host smart-852cd2ed-d52c-4621-90e2-49e7c4c8a726
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186852463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.4186852463
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2019516159
Short name T295
Test name
Test status
Simulation time 124075974 ps
CPU time 1.03 seconds
Started Jul 10 05:38:54 PM PDT 24
Finished Jul 10 05:38:56 PM PDT 24
Peak memory 196712 kb
Host smart-859dcd0a-9de1-4642-bda8-a51e25924b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019516159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2019516159
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.247179610
Short name T529
Test name
Test status
Simulation time 54758245 ps
CPU time 1.28 seconds
Started Jul 10 05:38:56 PM PDT 24
Finished Jul 10 05:38:58 PM PDT 24
Peak memory 197232 kb
Host smart-8d5e27ab-146d-423e-b503-0b02e9f628f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247179610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.247179610
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2967446021
Short name T51
Test name
Test status
Simulation time 233916549 ps
CPU time 2.74 seconds
Started Jul 10 05:39:04 PM PDT 24
Finished Jul 10 05:39:07 PM PDT 24
Peak memory 198632 kb
Host smart-a963ec00-9359-416d-8d89-19cc04afb401
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967446021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2967446021
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1843948186
Short name T471
Test name
Test status
Simulation time 30754693 ps
CPU time 0.85 seconds
Started Jul 10 05:38:53 PM PDT 24
Finished Jul 10 05:38:55 PM PDT 24
Peak memory 195876 kb
Host smart-13d90282-67e1-4964-9163-c1207cefda52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843948186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1843948186
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2295430238
Short name T26
Test name
Test status
Simulation time 346556818 ps
CPU time 0.87 seconds
Started Jul 10 05:38:55 PM PDT 24
Finished Jul 10 05:38:56 PM PDT 24
Peak memory 196712 kb
Host smart-c9c8a3f5-470e-4869-8d9e-7d1807424a0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295430238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2295430238
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2611844496
Short name T618
Test name
Test status
Simulation time 1900113247 ps
CPU time 43.65 seconds
Started Jul 10 05:38:59 PM PDT 24
Finished Jul 10 05:39:44 PM PDT 24
Peak memory 198728 kb
Host smart-47de02f4-3283-4a9f-a892-62970f4218c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611844496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2611844496
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.3590306321
Short name T58
Test name
Test status
Simulation time 223067576791 ps
CPU time 654.45 seconds
Started Jul 10 05:39:01 PM PDT 24
Finished Jul 10 05:49:56 PM PDT 24
Peak memory 198880 kb
Host smart-06f86b3d-9b5b-4695-9164-9f6dd24b2138
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3590306321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.3590306321
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3526757713
Short name T643
Test name
Test status
Simulation time 52406610 ps
CPU time 0.57 seconds
Started Jul 10 05:39:08 PM PDT 24
Finished Jul 10 05:39:09 PM PDT 24
Peak memory 194932 kb
Host smart-c7239815-7567-473f-a144-bd181b676c5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526757713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3526757713
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1109652505
Short name T410
Test name
Test status
Simulation time 153048948 ps
CPU time 0.94 seconds
Started Jul 10 05:39:02 PM PDT 24
Finished Jul 10 05:39:04 PM PDT 24
Peak memory 196664 kb
Host smart-ac91516a-b86c-4d4c-b6af-48ae110af3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109652505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1109652505
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.4056203219
Short name T404
Test name
Test status
Simulation time 7411728998 ps
CPU time 15.81 seconds
Started Jul 10 05:39:02 PM PDT 24
Finished Jul 10 05:39:19 PM PDT 24
Peak memory 198008 kb
Host smart-25ebd1c0-0a58-477a-abae-c6ac61efc66b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056203219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.4056203219
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2686150305
Short name T665
Test name
Test status
Simulation time 22910009 ps
CPU time 0.69 seconds
Started Jul 10 05:39:09 PM PDT 24
Finished Jul 10 05:39:10 PM PDT 24
Peak memory 196000 kb
Host smart-9f46c172-ed12-4e0e-8a9e-0e453a9230ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686150305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2686150305
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.915603970
Short name T218
Test name
Test status
Simulation time 22674013 ps
CPU time 0.81 seconds
Started Jul 10 05:39:00 PM PDT 24
Finished Jul 10 05:39:02 PM PDT 24
Peak memory 195996 kb
Host smart-888713a3-6d46-488c-be6a-0573e1d564f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915603970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.915603970
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.3559344279
Short name T564
Test name
Test status
Simulation time 202533722 ps
CPU time 2.15 seconds
Started Jul 10 05:38:58 PM PDT 24
Finished Jul 10 05:39:02 PM PDT 24
Peak memory 198620 kb
Host smart-f28aed37-f837-457f-927d-2d17644277ad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559344279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.3559344279
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1753406513
Short name T551
Test name
Test status
Simulation time 171481618 ps
CPU time 3.32 seconds
Started Jul 10 05:38:59 PM PDT 24
Finished Jul 10 05:39:04 PM PDT 24
Peak memory 197316 kb
Host smart-6fcce733-3c7f-459b-a108-ad54aa54a7b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753406513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1753406513
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1913016985
Short name T67
Test name
Test status
Simulation time 71028830 ps
CPU time 0.97 seconds
Started Jul 10 05:39:14 PM PDT 24
Finished Jul 10 05:39:17 PM PDT 24
Peak memory 196588 kb
Host smart-92a7175f-6698-4395-9ffc-3d5f4bb585e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913016985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1913016985
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3394371823
Short name T282
Test name
Test status
Simulation time 44149269 ps
CPU time 1.07 seconds
Started Jul 10 05:39:02 PM PDT 24
Finished Jul 10 05:39:04 PM PDT 24
Peak memory 196492 kb
Host smart-c1ba32cf-0994-409b-8a04-404ebeeba0a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394371823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3394371823
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3725631769
Short name T418
Test name
Test status
Simulation time 107378814 ps
CPU time 1.44 seconds
Started Jul 10 05:39:00 PM PDT 24
Finished Jul 10 05:39:03 PM PDT 24
Peak memory 198680 kb
Host smart-8a0eb9dc-2f01-4ff9-813a-39e0514d8e85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725631769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3725631769
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.445498909
Short name T573
Test name
Test status
Simulation time 200324119 ps
CPU time 1.07 seconds
Started Jul 10 05:39:00 PM PDT 24
Finished Jul 10 05:39:03 PM PDT 24
Peak memory 196492 kb
Host smart-51c68e56-137e-4676-94cf-4d98a0818ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445498909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.445498909
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.680212544
Short name T363
Test name
Test status
Simulation time 101764032 ps
CPU time 1.06 seconds
Started Jul 10 05:38:59 PM PDT 24
Finished Jul 10 05:39:01 PM PDT 24
Peak memory 196528 kb
Host smart-92d34d76-08fc-44cd-aaa1-544ba9668dda
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680212544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.680212544
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.417650718
Short name T180
Test name
Test status
Simulation time 10377496624 ps
CPU time 198.67 seconds
Started Jul 10 05:39:07 PM PDT 24
Finished Jul 10 05:42:26 PM PDT 24
Peak memory 198684 kb
Host smart-bae177bb-55a5-48dc-afe9-25ac9121fcea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417650718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.417650718
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.1488407996
Short name T456
Test name
Test status
Simulation time 25260574325 ps
CPU time 571.34 seconds
Started Jul 10 05:39:07 PM PDT 24
Finished Jul 10 05:48:39 PM PDT 24
Peak memory 198900 kb
Host smart-44ce5611-84ba-4ca8-a1c8-1f8f95067b87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1488407996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.1488407996
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.997915466
Short name T320
Test name
Test status
Simulation time 17182168 ps
CPU time 0.57 seconds
Started Jul 10 05:39:13 PM PDT 24
Finished Jul 10 05:39:15 PM PDT 24
Peak memory 194640 kb
Host smart-652777e2-28e0-40a9-9dd8-9cdfac8fbea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997915466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.997915466
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1246414968
Short name T451
Test name
Test status
Simulation time 475412775 ps
CPU time 0.91 seconds
Started Jul 10 05:39:09 PM PDT 24
Finished Jul 10 05:39:11 PM PDT 24
Peak memory 197096 kb
Host smart-1d7f17b2-8838-4f42-b4f7-4e68683335af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246414968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1246414968
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2123095086
Short name T327
Test name
Test status
Simulation time 356275641 ps
CPU time 5.9 seconds
Started Jul 10 05:39:14 PM PDT 24
Finished Jul 10 05:39:21 PM PDT 24
Peak memory 196892 kb
Host smart-967f5fe8-814c-42b0-b66d-621bc02afb7c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123095086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2123095086
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3395050013
Short name T579
Test name
Test status
Simulation time 100320450 ps
CPU time 1.06 seconds
Started Jul 10 05:39:15 PM PDT 24
Finished Jul 10 05:39:17 PM PDT 24
Peak memory 197288 kb
Host smart-e4246fc8-cca3-435e-bb33-068f22ad1f63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395050013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3395050013
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.227270494
Short name T720
Test name
Test status
Simulation time 207066815 ps
CPU time 0.92 seconds
Started Jul 10 05:39:09 PM PDT 24
Finished Jul 10 05:39:10 PM PDT 24
Peak memory 197352 kb
Host smart-9e74bee7-477b-437f-bae5-f508b501d338
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227270494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.227270494
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2683722444
Short name T257
Test name
Test status
Simulation time 91904489 ps
CPU time 2.04 seconds
Started Jul 10 05:39:13 PM PDT 24
Finished Jul 10 05:39:16 PM PDT 24
Peak memory 198892 kb
Host smart-142bddea-41ed-4326-9ba7-5f9cb117ed4a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683722444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2683722444
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3179969997
Short name T199
Test name
Test status
Simulation time 278336612 ps
CPU time 1.79 seconds
Started Jul 10 05:39:07 PM PDT 24
Finished Jul 10 05:39:09 PM PDT 24
Peak memory 197312 kb
Host smart-5774ee16-a3a0-47de-b6e7-89de73357d89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179969997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3179969997
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3314254715
Short name T18
Test name
Test status
Simulation time 49327558 ps
CPU time 1.05 seconds
Started Jul 10 05:39:08 PM PDT 24
Finished Jul 10 05:39:10 PM PDT 24
Peak memory 196632 kb
Host smart-6ff42903-086c-4dab-8371-9fe299c54425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314254715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3314254715
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3285454959
Short name T248
Test name
Test status
Simulation time 87744692 ps
CPU time 0.84 seconds
Started Jul 10 05:39:09 PM PDT 24
Finished Jul 10 05:39:11 PM PDT 24
Peak memory 196176 kb
Host smart-cbf069f2-7526-4475-a288-d2c781083307
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285454959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3285454959
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3290060127
Short name T335
Test name
Test status
Simulation time 90142755 ps
CPU time 1.51 seconds
Started Jul 10 05:39:16 PM PDT 24
Finished Jul 10 05:39:18 PM PDT 24
Peak memory 198664 kb
Host smart-7e432ee5-d052-4431-a32f-cacf5c7c6ff2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290060127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3290060127
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1459656639
Short name T269
Test name
Test status
Simulation time 39688149 ps
CPU time 0.75 seconds
Started Jul 10 05:39:06 PM PDT 24
Finished Jul 10 05:39:07 PM PDT 24
Peak memory 195856 kb
Host smart-3e3efc6f-9f6f-469f-994c-6e38ab92a661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459656639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1459656639
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3800089737
Short name T165
Test name
Test status
Simulation time 36550436 ps
CPU time 1.22 seconds
Started Jul 10 05:39:05 PM PDT 24
Finished Jul 10 05:39:07 PM PDT 24
Peak memory 196356 kb
Host smart-6d802108-1383-4e00-bea4-d6850e2b6385
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800089737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3800089737
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2024987705
Short name T211
Test name
Test status
Simulation time 18917200034 ps
CPU time 195.67 seconds
Started Jul 10 05:39:14 PM PDT 24
Finished Jul 10 05:42:30 PM PDT 24
Peak memory 198776 kb
Host smart-ef289c92-b312-4583-99ff-6af63530f1ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024987705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2024987705
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.366332806
Short name T470
Test name
Test status
Simulation time 218762177383 ps
CPU time 675.62 seconds
Started Jul 10 05:39:15 PM PDT 24
Finished Jul 10 05:50:32 PM PDT 24
Peak memory 198928 kb
Host smart-e5b6d574-04e8-4e77-bc06-1e44de8c50e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=366332806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.366332806
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.452783998
Short name T114
Test name
Test status
Simulation time 30353553 ps
CPU time 0.56 seconds
Started Jul 10 05:39:21 PM PDT 24
Finished Jul 10 05:39:23 PM PDT 24
Peak memory 194640 kb
Host smart-04469c23-8206-489e-907f-1903c11b867f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452783998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.452783998
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.581293286
Short name T241
Test name
Test status
Simulation time 52807541 ps
CPU time 0.71 seconds
Started Jul 10 05:39:13 PM PDT 24
Finished Jul 10 05:39:15 PM PDT 24
Peak memory 195936 kb
Host smart-a12cec34-ccc2-4c46-a4fc-f74f8dd9756b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581293286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.581293286
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.1763215363
Short name T698
Test name
Test status
Simulation time 558176306 ps
CPU time 7.13 seconds
Started Jul 10 05:39:22 PM PDT 24
Finished Jul 10 05:39:30 PM PDT 24
Peak memory 196148 kb
Host smart-550d4f46-f7aa-4aeb-bb4b-6dfa926b42dd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763215363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.1763215363
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.179631653
Short name T680
Test name
Test status
Simulation time 125520784 ps
CPU time 0.67 seconds
Started Jul 10 05:39:19 PM PDT 24
Finished Jul 10 05:39:21 PM PDT 24
Peak memory 195136 kb
Host smart-164e7d92-af93-4288-bd35-d6afeb98e950
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179631653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.179631653
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2401893429
Short name T646
Test name
Test status
Simulation time 244119723 ps
CPU time 1.14 seconds
Started Jul 10 05:39:21 PM PDT 24
Finished Jul 10 05:39:23 PM PDT 24
Peak memory 197124 kb
Host smart-eb003a9a-fdf7-40e6-be2e-b65077c52988
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401893429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2401893429
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.4122144998
Short name T321
Test name
Test status
Simulation time 224933001 ps
CPU time 0.98 seconds
Started Jul 10 05:39:20 PM PDT 24
Finished Jul 10 05:39:23 PM PDT 24
Peak memory 196892 kb
Host smart-3c2f26c3-1c80-49b3-9939-7e0e4539386e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122144998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.4122144998
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1553912066
Short name T656
Test name
Test status
Simulation time 235068589 ps
CPU time 2.6 seconds
Started Jul 10 05:39:21 PM PDT 24
Finished Jul 10 05:39:25 PM PDT 24
Peak memory 196432 kb
Host smart-2899af05-3579-48f7-b5bf-56e273251a91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553912066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1553912066
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3214395968
Short name T450
Test name
Test status
Simulation time 23969409 ps
CPU time 0.78 seconds
Started Jul 10 05:39:14 PM PDT 24
Finished Jul 10 05:39:16 PM PDT 24
Peak memory 196180 kb
Host smart-80f26e70-3c22-49f4-bf36-96e00b909f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214395968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3214395968
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2659667509
Short name T279
Test name
Test status
Simulation time 175769713 ps
CPU time 1.24 seconds
Started Jul 10 05:39:15 PM PDT 24
Finished Jul 10 05:39:17 PM PDT 24
Peak memory 198640 kb
Host smart-fcd9a466-e091-4044-9dec-39ff3a125d22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659667509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2659667509
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.856239285
Short name T545
Test name
Test status
Simulation time 395186947 ps
CPU time 1.68 seconds
Started Jul 10 05:39:21 PM PDT 24
Finished Jul 10 05:39:24 PM PDT 24
Peak memory 198544 kb
Host smart-c7bf3f0c-c7ce-4e65-9241-0e80773cb61a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856239285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.856239285
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3306662675
Short name T715
Test name
Test status
Simulation time 194089973 ps
CPU time 0.95 seconds
Started Jul 10 05:39:14 PM PDT 24
Finished Jul 10 05:39:16 PM PDT 24
Peak memory 196372 kb
Host smart-a302a2af-0364-4506-911d-7d5a02766788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306662675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3306662675
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3159910025
Short name T239
Test name
Test status
Simulation time 41778522 ps
CPU time 1.03 seconds
Started Jul 10 05:39:15 PM PDT 24
Finished Jul 10 05:39:17 PM PDT 24
Peak memory 196396 kb
Host smart-ae812c2b-236f-4b36-b1fe-d515ae54cf61
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159910025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3159910025
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1766000236
Short name T201
Test name
Test status
Simulation time 5191480329 ps
CPU time 146.75 seconds
Started Jul 10 05:39:21 PM PDT 24
Finished Jul 10 05:41:49 PM PDT 24
Peak memory 198752 kb
Host smart-71c1e939-3abd-4acd-854c-272aa331d939
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766000236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1766000236
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.2582211075
Short name T31
Test name
Test status
Simulation time 114444557503 ps
CPU time 1469.63 seconds
Started Jul 10 05:39:20 PM PDT 24
Finished Jul 10 06:03:51 PM PDT 24
Peak memory 198892 kb
Host smart-132f6105-a186-4e05-b342-80a3aaaa9443
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2582211075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.2582211075
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.447782677
Short name T685
Test name
Test status
Simulation time 21944604 ps
CPU time 0.59 seconds
Started Jul 10 05:39:22 PM PDT 24
Finished Jul 10 05:39:24 PM PDT 24
Peak memory 195284 kb
Host smart-5be63a34-56a9-4de5-9b63-cff6b8d01443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447782677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.447782677
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3197281577
Short name T522
Test name
Test status
Simulation time 49869636 ps
CPU time 0.94 seconds
Started Jul 10 05:39:22 PM PDT 24
Finished Jul 10 05:39:24 PM PDT 24
Peak memory 196516 kb
Host smart-2e63ae7e-f952-40a1-8c81-2a834d595886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197281577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3197281577
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3728540256
Short name T322
Test name
Test status
Simulation time 603826248 ps
CPU time 17.46 seconds
Started Jul 10 05:39:24 PM PDT 24
Finished Jul 10 05:39:43 PM PDT 24
Peak memory 197416 kb
Host smart-926cc35d-395c-4ccd-8591-78b61aad9308
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728540256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3728540256
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1887645718
Short name T221
Test name
Test status
Simulation time 41163372 ps
CPU time 0.85 seconds
Started Jul 10 05:39:21 PM PDT 24
Finished Jul 10 05:39:24 PM PDT 24
Peak memory 196576 kb
Host smart-3db208b8-06f1-494d-acb4-977009110255
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887645718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1887645718
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.41457786
Short name T625
Test name
Test status
Simulation time 40654407 ps
CPU time 1.15 seconds
Started Jul 10 05:39:19 PM PDT 24
Finished Jul 10 05:39:21 PM PDT 24
Peak memory 196760 kb
Host smart-47a03e36-9784-4e8a-8256-001041c16894
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41457786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.41457786
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1784424641
Short name T465
Test name
Test status
Simulation time 127553192 ps
CPU time 2.86 seconds
Started Jul 10 05:39:21 PM PDT 24
Finished Jul 10 05:39:25 PM PDT 24
Peak memory 198584 kb
Host smart-3a644c2f-044a-4d0c-916a-15fa94d7ec8c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784424641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1784424641
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.286862976
Short name T175
Test name
Test status
Simulation time 453542433 ps
CPU time 3.49 seconds
Started Jul 10 05:39:24 PM PDT 24
Finished Jul 10 05:39:28 PM PDT 24
Peak memory 198744 kb
Host smart-c6c844aa-2ca3-40d4-9139-66bd8e06e725
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286862976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
286862976
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2460002758
Short name T566
Test name
Test status
Simulation time 74593339 ps
CPU time 1.08 seconds
Started Jul 10 05:39:19 PM PDT 24
Finished Jul 10 05:39:21 PM PDT 24
Peak memory 197216 kb
Host smart-b0f5f268-eff1-4cef-9ab3-52f3097516fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460002758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2460002758
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.4148761127
Short name T259
Test name
Test status
Simulation time 75381912 ps
CPU time 0.93 seconds
Started Jul 10 05:39:21 PM PDT 24
Finished Jul 10 05:39:24 PM PDT 24
Peak memory 197292 kb
Host smart-a01f5778-e831-4e40-b0e3-73cff57a8918
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148761127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.4148761127
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1026725845
Short name T621
Test name
Test status
Simulation time 213259937 ps
CPU time 1.82 seconds
Started Jul 10 05:39:26 PM PDT 24
Finished Jul 10 05:39:28 PM PDT 24
Peak memory 198636 kb
Host smart-787cae67-6ac2-4ceb-bbd2-6eb3ebcecbb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026725845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1026725845
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1778905704
Short name T233
Test name
Test status
Simulation time 107590509 ps
CPU time 1.17 seconds
Started Jul 10 05:39:20 PM PDT 24
Finished Jul 10 05:39:23 PM PDT 24
Peak memory 196956 kb
Host smart-7cf3fd11-21ad-489a-af8c-364b293b3784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778905704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1778905704
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1015398411
Short name T626
Test name
Test status
Simulation time 80518576 ps
CPU time 1.63 seconds
Started Jul 10 05:39:24 PM PDT 24
Finished Jul 10 05:39:27 PM PDT 24
Peak memory 197548 kb
Host smart-158d3ae2-7d25-4d8f-882a-4ad281b2df64
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015398411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1015398411
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2523434932
Short name T132
Test name
Test status
Simulation time 27189451477 ps
CPU time 178.1 seconds
Started Jul 10 05:39:24 PM PDT 24
Finished Jul 10 05:42:24 PM PDT 24
Peak memory 198780 kb
Host smart-e4fed892-0f5a-4dde-a8a3-b16a82a80c65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523434932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2523434932
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.2132187134
Short name T6
Test name
Test status
Simulation time 56940736895 ps
CPU time 155.04 seconds
Started Jul 10 05:39:21 PM PDT 24
Finished Jul 10 05:41:58 PM PDT 24
Peak memory 198924 kb
Host smart-a6d037cd-4a8f-41cd-8965-4bf0b40e8853
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2132187134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.2132187134
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.268614110
Short name T609
Test name
Test status
Simulation time 24511896 ps
CPU time 0.56 seconds
Started Jul 10 05:39:26 PM PDT 24
Finished Jul 10 05:39:28 PM PDT 24
Peak memory 194656 kb
Host smart-a2dd2d68-c20f-4a65-83d4-3fb2b8827328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268614110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.268614110
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2260504351
Short name T669
Test name
Test status
Simulation time 18600906 ps
CPU time 0.64 seconds
Started Jul 10 05:39:21 PM PDT 24
Finished Jul 10 05:39:22 PM PDT 24
Peak memory 194600 kb
Host smart-d6582668-6884-4985-aa41-a51e34868848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260504351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2260504351
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.140679791
Short name T416
Test name
Test status
Simulation time 817964839 ps
CPU time 11.17 seconds
Started Jul 10 05:39:27 PM PDT 24
Finished Jul 10 05:39:39 PM PDT 24
Peak memory 197376 kb
Host smart-5dec38fb-f56b-4b64-ad57-1c9b98a297e0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140679791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.140679791
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.494830126
Short name T145
Test name
Test status
Simulation time 119074323 ps
CPU time 0.92 seconds
Started Jul 10 05:39:27 PM PDT 24
Finished Jul 10 05:39:29 PM PDT 24
Peak memory 197808 kb
Host smart-8e88cfd9-f146-400d-918c-eee7765c8d91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494830126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.494830126
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1747961985
Short name T24
Test name
Test status
Simulation time 594111221 ps
CPU time 1.36 seconds
Started Jul 10 05:39:28 PM PDT 24
Finished Jul 10 05:39:31 PM PDT 24
Peak memory 196500 kb
Host smart-1732a2b7-ace3-483c-b6f9-6b6a68a58b43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747961985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1747961985
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2831191962
Short name T542
Test name
Test status
Simulation time 46132466 ps
CPU time 2.09 seconds
Started Jul 10 05:39:28 PM PDT 24
Finished Jul 10 05:39:31 PM PDT 24
Peak memory 198660 kb
Host smart-7b16bead-ce72-47c8-8ab8-b4a2f6f3da4a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831191962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2831191962
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.4120470512
Short name T517
Test name
Test status
Simulation time 156035006 ps
CPU time 3.09 seconds
Started Jul 10 05:39:27 PM PDT 24
Finished Jul 10 05:39:32 PM PDT 24
Peak memory 197852 kb
Host smart-55724fdb-7fac-4c32-bb44-910dba6677b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120470512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.4120470512
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1180160236
Short name T122
Test name
Test status
Simulation time 77753983 ps
CPU time 0.97 seconds
Started Jul 10 05:39:25 PM PDT 24
Finished Jul 10 05:39:27 PM PDT 24
Peak memory 196744 kb
Host smart-949a3d76-365d-4856-aec3-e5f1ffff10a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180160236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1180160236
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.4177914191
Short name T225
Test name
Test status
Simulation time 156270125 ps
CPU time 1.11 seconds
Started Jul 10 05:39:21 PM PDT 24
Finished Jul 10 05:39:24 PM PDT 24
Peak memory 197420 kb
Host smart-2f94ecde-263e-49de-9d1d-6baa748becbd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177914191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.4177914191
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2398827454
Short name T614
Test name
Test status
Simulation time 257162699 ps
CPU time 1.98 seconds
Started Jul 10 05:39:27 PM PDT 24
Finished Jul 10 05:39:30 PM PDT 24
Peak memory 198636 kb
Host smart-211a3b44-155f-4d4f-9318-5e7c422adc4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398827454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2398827454
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.479100142
Short name T704
Test name
Test status
Simulation time 63292803 ps
CPU time 1.2 seconds
Started Jul 10 05:39:22 PM PDT 24
Finished Jul 10 05:39:25 PM PDT 24
Peak memory 196336 kb
Host smart-2c386374-039e-43bd-b229-75eb13a66265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479100142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.479100142
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3445903302
Short name T402
Test name
Test status
Simulation time 60114442 ps
CPU time 1.06 seconds
Started Jul 10 05:39:22 PM PDT 24
Finished Jul 10 05:39:25 PM PDT 24
Peak memory 196220 kb
Host smart-27bad3fd-6b3a-45b5-a30a-d9045fdfa151
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445903302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3445903302
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.4205260618
Short name T620
Test name
Test status
Simulation time 4673142461 ps
CPU time 48.93 seconds
Started Jul 10 05:39:27 PM PDT 24
Finished Jul 10 05:40:17 PM PDT 24
Peak memory 198828 kb
Host smart-7a039481-b97d-4d32-a226-4578faf65a01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205260618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.4205260618
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.890363445
Short name T433
Test name
Test status
Simulation time 16010932 ps
CPU time 0.58 seconds
Started Jul 10 05:34:38 PM PDT 24
Finished Jul 10 05:34:40 PM PDT 24
Peak memory 194824 kb
Host smart-343acc3b-71db-4aa8-8b09-2cb4e2b84f5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890363445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.890363445
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3693380740
Short name T543
Test name
Test status
Simulation time 37771223 ps
CPU time 0.65 seconds
Started Jul 10 05:34:28 PM PDT 24
Finished Jul 10 05:34:30 PM PDT 24
Peak memory 194720 kb
Host smart-e82a764b-6196-42e9-bc0a-ad831e5a7c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693380740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3693380740
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.161245823
Short name T130
Test name
Test status
Simulation time 591523990 ps
CPU time 16.32 seconds
Started Jul 10 05:34:28 PM PDT 24
Finished Jul 10 05:34:46 PM PDT 24
Peak memory 198608 kb
Host smart-00b750f8-ee4a-46d8-b625-b85a381717c6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161245823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.161245823
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.811088856
Short name T299
Test name
Test status
Simulation time 347948121 ps
CPU time 1.02 seconds
Started Jul 10 05:34:34 PM PDT 24
Finished Jul 10 05:34:36 PM PDT 24
Peak memory 197076 kb
Host smart-6cbd2474-af0e-4a03-9237-8ac32daa1a44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811088856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.811088856
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.861438785
Short name T595
Test name
Test status
Simulation time 29030496 ps
CPU time 1.03 seconds
Started Jul 10 05:34:28 PM PDT 24
Finished Jul 10 05:34:31 PM PDT 24
Peak memory 196852 kb
Host smart-1f114e21-e56f-430e-981f-653a5b8679c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861438785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.861438785
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3053867713
Short name T617
Test name
Test status
Simulation time 174332184 ps
CPU time 1.93 seconds
Started Jul 10 05:34:28 PM PDT 24
Finished Jul 10 05:34:31 PM PDT 24
Peak memory 198576 kb
Host smart-e898c0ee-89ad-4ffe-8101-ea20eaa79be6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053867713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3053867713
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1314027099
Short name T188
Test name
Test status
Simulation time 106079044 ps
CPU time 3.52 seconds
Started Jul 10 05:34:33 PM PDT 24
Finished Jul 10 05:34:37 PM PDT 24
Peak memory 197824 kb
Host smart-4af0dd0e-6806-47e6-b2a3-6815afee173d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314027099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1314027099
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3729607189
Short name T226
Test name
Test status
Simulation time 63076634 ps
CPU time 1.27 seconds
Started Jul 10 05:34:28 PM PDT 24
Finished Jul 10 05:34:31 PM PDT 24
Peak memory 196468 kb
Host smart-c9dd495d-0c70-4ffe-908a-2b58d65e677b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729607189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3729607189
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1396759311
Short name T345
Test name
Test status
Simulation time 204472244 ps
CPU time 1.37 seconds
Started Jul 10 05:34:28 PM PDT 24
Finished Jul 10 05:34:31 PM PDT 24
Peak memory 197152 kb
Host smart-85cc302e-4794-46de-9131-f3b59eb9b47a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396759311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1396759311
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3771461324
Short name T121
Test name
Test status
Simulation time 906703392 ps
CPU time 5.49 seconds
Started Jul 10 05:34:36 PM PDT 24
Finished Jul 10 05:34:42 PM PDT 24
Peak memory 198528 kb
Host smart-6815802a-d561-4906-8756-54b25cc45a4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771461324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3771461324
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3380011021
Short name T628
Test name
Test status
Simulation time 137225395 ps
CPU time 1.35 seconds
Started Jul 10 05:34:28 PM PDT 24
Finished Jul 10 05:34:31 PM PDT 24
Peak memory 198644 kb
Host smart-9e0a2bec-b1ac-4223-b4fd-04aaa314e3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380011021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3380011021
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2658496432
Short name T235
Test name
Test status
Simulation time 399512707 ps
CPU time 1.5 seconds
Started Jul 10 05:34:36 PM PDT 24
Finished Jul 10 05:34:39 PM PDT 24
Peak memory 198648 kb
Host smart-71b975dd-18b9-4424-8380-26883dac68cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658496432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2658496432
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.845589220
Short name T687
Test name
Test status
Simulation time 5508749202 ps
CPU time 77.51 seconds
Started Jul 10 05:34:40 PM PDT 24
Finished Jul 10 05:35:58 PM PDT 24
Peak memory 198724 kb
Host smart-ed5ab189-9ee1-4935-82d1-e967a49fc505
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845589220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gp
io_stress_all.845589220
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.757236826
Short name T420
Test name
Test status
Simulation time 12568061 ps
CPU time 0.57 seconds
Started Jul 10 05:34:54 PM PDT 24
Finished Jul 10 05:34:56 PM PDT 24
Peak memory 194824 kb
Host smart-aa479faf-8eaa-4951-9da2-04c3426516d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757236826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.757236826
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2310486825
Short name T376
Test name
Test status
Simulation time 57069091 ps
CPU time 0.77 seconds
Started Jul 10 05:34:40 PM PDT 24
Finished Jul 10 05:34:42 PM PDT 24
Peak memory 195924 kb
Host smart-f8e9ab3f-9973-474a-b7aa-19b1302dd23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310486825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2310486825
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.4226378253
Short name T605
Test name
Test status
Simulation time 3669429863 ps
CPU time 18.41 seconds
Started Jul 10 05:34:44 PM PDT 24
Finished Jul 10 05:35:03 PM PDT 24
Peak memory 197412 kb
Host smart-73d21c31-5772-46c4-b1e4-52b136177e1b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226378253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.4226378253
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1899096759
Short name T703
Test name
Test status
Simulation time 126530707 ps
CPU time 1.09 seconds
Started Jul 10 05:34:39 PM PDT 24
Finished Jul 10 05:34:41 PM PDT 24
Peak memory 198516 kb
Host smart-113a63bf-0ced-4879-85ec-48cff7675f0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899096759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1899096759
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.29832020
Short name T458
Test name
Test status
Simulation time 59899762 ps
CPU time 1.05 seconds
Started Jul 10 05:34:43 PM PDT 24
Finished Jul 10 05:34:45 PM PDT 24
Peak memory 196712 kb
Host smart-37bf6feb-3d50-4a2e-aaa6-6835d3a42a5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29832020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.29832020
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2653372926
Short name T231
Test name
Test status
Simulation time 112337395 ps
CPU time 2.48 seconds
Started Jul 10 05:34:40 PM PDT 24
Finished Jul 10 05:34:43 PM PDT 24
Peak memory 197108 kb
Host smart-1d17a562-99f1-4397-afb7-b30e9bf63ca5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653372926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2653372926
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.429958164
Short name T699
Test name
Test status
Simulation time 426031623 ps
CPU time 2.09 seconds
Started Jul 10 05:34:40 PM PDT 24
Finished Jul 10 05:34:43 PM PDT 24
Peak memory 196580 kb
Host smart-8a116f7e-e1ee-4fa1-a844-f880be769dc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429958164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.429958164
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3920001257
Short name T577
Test name
Test status
Simulation time 183196361 ps
CPU time 1.21 seconds
Started Jul 10 05:34:46 PM PDT 24
Finished Jul 10 05:34:48 PM PDT 24
Peak memory 196496 kb
Host smart-3a87877e-e960-4e61-8e3e-1cccf195a28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920001257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3920001257
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2250654148
Short name T351
Test name
Test status
Simulation time 32903259 ps
CPU time 1.23 seconds
Started Jul 10 05:34:40 PM PDT 24
Finished Jul 10 05:34:42 PM PDT 24
Peak memory 197688 kb
Host smart-3baadb87-d97a-4e56-a03a-fbee860781f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250654148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2250654148
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3132135520
Short name T408
Test name
Test status
Simulation time 1028717372 ps
CPU time 3.77 seconds
Started Jul 10 05:34:45 PM PDT 24
Finished Jul 10 05:34:49 PM PDT 24
Peak memory 198628 kb
Host smart-c16846e7-62d0-456a-98b0-26c36e92370e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132135520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3132135520
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.224527867
Short name T71
Test name
Test status
Simulation time 58707325 ps
CPU time 1.07 seconds
Started Jul 10 05:34:41 PM PDT 24
Finished Jul 10 05:34:43 PM PDT 24
Peak memory 196440 kb
Host smart-fbc8d3d3-878f-41b4-9aad-3a0d6bc444b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224527867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.224527867
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2145631786
Short name T570
Test name
Test status
Simulation time 166575237 ps
CPU time 1.16 seconds
Started Jul 10 05:34:36 PM PDT 24
Finished Jul 10 05:34:38 PM PDT 24
Peak memory 197076 kb
Host smart-a5f13de8-aee4-4050-9b9a-baf4794f84b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145631786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2145631786
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.436653234
Short name T501
Test name
Test status
Simulation time 2716222147 ps
CPU time 41.91 seconds
Started Jul 10 05:34:44 PM PDT 24
Finished Jul 10 05:35:27 PM PDT 24
Peak memory 198768 kb
Host smart-dc1ada65-9e7e-40e3-9b0e-ef3091c0ea4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436653234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.436653234
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.4028212696
Short name T483
Test name
Test status
Simulation time 13315201 ps
CPU time 0.57 seconds
Started Jul 10 05:34:54 PM PDT 24
Finished Jul 10 05:34:56 PM PDT 24
Peak memory 195568 kb
Host smart-9988e63e-af29-45cc-bb28-6b98f026196a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028212696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.4028212696
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.457162064
Short name T576
Test name
Test status
Simulation time 99033320 ps
CPU time 0.72 seconds
Started Jul 10 05:34:54 PM PDT 24
Finished Jul 10 05:34:56 PM PDT 24
Peak memory 195820 kb
Host smart-c8939d06-d2d3-49df-a16b-5a54b070ae62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457162064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.457162064
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2569904132
Short name T111
Test name
Test status
Simulation time 6562492118 ps
CPU time 18.82 seconds
Started Jul 10 05:34:53 PM PDT 24
Finished Jul 10 05:35:13 PM PDT 24
Peak memory 197244 kb
Host smart-6a414641-dccf-42e5-ab22-4d62c12f36ed
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569904132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2569904132
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.2544364849
Short name T274
Test name
Test status
Simulation time 62455063 ps
CPU time 0.94 seconds
Started Jul 10 05:34:53 PM PDT 24
Finished Jul 10 05:34:55 PM PDT 24
Peak memory 196664 kb
Host smart-b3c19566-b090-4dfa-84ec-d52e15be5ec4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544364849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.2544364849
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2969861437
Short name T290
Test name
Test status
Simulation time 377390881 ps
CPU time 1.19 seconds
Started Jul 10 05:34:54 PM PDT 24
Finished Jul 10 05:34:56 PM PDT 24
Peak memory 197500 kb
Host smart-75261c77-f7be-4e8f-afb3-6f729f742b70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969861437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2969861437
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3231547784
Short name T701
Test name
Test status
Simulation time 35412013 ps
CPU time 1.01 seconds
Started Jul 10 05:34:54 PM PDT 24
Finished Jul 10 05:34:57 PM PDT 24
Peak memory 197456 kb
Host smart-2eb3c743-4432-458e-87a5-c60b9b871488
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231547784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3231547784
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3183546358
Short name T406
Test name
Test status
Simulation time 167350513 ps
CPU time 3.4 seconds
Started Jul 10 05:34:55 PM PDT 24
Finished Jul 10 05:34:59 PM PDT 24
Peak memory 197796 kb
Host smart-89f54739-e5e1-4a26-8f7f-bf4a2d2a042c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183546358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3183546358
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1363201596
Short name T117
Test name
Test status
Simulation time 71163580 ps
CPU time 1.4 seconds
Started Jul 10 05:34:47 PM PDT 24
Finished Jul 10 05:34:49 PM PDT 24
Peak memory 197644 kb
Host smart-590c7214-1b07-42b4-a1c7-0e2dc9a161b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363201596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1363201596
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.1574545187
Short name T184
Test name
Test status
Simulation time 85248065 ps
CPU time 0.78 seconds
Started Jul 10 05:34:53 PM PDT 24
Finished Jul 10 05:34:56 PM PDT 24
Peak memory 196688 kb
Host smart-854b22c6-b60e-42e0-843a-abf1033eff34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574545187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.1574545187
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.560605014
Short name T639
Test name
Test status
Simulation time 257040936 ps
CPU time 3.47 seconds
Started Jul 10 05:34:53 PM PDT 24
Finished Jul 10 05:34:57 PM PDT 24
Peak memory 198612 kb
Host smart-009d8a6f-dcbd-47d4-858c-28ddb62141ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560605014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.560605014
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.321294931
Short name T604
Test name
Test status
Simulation time 34540917 ps
CPU time 0.93 seconds
Started Jul 10 05:34:47 PM PDT 24
Finished Jul 10 05:34:49 PM PDT 24
Peak memory 195984 kb
Host smart-45124157-117f-4ed6-8ebb-9eea959d9576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321294931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.321294931
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1007045462
Short name T467
Test name
Test status
Simulation time 49589303 ps
CPU time 1.42 seconds
Started Jul 10 05:34:47 PM PDT 24
Finished Jul 10 05:34:49 PM PDT 24
Peak memory 197400 kb
Host smart-6e7480e3-2a86-4f5f-8a58-f1143812b5c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007045462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1007045462
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3519292194
Short name T300
Test name
Test status
Simulation time 23298767112 ps
CPU time 196.01 seconds
Started Jul 10 05:34:52 PM PDT 24
Finished Jul 10 05:38:10 PM PDT 24
Peak memory 198772 kb
Host smart-2d76ffc8-6ebc-4288-8d00-a60d83882985
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519292194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3519292194
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.634346691
Short name T657
Test name
Test status
Simulation time 113445820934 ps
CPU time 2364.84 seconds
Started Jul 10 05:34:53 PM PDT 24
Finished Jul 10 06:14:19 PM PDT 24
Peak memory 198844 kb
Host smart-7accae65-a9f1-4fef-a134-05ea13658824
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=634346691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.634346691
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.4004020792
Short name T586
Test name
Test status
Simulation time 16489952 ps
CPU time 0.61 seconds
Started Jul 10 05:35:00 PM PDT 24
Finished Jul 10 05:35:01 PM PDT 24
Peak memory 194876 kb
Host smart-2e69740c-4100-4233-b9a5-b00c4592cc44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004020792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.4004020792
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3918077562
Short name T584
Test name
Test status
Simulation time 65568189 ps
CPU time 0.72 seconds
Started Jul 10 05:34:54 PM PDT 24
Finished Jul 10 05:34:56 PM PDT 24
Peak memory 194872 kb
Host smart-63d8cb48-a2bc-49b5-8f43-c661c28e1afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918077562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3918077562
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2782857880
Short name T29
Test name
Test status
Simulation time 1538582309 ps
CPU time 21.58 seconds
Started Jul 10 05:35:01 PM PDT 24
Finished Jul 10 05:35:24 PM PDT 24
Peak memory 197240 kb
Host smart-f86db4df-c519-4d48-a201-ade5d44445db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782857880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2782857880
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1787063580
Short name T401
Test name
Test status
Simulation time 44591515 ps
CPU time 0.75 seconds
Started Jul 10 05:35:01 PM PDT 24
Finished Jul 10 05:35:03 PM PDT 24
Peak memory 197056 kb
Host smart-0d8121ce-d493-48f6-b39b-a41a810fd538
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787063580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1787063580
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.685939217
Short name T249
Test name
Test status
Simulation time 64570012 ps
CPU time 1 seconds
Started Jul 10 05:34:53 PM PDT 24
Finished Jul 10 05:34:55 PM PDT 24
Peak memory 197404 kb
Host smart-6c4f5a45-b136-4a33-865c-69ffe23d1fef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685939217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.685939217
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1890060428
Short name T531
Test name
Test status
Simulation time 241612999 ps
CPU time 2.66 seconds
Started Jul 10 05:35:00 PM PDT 24
Finished Jul 10 05:35:04 PM PDT 24
Peak memory 198728 kb
Host smart-5bbccd09-c9ce-441f-954c-40228f3a16cc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890060428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1890060428
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2034606757
Short name T479
Test name
Test status
Simulation time 69170276 ps
CPU time 2.14 seconds
Started Jul 10 05:35:02 PM PDT 24
Finished Jul 10 05:35:05 PM PDT 24
Peak memory 198824 kb
Host smart-8cdee14f-7a48-46d9-8cf6-f932e1235195
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034606757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2034606757
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3550039955
Short name T280
Test name
Test status
Simulation time 99994802 ps
CPU time 1.16 seconds
Started Jul 10 05:34:52 PM PDT 24
Finished Jul 10 05:34:55 PM PDT 24
Peak memory 196732 kb
Host smart-d9801916-5385-4de9-afa0-7b3b9c88391c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550039955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3550039955
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2662950041
Short name T288
Test name
Test status
Simulation time 30273011 ps
CPU time 0.81 seconds
Started Jul 10 05:34:52 PM PDT 24
Finished Jul 10 05:34:53 PM PDT 24
Peak memory 196036 kb
Host smart-5d9ffd69-fb36-4416-bdf5-d761907cb893
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662950041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2662950041
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.849083695
Short name T123
Test name
Test status
Simulation time 157794717 ps
CPU time 2.29 seconds
Started Jul 10 05:35:00 PM PDT 24
Finished Jul 10 05:35:03 PM PDT 24
Peak memory 198604 kb
Host smart-7376dfc5-4fb3-458c-8f8e-e187b6ea2642
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849083695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.849083695
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2279088222
Short name T272
Test name
Test status
Simulation time 148336122 ps
CPU time 1.03 seconds
Started Jul 10 05:34:56 PM PDT 24
Finished Jul 10 05:34:58 PM PDT 24
Peak memory 196648 kb
Host smart-a09c24f5-584e-423f-a088-7e4634f5eaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279088222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2279088222
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3663554654
Short name T686
Test name
Test status
Simulation time 49868552 ps
CPU time 0.98 seconds
Started Jul 10 05:34:56 PM PDT 24
Finished Jul 10 05:34:58 PM PDT 24
Peak memory 196056 kb
Host smart-633770f8-52a0-4b86-a216-99fe33308671
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663554654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3663554654
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1500427967
Short name T217
Test name
Test status
Simulation time 34050557826 ps
CPU time 32.04 seconds
Started Jul 10 05:35:01 PM PDT 24
Finished Jul 10 05:35:34 PM PDT 24
Peak memory 198720 kb
Host smart-8b13c481-1a14-44dc-acb6-d96f7ec933a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500427967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1500427967
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.4178899771
Short name T683
Test name
Test status
Simulation time 34753772 ps
CPU time 0.58 seconds
Started Jul 10 05:35:24 PM PDT 24
Finished Jul 10 05:35:26 PM PDT 24
Peak memory 194632 kb
Host smart-4ba7b1b6-a866-42c1-8043-b3e648c61a45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178899771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.4178899771
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3465675414
Short name T383
Test name
Test status
Simulation time 91413873 ps
CPU time 0.72 seconds
Started Jul 10 05:35:07 PM PDT 24
Finished Jul 10 05:35:10 PM PDT 24
Peak memory 194748 kb
Host smart-79e92bdf-a0b7-4b1d-99a5-21a10ada1e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465675414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3465675414
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1406581118
Short name T414
Test name
Test status
Simulation time 963646847 ps
CPU time 15.26 seconds
Started Jul 10 05:35:06 PM PDT 24
Finished Jul 10 05:35:23 PM PDT 24
Peak memory 198628 kb
Host smart-1aa0f56c-eff1-4444-9965-2717cd71a65e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406581118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1406581118
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1737675688
Short name T214
Test name
Test status
Simulation time 254032725 ps
CPU time 0.64 seconds
Started Jul 10 05:35:06 PM PDT 24
Finished Jul 10 05:35:09 PM PDT 24
Peak memory 195084 kb
Host smart-45fa93ef-0847-47f7-9797-c6bcb385ff33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737675688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1737675688
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.646732410
Short name T472
Test name
Test status
Simulation time 23388433 ps
CPU time 0.84 seconds
Started Jul 10 05:35:08 PM PDT 24
Finished Jul 10 05:35:11 PM PDT 24
Peak memory 196980 kb
Host smart-2e42ee20-8164-4f2b-9ff1-d13c631c8f74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646732410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.646732410
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.4206886209
Short name T567
Test name
Test status
Simulation time 103473458 ps
CPU time 2.44 seconds
Started Jul 10 05:35:05 PM PDT 24
Finished Jul 10 05:35:09 PM PDT 24
Peak memory 198724 kb
Host smart-fe45ef5d-7b14-4b26-b3a4-9036a5b6e6d7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206886209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.4206886209
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2278554881
Short name T370
Test name
Test status
Simulation time 107607340 ps
CPU time 1.92 seconds
Started Jul 10 05:35:08 PM PDT 24
Finished Jul 10 05:35:11 PM PDT 24
Peak memory 197024 kb
Host smart-879c0773-3acf-4a64-912d-3a6d1fd153df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278554881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2278554881
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.7943042
Short name T242
Test name
Test status
Simulation time 141426750 ps
CPU time 0.83 seconds
Started Jul 10 05:35:07 PM PDT 24
Finished Jul 10 05:35:09 PM PDT 24
Peak memory 196140 kb
Host smart-ef95e5cb-3108-49f2-8973-6c6e7d2e9d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7943042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.7943042
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3841586693
Short name T137
Test name
Test status
Simulation time 215318612 ps
CPU time 1.2 seconds
Started Jul 10 05:35:07 PM PDT 24
Finished Jul 10 05:35:09 PM PDT 24
Peak memory 197476 kb
Host smart-2f09ec77-2f32-48c8-856d-2a5964d3cb29
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841586693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3841586693
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.388606119
Short name T454
Test name
Test status
Simulation time 1187677773 ps
CPU time 5.82 seconds
Started Jul 10 05:35:07 PM PDT 24
Finished Jul 10 05:35:15 PM PDT 24
Peak memory 198728 kb
Host smart-f6c3e875-deb1-46f2-bbbc-fdd93b06f0d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388606119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.388606119
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1466858287
Short name T430
Test name
Test status
Simulation time 36859483 ps
CPU time 1.02 seconds
Started Jul 10 05:35:06 PM PDT 24
Finished Jul 10 05:35:08 PM PDT 24
Peak memory 197312 kb
Host smart-6c9875e3-d730-4bc8-a2e1-350808d0bfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466858287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1466858287
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3658601827
Short name T502
Test name
Test status
Simulation time 45715129 ps
CPU time 1.33 seconds
Started Jul 10 05:35:06 PM PDT 24
Finished Jul 10 05:35:09 PM PDT 24
Peak memory 198596 kb
Host smart-3e9baefe-4dbe-43a5-bf9c-cf1c141ef981
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658601827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3658601827
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1770887110
Short name T642
Test name
Test status
Simulation time 8137336527 ps
CPU time 118.77 seconds
Started Jul 10 05:35:13 PM PDT 24
Finished Jul 10 05:37:13 PM PDT 24
Peak memory 198644 kb
Host smart-139fbcec-5223-4680-8176-8c4f0c1dfa9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770887110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1770887110
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3498478841
Short name T942
Test name
Test status
Simulation time 235475259 ps
CPU time 1.28 seconds
Started Jul 10 04:50:04 PM PDT 24
Finished Jul 10 04:50:06 PM PDT 24
Peak memory 196192 kb
Host smart-5a49f51c-7e67-443f-8b33-f86f3f7bd6dd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3498478841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3498478841
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2168000896
Short name T873
Test name
Test status
Simulation time 33831473 ps
CPU time 1.07 seconds
Started Jul 10 04:50:05 PM PDT 24
Finished Jul 10 04:50:07 PM PDT 24
Peak memory 196720 kb
Host smart-60fbe519-c683-4cfe-a62d-408097151f31
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168000896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2168000896
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3846118554
Short name T895
Test name
Test status
Simulation time 58872145 ps
CPU time 1.27 seconds
Started Jul 10 04:50:04 PM PDT 24
Finished Jul 10 04:50:07 PM PDT 24
Peak memory 196860 kb
Host smart-4d0dec34-c0bf-424d-8c76-afefd3b4eeaf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3846118554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3846118554
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.635481290
Short name T916
Test name
Test status
Simulation time 36645457 ps
CPU time 1.21 seconds
Started Jul 10 04:50:03 PM PDT 24
Finished Jul 10 04:50:05 PM PDT 24
Peak memory 198356 kb
Host smart-2532e8ff-94b0-4068-81c3-bd4796de0f6d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635481290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.635481290
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.430631564
Short name T867
Test name
Test status
Simulation time 127621110 ps
CPU time 1.2 seconds
Started Jul 10 04:50:09 PM PDT 24
Finished Jul 10 04:50:11 PM PDT 24
Peak memory 198368 kb
Host smart-5cde7142-c10b-463b-9c33-30cb3626b7c0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=430631564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.430631564
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.468158924
Short name T864
Test name
Test status
Simulation time 141105616 ps
CPU time 1.09 seconds
Started Jul 10 04:50:11 PM PDT 24
Finished Jul 10 04:50:13 PM PDT 24
Peak memory 198348 kb
Host smart-f0ae3bec-790b-4369-9dab-036d0597cb12
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468158924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.468158924
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.4107537097
Short name T879
Test name
Test status
Simulation time 37509596 ps
CPU time 1.06 seconds
Started Jul 10 04:50:11 PM PDT 24
Finished Jul 10 04:50:13 PM PDT 24
Peak memory 198312 kb
Host smart-6c34fcc2-1f5f-4150-9255-d451e7b036d0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4107537097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.4107537097
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2585295170
Short name T945
Test name
Test status
Simulation time 300324199 ps
CPU time 1.33 seconds
Started Jul 10 04:50:10 PM PDT 24
Finished Jul 10 04:50:13 PM PDT 24
Peak memory 196948 kb
Host smart-8dc2b8ac-deb9-4dc0-ac3d-b9f515de4655
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585295170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2585295170
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.895637678
Short name T882
Test name
Test status
Simulation time 127318914 ps
CPU time 0.99 seconds
Started Jul 10 04:50:12 PM PDT 24
Finished Jul 10 04:50:14 PM PDT 24
Peak memory 197060 kb
Host smart-bd9dd478-a452-4ef1-b2ad-bab6c46a96fc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=895637678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.895637678
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3912962778
Short name T911
Test name
Test status
Simulation time 122871109 ps
CPU time 1.04 seconds
Started Jul 10 04:50:11 PM PDT 24
Finished Jul 10 04:50:13 PM PDT 24
Peak memory 196344 kb
Host smart-042cd9e5-7980-4995-9058-50c40a64483f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912962778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3912962778
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2472787012
Short name T901
Test name
Test status
Simulation time 141266180 ps
CPU time 0.89 seconds
Started Jul 10 04:50:12 PM PDT 24
Finished Jul 10 04:50:14 PM PDT 24
Peak memory 196564 kb
Host smart-e100b7c6-3cc6-47b6-8762-1fb92667975c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2472787012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2472787012
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3859980167
Short name T853
Test name
Test status
Simulation time 54435120 ps
CPU time 1.1 seconds
Started Jul 10 04:50:09 PM PDT 24
Finished Jul 10 04:50:11 PM PDT 24
Peak memory 196996 kb
Host smart-934a5e83-2ec5-47b9-ac4d-a43f740d81af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859980167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3859980167
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.217244150
Short name T874
Test name
Test status
Simulation time 231664025 ps
CPU time 1.14 seconds
Started Jul 10 04:50:17 PM PDT 24
Finished Jul 10 04:50:21 PM PDT 24
Peak memory 197400 kb
Host smart-61d4b757-e842-4b56-af4d-f9954917fc16
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=217244150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.217244150
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3453435024
Short name T898
Test name
Test status
Simulation time 59679052 ps
CPU time 1.13 seconds
Started Jul 10 04:50:17 PM PDT 24
Finished Jul 10 04:50:19 PM PDT 24
Peak memory 196876 kb
Host smart-ef598d4f-bc16-41f8-a435-08308e38d488
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453435024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3453435024
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1620599804
Short name T849
Test name
Test status
Simulation time 65097277 ps
CPU time 1.32 seconds
Started Jul 10 04:50:15 PM PDT 24
Finished Jul 10 04:50:17 PM PDT 24
Peak memory 196968 kb
Host smart-f4fd1e0e-943a-40bc-90b3-171ad693c029
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1620599804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1620599804
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.638405374
Short name T902
Test name
Test status
Simulation time 72331315 ps
CPU time 1.21 seconds
Started Jul 10 04:50:18 PM PDT 24
Finished Jul 10 04:50:22 PM PDT 24
Peak memory 198336 kb
Host smart-61e534e6-c36c-4beb-93c6-6726ec944742
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638405374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.638405374
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.527614474
Short name T909
Test name
Test status
Simulation time 1429665015 ps
CPU time 1.39 seconds
Started Jul 10 04:50:18 PM PDT 24
Finished Jul 10 04:50:22 PM PDT 24
Peak memory 198316 kb
Host smart-4bd5e09a-2510-4a71-abab-c3c7870294b9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=527614474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.527614474
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3357902597
Short name T925
Test name
Test status
Simulation time 18608890 ps
CPU time 0.73 seconds
Started Jul 10 04:50:16 PM PDT 24
Finished Jul 10 04:50:17 PM PDT 24
Peak memory 194584 kb
Host smart-2d6ab125-4b00-46b6-8c05-f80174075433
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357902597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3357902597
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3947000791
Short name T928
Test name
Test status
Simulation time 202480429 ps
CPU time 1.24 seconds
Started Jul 10 04:50:18 PM PDT 24
Finished Jul 10 04:50:23 PM PDT 24
Peak memory 197048 kb
Host smart-cf34ae69-b3f9-4627-a52e-42584c21abc4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3947000791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3947000791
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1168018878
Short name T885
Test name
Test status
Simulation time 119201491 ps
CPU time 0.84 seconds
Started Jul 10 04:50:17 PM PDT 24
Finished Jul 10 04:50:21 PM PDT 24
Peak memory 196424 kb
Host smart-f0b3086f-ad79-4486-a587-198202dc1656
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168018878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1168018878
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1007419150
Short name T860
Test name
Test status
Simulation time 187931590 ps
CPU time 1.14 seconds
Started Jul 10 04:50:17 PM PDT 24
Finished Jul 10 04:50:21 PM PDT 24
Peak memory 196812 kb
Host smart-b15d5d6a-1a78-475e-b5d7-3f886cf31326
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1007419150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1007419150
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1867160082
Short name T863
Test name
Test status
Simulation time 123973679 ps
CPU time 1.19 seconds
Started Jul 10 04:50:16 PM PDT 24
Finished Jul 10 04:50:19 PM PDT 24
Peak memory 196856 kb
Host smart-8524e4a1-7208-4fbe-b258-046324de6f29
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867160082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1867160082
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.4269694364
Short name T914
Test name
Test status
Simulation time 571120088 ps
CPU time 1.07 seconds
Started Jul 10 04:50:18 PM PDT 24
Finished Jul 10 04:50:22 PM PDT 24
Peak memory 196808 kb
Host smart-59e35c2e-9b3f-42bf-b46b-0e7d22fc0186
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4269694364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.4269694364
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1888857994
Short name T869
Test name
Test status
Simulation time 316731010 ps
CPU time 1.36 seconds
Started Jul 10 04:50:16 PM PDT 24
Finished Jul 10 04:50:18 PM PDT 24
Peak memory 198304 kb
Host smart-53fcb619-5707-4bdd-8850-0d5dba818a8a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888857994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1888857994
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3306723128
Short name T918
Test name
Test status
Simulation time 108349785 ps
CPU time 0.96 seconds
Started Jul 10 04:50:04 PM PDT 24
Finished Jul 10 04:50:06 PM PDT 24
Peak memory 195812 kb
Host smart-b2130d14-d1e3-4dd3-82b4-8635ef53df82
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3306723128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3306723128
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1739575081
Short name T854
Test name
Test status
Simulation time 126009273 ps
CPU time 1.21 seconds
Started Jul 10 04:50:04 PM PDT 24
Finished Jul 10 04:50:07 PM PDT 24
Peak memory 192336 kb
Host smart-a72c6057-204a-4956-b5bc-6106b1ce1acb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739575081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1739575081
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1602737192
Short name T889
Test name
Test status
Simulation time 75661002 ps
CPU time 1.4 seconds
Started Jul 10 04:50:15 PM PDT 24
Finished Jul 10 04:50:18 PM PDT 24
Peak memory 196960 kb
Host smart-8923f0fa-de00-4ade-acdf-5bd431e2a9ce
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1602737192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1602737192
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.996397147
Short name T926
Test name
Test status
Simulation time 44525392 ps
CPU time 1.02 seconds
Started Jul 10 04:50:16 PM PDT 24
Finished Jul 10 04:50:18 PM PDT 24
Peak memory 196892 kb
Host smart-275fe9f2-b80c-403b-96f5-f6a39677b4ad
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996397147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.996397147
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1399255952
Short name T922
Test name
Test status
Simulation time 72647750 ps
CPU time 1.32 seconds
Started Jul 10 04:50:18 PM PDT 24
Finished Jul 10 04:50:22 PM PDT 24
Peak memory 196864 kb
Host smart-6030c7db-d4e3-4cd4-9efc-17ca2b52e748
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1399255952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1399255952
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.216661698
Short name T939
Test name
Test status
Simulation time 70097941 ps
CPU time 1.12 seconds
Started Jul 10 04:50:18 PM PDT 24
Finished Jul 10 04:50:22 PM PDT 24
Peak memory 196560 kb
Host smart-a6bf98b5-7e2b-49ef-938e-5723f1aa390f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216661698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.216661698
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.153201426
Short name T892
Test name
Test status
Simulation time 26539708 ps
CPU time 0.79 seconds
Started Jul 10 04:50:17 PM PDT 24
Finished Jul 10 04:50:21 PM PDT 24
Peak memory 195792 kb
Host smart-1c978b17-66c2-4461-ad47-c0e1e762fc53
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=153201426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.153201426
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3412707033
Short name T890
Test name
Test status
Simulation time 325456159 ps
CPU time 1.31 seconds
Started Jul 10 04:50:18 PM PDT 24
Finished Jul 10 04:50:23 PM PDT 24
Peak memory 197236 kb
Host smart-ac74e063-13dc-4767-89cb-73c200cc33f3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412707033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3412707033
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.304201449
Short name T905
Test name
Test status
Simulation time 69538610 ps
CPU time 1.11 seconds
Started Jul 10 04:50:16 PM PDT 24
Finished Jul 10 04:50:18 PM PDT 24
Peak memory 197088 kb
Host smart-ecaa27b1-777d-45db-9157-96feab5b585d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=304201449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.304201449
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.585194211
Short name T881
Test name
Test status
Simulation time 265414779 ps
CPU time 1.44 seconds
Started Jul 10 04:50:18 PM PDT 24
Finished Jul 10 04:50:22 PM PDT 24
Peak memory 198352 kb
Host smart-5344c28a-7051-4931-a551-e95765346ced
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585194211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.585194211
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1060895577
Short name T932
Test name
Test status
Simulation time 32882852 ps
CPU time 0.98 seconds
Started Jul 10 04:50:17 PM PDT 24
Finished Jul 10 04:50:21 PM PDT 24
Peak memory 196804 kb
Host smart-193a009e-f57b-435b-bc84-7bde12062505
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1060895577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1060895577
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3993476369
Short name T884
Test name
Test status
Simulation time 41306234 ps
CPU time 1.27 seconds
Started Jul 10 04:50:16 PM PDT 24
Finished Jul 10 04:50:17 PM PDT 24
Peak memory 196176 kb
Host smart-cd2c202b-5b5c-42f6-a204-0b9784c3550e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993476369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3993476369
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3766869720
Short name T893
Test name
Test status
Simulation time 65570896 ps
CPU time 0.8 seconds
Started Jul 10 04:50:16 PM PDT 24
Finished Jul 10 04:50:18 PM PDT 24
Peak memory 195640 kb
Host smart-4071765f-a80a-4a8c-a2fa-9426b1f5713b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3766869720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3766869720
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2237607165
Short name T880
Test name
Test status
Simulation time 45882640 ps
CPU time 0.89 seconds
Started Jul 10 04:50:18 PM PDT 24
Finished Jul 10 04:50:22 PM PDT 24
Peak memory 196772 kb
Host smart-a61e8d02-234b-44af-9724-717ffededdb1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237607165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2237607165
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3360350571
Short name T920
Test name
Test status
Simulation time 619064787 ps
CPU time 1.55 seconds
Started Jul 10 04:50:16 PM PDT 24
Finished Jul 10 04:50:19 PM PDT 24
Peak memory 197212 kb
Host smart-ce0c239d-f079-4756-ba9d-644f78b33f5a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3360350571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3360350571
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3627317793
Short name T931
Test name
Test status
Simulation time 224439178 ps
CPU time 0.9 seconds
Started Jul 10 04:50:24 PM PDT 24
Finished Jul 10 04:50:26 PM PDT 24
Peak memory 198180 kb
Host smart-426edfc0-9fa2-4c48-a4ad-316e79d886e5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627317793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3627317793
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1935804238
Short name T891
Test name
Test status
Simulation time 116540572 ps
CPU time 1.2 seconds
Started Jul 10 04:50:22 PM PDT 24
Finished Jul 10 04:50:26 PM PDT 24
Peak memory 196836 kb
Host smart-4e2768ec-41be-41ac-8ca5-803eae33feeb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1935804238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1935804238
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.744646875
Short name T900
Test name
Test status
Simulation time 159174654 ps
CPU time 1.36 seconds
Started Jul 10 04:50:25 PM PDT 24
Finished Jul 10 04:50:28 PM PDT 24
Peak memory 197308 kb
Host smart-51f2d2fc-f71a-4b80-a48c-b7881663b6fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744646875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.744646875
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3220792102
Short name T888
Test name
Test status
Simulation time 143020000 ps
CPU time 1.36 seconds
Started Jul 10 04:50:23 PM PDT 24
Finished Jul 10 04:50:26 PM PDT 24
Peak memory 197548 kb
Host smart-ad8dc87e-0883-4605-bc23-f39de6254028
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3220792102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3220792102
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.175415163
Short name T883
Test name
Test status
Simulation time 160914821 ps
CPU time 1.23 seconds
Started Jul 10 04:50:23 PM PDT 24
Finished Jul 10 04:50:27 PM PDT 24
Peak memory 197096 kb
Host smart-fcdcf4b5-681f-4bb9-b046-b1f0d331c7a8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175415163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.175415163
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3203312983
Short name T946
Test name
Test status
Simulation time 119152955 ps
CPU time 0.95 seconds
Started Jul 10 04:50:22 PM PDT 24
Finished Jul 10 04:50:25 PM PDT 24
Peak memory 195660 kb
Host smart-bffca402-2d79-4fa9-b4e8-fed0904aebd8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3203312983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3203312983
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1873835608
Short name T924
Test name
Test status
Simulation time 77835935 ps
CPU time 1.34 seconds
Started Jul 10 04:50:26 PM PDT 24
Finished Jul 10 04:50:29 PM PDT 24
Peak memory 197272 kb
Host smart-b3bb996e-2584-4645-a19b-d9d86bab4cd8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873835608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1873835608
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1069378426
Short name T887
Test name
Test status
Simulation time 921232864 ps
CPU time 1.25 seconds
Started Jul 10 04:50:03 PM PDT 24
Finished Jul 10 04:50:06 PM PDT 24
Peak memory 197004 kb
Host smart-62ab8e0d-0908-42b5-8e76-17d9f7f9ae74
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1069378426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1069378426
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4219176307
Short name T871
Test name
Test status
Simulation time 258306724 ps
CPU time 1.15 seconds
Started Jul 10 04:50:05 PM PDT 24
Finished Jul 10 04:50:08 PM PDT 24
Peak memory 196812 kb
Host smart-9c7e2fae-52d5-40a3-8917-138ca0a75d35
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219176307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4219176307
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3465824162
Short name T904
Test name
Test status
Simulation time 245320051 ps
CPU time 1.15 seconds
Started Jul 10 04:50:23 PM PDT 24
Finished Jul 10 04:50:26 PM PDT 24
Peak memory 196928 kb
Host smart-b90d2b3a-6e7c-4f8b-ae04-694e89dc65b5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3465824162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3465824162
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2015402619
Short name T897
Test name
Test status
Simulation time 352337412 ps
CPU time 1.44 seconds
Started Jul 10 04:50:24 PM PDT 24
Finished Jul 10 04:50:27 PM PDT 24
Peak memory 197148 kb
Host smart-465a88b6-6026-4fd8-b74e-a1fca7167529
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015402619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2015402619
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2409222792
Short name T899
Test name
Test status
Simulation time 79837970 ps
CPU time 1.33 seconds
Started Jul 10 04:50:22 PM PDT 24
Finished Jul 10 04:50:25 PM PDT 24
Peak memory 197080 kb
Host smart-73276950-a271-494a-924b-8d33a626cf7b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2409222792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2409222792
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1393543090
Short name T847
Test name
Test status
Simulation time 202676706 ps
CPU time 1.09 seconds
Started Jul 10 04:50:26 PM PDT 24
Finished Jul 10 04:50:28 PM PDT 24
Peak memory 196872 kb
Host smart-6e29a429-6baf-4c0c-a352-933bab9de4db
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393543090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1393543090
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1165320636
Short name T940
Test name
Test status
Simulation time 52002864 ps
CPU time 1.1 seconds
Started Jul 10 04:50:25 PM PDT 24
Finished Jul 10 04:50:28 PM PDT 24
Peak memory 198396 kb
Host smart-d120f128-9616-4402-950b-90312bca1e4a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1165320636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1165320636
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2945092654
Short name T857
Test name
Test status
Simulation time 62315774 ps
CPU time 1.31 seconds
Started Jul 10 04:50:23 PM PDT 24
Finished Jul 10 04:50:26 PM PDT 24
Peak memory 196000 kb
Host smart-9103a344-b579-45c6-b259-def63bf6c0f0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945092654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2945092654
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2556814141
Short name T927
Test name
Test status
Simulation time 86634427 ps
CPU time 0.89 seconds
Started Jul 10 04:50:24 PM PDT 24
Finished Jul 10 04:50:27 PM PDT 24
Peak memory 197720 kb
Host smart-467ac517-0a46-41bc-8daf-5f06b0d6bb76
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2556814141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2556814141
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.266296541
Short name T910
Test name
Test status
Simulation time 46715974 ps
CPU time 0.94 seconds
Started Jul 10 04:50:25 PM PDT 24
Finished Jul 10 04:50:28 PM PDT 24
Peak memory 196760 kb
Host smart-f2140dee-dd1e-4fe2-a539-87a5099ec6d4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266296541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.266296541
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.392688103
Short name T851
Test name
Test status
Simulation time 449564056 ps
CPU time 0.92 seconds
Started Jul 10 04:50:24 PM PDT 24
Finished Jul 10 04:50:27 PM PDT 24
Peak memory 198172 kb
Host smart-83223ae7-373f-4f6d-97f1-e6fd6178aa63
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=392688103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.392688103
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1208534722
Short name T862
Test name
Test status
Simulation time 216906120 ps
CPU time 1.14 seconds
Started Jul 10 04:50:22 PM PDT 24
Finished Jul 10 04:50:25 PM PDT 24
Peak memory 196988 kb
Host smart-cd42b039-5710-4650-b547-e3b678192e35
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208534722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1208534722
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4172490960
Short name T912
Test name
Test status
Simulation time 25288975 ps
CPU time 0.8 seconds
Started Jul 10 04:50:22 PM PDT 24
Finished Jul 10 04:50:25 PM PDT 24
Peak memory 195736 kb
Host smart-402f37e9-7d13-4675-b0d1-9e0a6d5ebb59
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4172490960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.4172490960
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2595547344
Short name T903
Test name
Test status
Simulation time 163373983 ps
CPU time 1.17 seconds
Started Jul 10 04:50:23 PM PDT 24
Finished Jul 10 04:50:26 PM PDT 24
Peak memory 197052 kb
Host smart-204516f1-ad13-4536-a5f1-e6ff5e968134
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595547344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2595547344
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.458412730
Short name T877
Test name
Test status
Simulation time 68953827 ps
CPU time 0.69 seconds
Started Jul 10 04:50:23 PM PDT 24
Finished Jul 10 04:50:26 PM PDT 24
Peak memory 194668 kb
Host smart-e2cf5467-9356-45f5-996b-84e9e1361021
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=458412730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.458412730
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.22100582
Short name T855
Test name
Test status
Simulation time 30005953 ps
CPU time 0.98 seconds
Started Jul 10 04:50:34 PM PDT 24
Finished Jul 10 04:50:37 PM PDT 24
Peak memory 196824 kb
Host smart-82b295f3-1238-4e53-80cd-e80e57524c03
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22100582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.22100582
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.44317727
Short name T917
Test name
Test status
Simulation time 69612962 ps
CPU time 1.27 seconds
Started Jul 10 04:50:35 PM PDT 24
Finished Jul 10 04:50:38 PM PDT 24
Peak memory 196928 kb
Host smart-7ef073b2-8fbb-44f8-826e-3989d78752f0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=44317727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.44317727
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.349584349
Short name T919
Test name
Test status
Simulation time 196818584 ps
CPU time 1.4 seconds
Started Jul 10 04:50:34 PM PDT 24
Finished Jul 10 04:50:38 PM PDT 24
Peak memory 198380 kb
Host smart-3f365cb2-4902-465e-9142-6ea3eef90cae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349584349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.349584349
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3217004447
Short name T915
Test name
Test status
Simulation time 58853391 ps
CPU time 1.12 seconds
Started Jul 10 04:50:34 PM PDT 24
Finished Jul 10 04:50:38 PM PDT 24
Peak memory 196224 kb
Host smart-4143b499-9876-4966-abec-656602e79c1e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3217004447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3217004447
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4261587893
Short name T908
Test name
Test status
Simulation time 48733748 ps
CPU time 0.94 seconds
Started Jul 10 04:50:33 PM PDT 24
Finished Jul 10 04:50:36 PM PDT 24
Peak memory 195708 kb
Host smart-1aaec751-a362-4bcd-a8d3-0f31dd9930a4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261587893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4261587893
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1205843370
Short name T906
Test name
Test status
Simulation time 235335308 ps
CPU time 1.14 seconds
Started Jul 10 04:50:34 PM PDT 24
Finished Jul 10 04:50:38 PM PDT 24
Peak memory 196880 kb
Host smart-acdf7cce-199b-4bab-b5bd-9cb05b78d9f2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1205843370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1205843370
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2103294433
Short name T907
Test name
Test status
Simulation time 115910663 ps
CPU time 1.29 seconds
Started Jul 10 04:50:33 PM PDT 24
Finished Jul 10 04:50:37 PM PDT 24
Peak memory 197280 kb
Host smart-e2eadc85-661b-45fb-b970-f59accbbaee4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103294433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2103294433
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.855419566
Short name T929
Test name
Test status
Simulation time 150555428 ps
CPU time 1.31 seconds
Started Jul 10 04:50:04 PM PDT 24
Finished Jul 10 04:50:06 PM PDT 24
Peak memory 197508 kb
Host smart-6d893dcf-48bd-4a63-b97e-7413c4657ce5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=855419566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.855419566
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3900974151
Short name T938
Test name
Test status
Simulation time 613154161 ps
CPU time 1.4 seconds
Started Jul 10 04:50:07 PM PDT 24
Finished Jul 10 04:50:09 PM PDT 24
Peak memory 197140 kb
Host smart-a4b58ab1-87e6-4aae-8c37-c558d6464f0d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900974151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3900974151
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2209550300
Short name T944
Test name
Test status
Simulation time 100247852 ps
CPU time 1.12 seconds
Started Jul 10 04:50:33 PM PDT 24
Finished Jul 10 04:50:37 PM PDT 24
Peak memory 196936 kb
Host smart-c82c16dc-46c1-40ef-9ff0-cf5337b58f76
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2209550300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2209550300
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.460269114
Short name T896
Test name
Test status
Simulation time 61579891 ps
CPU time 1.16 seconds
Started Jul 10 04:50:33 PM PDT 24
Finished Jul 10 04:50:37 PM PDT 24
Peak memory 196908 kb
Host smart-d9918103-821f-48e1-a5fa-37802986e254
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460269114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.460269114
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.229328427
Short name T872
Test name
Test status
Simulation time 72014223 ps
CPU time 1.06 seconds
Started Jul 10 04:50:34 PM PDT 24
Finished Jul 10 04:50:38 PM PDT 24
Peak memory 195944 kb
Host smart-f78a41a3-a336-4c5d-8dca-dc368387ad93
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=229328427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.229328427
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1892839051
Short name T937
Test name
Test status
Simulation time 213944873 ps
CPU time 1.21 seconds
Started Jul 10 04:50:32 PM PDT 24
Finished Jul 10 04:50:34 PM PDT 24
Peak memory 196012 kb
Host smart-59b30d4e-1bf1-463d-a0bd-534a7040dbd6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892839051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1892839051
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1745466542
Short name T858
Test name
Test status
Simulation time 403290756 ps
CPU time 1.09 seconds
Started Jul 10 04:50:33 PM PDT 24
Finished Jul 10 04:50:37 PM PDT 24
Peak memory 198312 kb
Host smart-6dfc86ed-c5f7-49f4-8d30-690edff4732f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1745466542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1745466542
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2092265004
Short name T878
Test name
Test status
Simulation time 79232740 ps
CPU time 1.53 seconds
Started Jul 10 04:50:32 PM PDT 24
Finished Jul 10 04:50:35 PM PDT 24
Peak memory 197056 kb
Host smart-51151936-25a0-4b93-9722-cb2610385225
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092265004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2092265004
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2798097279
Short name T852
Test name
Test status
Simulation time 145235816 ps
CPU time 0.84 seconds
Started Jul 10 04:50:32 PM PDT 24
Finished Jul 10 04:50:35 PM PDT 24
Peak memory 196428 kb
Host smart-d2c03b3e-1127-4ba5-a953-c23f64b7d001
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2798097279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2798097279
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2051449387
Short name T875
Test name
Test status
Simulation time 586315380 ps
CPU time 1.6 seconds
Started Jul 10 04:50:32 PM PDT 24
Finished Jul 10 04:50:35 PM PDT 24
Peak memory 197220 kb
Host smart-51905e0d-8066-43cb-b885-98898eb0fac7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051449387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2051449387
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1822461910
Short name T859
Test name
Test status
Simulation time 82754159 ps
CPU time 0.91 seconds
Started Jul 10 04:50:33 PM PDT 24
Finished Jul 10 04:50:37 PM PDT 24
Peak memory 195628 kb
Host smart-4dc30c46-9f36-4993-b1a7-b760dc30fd88
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1822461910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1822461910
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.387520535
Short name T865
Test name
Test status
Simulation time 74097105 ps
CPU time 0.93 seconds
Started Jul 10 04:50:36 PM PDT 24
Finished Jul 10 04:50:39 PM PDT 24
Peak memory 195776 kb
Host smart-7b708de7-bf48-4efb-8114-2cb0bc5dccc7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387520535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.387520535
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2665859234
Short name T933
Test name
Test status
Simulation time 50921001 ps
CPU time 0.81 seconds
Started Jul 10 04:50:30 PM PDT 24
Finished Jul 10 04:50:32 PM PDT 24
Peak memory 195772 kb
Host smart-e7c813ed-f0ed-4621-a826-790985e7d159
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2665859234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2665859234
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3247759330
Short name T861
Test name
Test status
Simulation time 70782619 ps
CPU time 1.19 seconds
Started Jul 10 04:50:32 PM PDT 24
Finished Jul 10 04:50:34 PM PDT 24
Peak memory 196832 kb
Host smart-c46e3329-800b-4282-aee1-70bb8ad67ff3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247759330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3247759330
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2971691403
Short name T850
Test name
Test status
Simulation time 122165041 ps
CPU time 0.92 seconds
Started Jul 10 04:50:34 PM PDT 24
Finished Jul 10 04:50:38 PM PDT 24
Peak memory 196784 kb
Host smart-096c1026-4879-45fd-b243-36a5bb075d4b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2971691403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2971691403
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3579264848
Short name T930
Test name
Test status
Simulation time 63976353 ps
CPU time 0.85 seconds
Started Jul 10 04:50:34 PM PDT 24
Finished Jul 10 04:50:38 PM PDT 24
Peak memory 195556 kb
Host smart-00cee6ce-227a-4978-aaf8-de86de61d7bc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579264848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3579264848
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3020951042
Short name T913
Test name
Test status
Simulation time 63675398 ps
CPU time 1.22 seconds
Started Jul 10 04:50:33 PM PDT 24
Finished Jul 10 04:50:36 PM PDT 24
Peak memory 197208 kb
Host smart-b948dcc3-b0e0-4e78-a2a4-0b6e341661fe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3020951042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3020951042
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1662826493
Short name T848
Test name
Test status
Simulation time 23443225 ps
CPU time 0.9 seconds
Started Jul 10 04:50:32 PM PDT 24
Finished Jul 10 04:50:35 PM PDT 24
Peak memory 196768 kb
Host smart-ba0bf3d9-1f3a-4653-8939-8eefdb9a7176
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662826493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1662826493
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.450081635
Short name T936
Test name
Test status
Simulation time 96675440 ps
CPU time 0.96 seconds
Started Jul 10 04:50:32 PM PDT 24
Finished Jul 10 04:50:34 PM PDT 24
Peak memory 198168 kb
Host smart-7b7a03ef-745c-45b6-86bc-d00536b62313
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=450081635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.450081635
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1218398872
Short name T943
Test name
Test status
Simulation time 151160398 ps
CPU time 1.29 seconds
Started Jul 10 04:50:33 PM PDT 24
Finished Jul 10 04:50:36 PM PDT 24
Peak memory 197364 kb
Host smart-5b5cf4e8-76db-4b5f-a135-f3716c760762
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218398872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1218398872
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2824298785
Short name T870
Test name
Test status
Simulation time 51138631 ps
CPU time 1.14 seconds
Started Jul 10 04:50:33 PM PDT 24
Finished Jul 10 04:50:36 PM PDT 24
Peak memory 197924 kb
Host smart-f969e72e-99ca-42a8-8d3a-3242ede05107
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2824298785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2824298785
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3174025828
Short name T935
Test name
Test status
Simulation time 81111461 ps
CPU time 1.24 seconds
Started Jul 10 04:50:32 PM PDT 24
Finished Jul 10 04:50:36 PM PDT 24
Peak memory 197048 kb
Host smart-88605ad0-bb1b-4ae2-9ffa-0c0a04c985b9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174025828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3174025828
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1519774661
Short name T886
Test name
Test status
Simulation time 70477808 ps
CPU time 1.29 seconds
Started Jul 10 04:50:07 PM PDT 24
Finished Jul 10 04:50:09 PM PDT 24
Peak memory 197208 kb
Host smart-89cadc82-c624-484c-94d8-35abb35ded0f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1519774661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1519774661
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.418779975
Short name T894
Test name
Test status
Simulation time 112433773 ps
CPU time 1.1 seconds
Started Jul 10 04:50:05 PM PDT 24
Finished Jul 10 04:50:08 PM PDT 24
Peak memory 192072 kb
Host smart-3ef95a4c-3bec-4045-8480-d9f8bbf3a174
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418779975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.418779975
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.474021692
Short name T866
Test name
Test status
Simulation time 79863775 ps
CPU time 1.24 seconds
Started Jul 10 04:50:07 PM PDT 24
Finished Jul 10 04:50:09 PM PDT 24
Peak memory 197560 kb
Host smart-6103ecf1-2bc8-4a53-93ab-b12cf89d0d42
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=474021692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.474021692
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.318363028
Short name T876
Test name
Test status
Simulation time 84972045 ps
CPU time 1.23 seconds
Started Jul 10 04:50:03 PM PDT 24
Finished Jul 10 04:50:06 PM PDT 24
Peak memory 198388 kb
Host smart-5c973e52-1515-47f5-9877-a5cf7616e33c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318363028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.318363028
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1054255057
Short name T856
Test name
Test status
Simulation time 78318019 ps
CPU time 1.39 seconds
Started Jul 10 04:50:09 PM PDT 24
Finished Jul 10 04:50:11 PM PDT 24
Peak memory 196924 kb
Host smart-7b1e3fc2-1960-4caf-9277-e7705aec4247
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1054255057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1054255057
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.149316407
Short name T934
Test name
Test status
Simulation time 285641078 ps
CPU time 0.97 seconds
Started Jul 10 04:50:09 PM PDT 24
Finished Jul 10 04:50:11 PM PDT 24
Peak memory 196672 kb
Host smart-cc7dc644-8066-4ece-a777-0faf1599b8ec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149316407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.149316407
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1081375044
Short name T921
Test name
Test status
Simulation time 84269781 ps
CPU time 0.97 seconds
Started Jul 10 04:50:09 PM PDT 24
Finished Jul 10 04:50:11 PM PDT 24
Peak memory 196684 kb
Host smart-1bc2f432-e135-44cf-9b3d-f3cff7306725
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1081375044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1081375044
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3875731298
Short name T923
Test name
Test status
Simulation time 28566396 ps
CPU time 0.91 seconds
Started Jul 10 04:50:12 PM PDT 24
Finished Jul 10 04:50:14 PM PDT 24
Peak memory 198164 kb
Host smart-10b7c6bc-72cd-4267-aaa2-6bf20f93d780
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875731298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3875731298
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1061059926
Short name T868
Test name
Test status
Simulation time 170156509 ps
CPU time 0.96 seconds
Started Jul 10 04:50:10 PM PDT 24
Finished Jul 10 04:50:13 PM PDT 24
Peak memory 195752 kb
Host smart-3262cc43-4380-4673-a95b-f1ab77567b85
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1061059926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1061059926
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2891769718
Short name T941
Test name
Test status
Simulation time 1186237371 ps
CPU time 1.48 seconds
Started Jul 10 04:50:10 PM PDT 24
Finished Jul 10 04:50:13 PM PDT 24
Peak memory 198404 kb
Host smart-c4baeda4-4839-423f-8499-0853e4f2ea25
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891769718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2891769718
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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