Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4068724	1			T21	1		T22	74		T23	1
all_pins[1]	4068724	1			T21	1		T22	74		T23	1
all_pins[2]	4068724	1			T21	1		T22	74		T23	1
all_pins[3]	4068724	1			T21	1		T22	74		T23	1
all_pins[4]	4068724	1			T21	1		T22	74		T23	1
all_pins[5]	4068724	1			T21	1		T22	74		T23	1
all_pins[6]	4068724	1			T21	1		T22	74		T23	1
all_pins[7]	4068724	1			T21	1		T22	74		T23	1
all_pins[8]	4068724	1			T21	1		T22	74		T23	1
all_pins[9]	4068724	1			T21	1		T22	74		T23	1
all_pins[10]	4068724	1			T21	1		T22	74		T23	1
all_pins[11]	4068724	1			T21	1		T22	74		T23	1
all_pins[12]	4068724	1			T21	1		T22	74		T23	1
all_pins[13]	4068724	1			T21	1		T22	74		T23	1
all_pins[14]	4068724	1			T21	1		T22	74		T23	1
all_pins[15]	4068724	1			T21	1		T22	74		T23	1
all_pins[16]	4068724	1			T21	1		T22	74		T23	1
all_pins[17]	4068724	1			T21	1		T22	74		T23	1
all_pins[18]	4068724	1			T21	1		T22	74		T23	1
all_pins[19]	4068724	1			T21	1		T22	74		T23	1
all_pins[20]	4068724	1			T21	1		T22	74		T23	1
all_pins[21]	4068724	1			T21	1		T22	74		T23	1
all_pins[22]	4068724	1			T21	1		T22	74		T23	1
all_pins[23]	4068724	1			T21	1		T22	74		T23	1
all_pins[24]	4068724	1			T21	1		T22	74		T23	1
all_pins[25]	4068724	1			T21	1		T22	74		T23	1
all_pins[26]	4068724	1			T21	1		T22	74		T23	1
all_pins[27]	4068724	1			T21	1		T22	74		T23	1
all_pins[28]	4068724	1			T21	1		T22	74		T23	1
all_pins[29]	4068724	1			T21	1		T22	74		T23	1
all_pins[30]	4068724	1			T21	1		T22	74		T23	1
all_pins[31]	4068724	1			T21	1		T22	74		T23	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	80892038	1			T21	32		T22	1887		T23	32
values[0x1]	49307130	1			T22	481		T26	252551		T27	1423
transitions[0x0=>0x1]	29549048	1			T22	312		T26	150051		T27	810
transitions[0x1=>0x0]	29548897	1			T22	311		T26	150051		T27	810

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2523490	1			T21	1		T22	53		T23	1
all_pins[0]	values[0x1]	1545234	1			T22	21		T26	7957		T27	37
all_pins[0]	transitions[0x0=>0x1]	956027	1			T22	19		T26	4851		T27	20
all_pins[0]	transitions[0x1=>0x0]	952871	1			T22	12		T26	4777		T27	31
all_pins[1]	values[0x0]	2527392	1			T21	1		T22	46		T23	1
all_pins[1]	values[0x1]	1541332	1			T22	28		T26	8011		T27	38
all_pins[1]	transitions[0x0=>0x1]	921923	1			T22	12		T26	4838		T27	21
all_pins[1]	transitions[0x1=>0x0]	925825	1			T22	5		T26	4784		T27	20
all_pins[2]	values[0x0]	2528187	1			T21	1		T22	52		T23	1
all_pins[2]	values[0x1]	1540537	1			T22	22		T26	7899		T27	62
all_pins[2]	transitions[0x0=>0x1]	922861	1			T22	13		T26	4617		T27	47
all_pins[2]	transitions[0x1=>0x0]	923656	1			T22	19		T26	4729		T27	23
all_pins[3]	values[0x0]	2527301	1			T21	1		T22	56		T23	1
all_pins[3]	values[0x1]	1541423	1			T22	18		T26	7831		T27	60
all_pins[3]	transitions[0x0=>0x1]	922978	1			T22	7		T26	4681		T27	20
all_pins[3]	transitions[0x1=>0x0]	922092	1			T22	11		T26	4749		T27	22
all_pins[4]	values[0x0]	2527671	1			T21	1		T22	61		T23	1
all_pins[4]	values[0x1]	1541053	1			T22	13		T26	7900		T27	32
all_pins[4]	transitions[0x0=>0x1]	920475	1			T22	13		T26	4612		T27	17
all_pins[4]	transitions[0x1=>0x0]	920845	1			T22	18		T26	4543		T27	45
all_pins[5]	values[0x0]	2527133	1			T21	1		T22	66		T23	1
all_pins[5]	values[0x1]	1541591	1			T22	8		T26	7562		T27	58
all_pins[5]	transitions[0x0=>0x1]	923403	1			T22	8		T26	4623		T27	36
all_pins[5]	transitions[0x1=>0x0]	922865	1			T22	13		T26	4961		T27	10
all_pins[6]	values[0x0]	2531965	1			T21	1		T22	58		T23	1
all_pins[6]	values[0x1]	1536759	1			T22	16		T26	7650		T27	64
all_pins[6]	transitions[0x0=>0x1]	918614	1			T22	12		T26	4651		T27	29
all_pins[6]	transitions[0x1=>0x0]	923446	1			T22	4		T26	4563		T27	23
all_pins[7]	values[0x0]	2527823	1			T21	1		T22	55		T23	1
all_pins[7]	values[0x1]	1540901	1			T22	19		T26	8048		T27	48
all_pins[7]	transitions[0x0=>0x1]	923428	1			T22	8		T26	4886		T27	21
all_pins[7]	transitions[0x1=>0x0]	919286	1			T22	5		T26	4488		T27	37
all_pins[8]	values[0x0]	2524068	1			T21	1		T22	57		T23	1
all_pins[8]	values[0x1]	1544656	1			T22	17		T26	7834		T27	21
all_pins[8]	transitions[0x0=>0x1]	926662	1			T22	9		T26	4614		T27	12
all_pins[8]	transitions[0x1=>0x0]	922907	1			T22	11		T26	4828		T27	39
all_pins[9]	values[0x0]	2529028	1			T21	1		T22	69		T23	1
all_pins[9]	values[0x1]	1539696	1			T22	5		T26	7631		T27	28
all_pins[9]	transitions[0x0=>0x1]	921905	1			T22	4		T26	4339		T27	23
all_pins[9]	transitions[0x1=>0x0]	926865	1			T22	16		T26	4542		T27	16
all_pins[10]	values[0x0]	2524461	1			T21	1		T22	59		T23	1
all_pins[10]	values[0x1]	1544263	1			T22	15		T26	7840		T27	30
all_pins[10]	transitions[0x0=>0x1]	924229	1			T22	15		T26	4744		T27	23
all_pins[10]	transitions[0x1=>0x0]	919662	1			T22	5		T26	4535		T27	21
all_pins[11]	values[0x0]	2525659	1			T21	1		T22	68		T23	1
all_pins[11]	values[0x1]	1543065	1			T22	6		T26	8095		T27	48
all_pins[11]	transitions[0x0=>0x1]	922196	1			T22	2		T26	4867		T27	39
all_pins[11]	transitions[0x1=>0x0]	923394	1			T22	11		T26	4612		T27	21
all_pins[12]	values[0x0]	2528266	1			T21	1		T22	65		T23	1
all_pins[12]	values[0x1]	1540458	1			T22	9		T26	7939		T27	38
all_pins[12]	transitions[0x0=>0x1]	922064	1			T22	7		T26	4742		T27	16
all_pins[12]	transitions[0x1=>0x0]	924671	1			T22	4		T26	4898		T27	26
all_pins[13]	values[0x0]	2532193	1			T21	1		T22	63		T23	1
all_pins[13]	values[0x1]	1536531	1			T22	11		T26	7955		T27	50
all_pins[13]	transitions[0x0=>0x1]	920132	1			T22	4		T26	4769		T27	27
all_pins[13]	transitions[0x1=>0x0]	924059	1			T22	2		T26	4753		T27	15
all_pins[14]	values[0x0]	2531035	1			T21	1		T22	69		T23	1
all_pins[14]	values[0x1]	1537689	1			T22	5		T26	7798		T27	48
all_pins[14]	transitions[0x0=>0x1]	921891	1			T22	5		T26	4551		T27	26
all_pins[14]	transitions[0x1=>0x0]	920733	1			T22	11		T26	4708		T27	28
all_pins[15]	values[0x0]	2523498	1			T21	1		T22	55		T23	1
all_pins[15]	values[0x1]	1545226	1			T22	19		T26	7851		T27	67
all_pins[15]	transitions[0x0=>0x1]	928987	1			T22	14		T26	4575		T27	32
all_pins[15]	transitions[0x1=>0x0]	921450	1			T26	4522		T27	13		T28	11040
all_pins[16]	values[0x0]	2529900	1			T21	1		T22	59		T23	1
all_pins[16]	values[0x1]	1538824	1			T22	15		T26	8120		T27	72
all_pins[16]	transitions[0x0=>0x1]	918102	1			T22	9		T26	4835		T27	37
all_pins[16]	transitions[0x1=>0x0]	924504	1			T22	13		T26	4566		T27	32
all_pins[17]	values[0x0]	2522278	1			T21	1		T22	56		T23	1
all_pins[17]	values[0x1]	1546446	1			T22	18		T26	8103		T27	54
all_pins[17]	transitions[0x0=>0x1]	927513	1			T22	9		T26	4506		T27	18
all_pins[17]	transitions[0x1=>0x0]	919891	1			T22	6		T26	4523		T27	36
all_pins[18]	values[0x0]	2529129	1			T21	1		T22	64		T23	1
all_pins[18]	values[0x1]	1539595	1			T22	10		T26	8104		T27	45
all_pins[18]	transitions[0x0=>0x1]	918060	1			T22	7		T26	4732		T27	18
all_pins[18]	transitions[0x1=>0x0]	924911	1			T22	15		T26	4731		T27	27
all_pins[19]	values[0x0]	2524656	1			T21	1		T22	53		T23	1
all_pins[19]	values[0x1]	1544068	1			T22	21		T26	7681		T27	41
all_pins[19]	transitions[0x0=>0x1]	923956	1			T22	15		T26	4563		T27	29
all_pins[19]	transitions[0x1=>0x0]	919483	1			T22	4		T26	4986		T27	33
all_pins[20]	values[0x0]	2526523	1			T21	1		T22	51		T23	1
all_pins[20]	values[0x1]	1542201	1			T22	23		T26	7544		T27	44
all_pins[20]	transitions[0x0=>0x1]	923207	1			T22	10		T26	4498		T27	22
all_pins[20]	transitions[0x1=>0x0]	925074	1			T22	8		T26	4635		T27	19
all_pins[21]	values[0x0]	2526810	1			T21	1		T22	57		T23	1
all_pins[21]	values[0x1]	1541914	1			T22	17		T26	8109		T27	36
all_pins[21]	transitions[0x0=>0x1]	921014	1			T22	5		T26	4992		T27	28
all_pins[21]	transitions[0x1=>0x0]	921301	1			T22	11		T26	4427		T27	36
all_pins[22]	values[0x0]	2526837	1			T21	1		T22	60		T23	1
all_pins[22]	values[0x1]	1541887	1			T22	14		T26	7554		T27	39
all_pins[22]	transitions[0x0=>0x1]	924467	1			T22	10		T26	4379		T27	25
all_pins[22]	transitions[0x1=>0x0]	924494	1			T22	13		T26	4934		T27	22
all_pins[23]	values[0x0]	2532454	1			T21	1		T22	60		T23	1
all_pins[23]	values[0x1]	1536270	1			T22	14		T26	7904		T27	44
all_pins[23]	transitions[0x0=>0x1]	920535	1			T22	14		T26	4776		T27	32
all_pins[23]	transitions[0x1=>0x0]	926152	1			T22	14		T26	4426		T27	27
all_pins[24]	values[0x0]	2530259	1			T21	1		T22	46		T23	1
all_pins[24]	values[0x1]	1538465	1			T22	28		T26	8015		T27	49
all_pins[24]	transitions[0x0=>0x1]	923439	1			T22	21		T26	5005		T27	30
all_pins[24]	transitions[0x1=>0x0]	921244	1			T22	7		T26	4894		T27	25
all_pins[25]	values[0x0]	2522832	1			T21	1		T22	52		T23	1
all_pins[25]	values[0x1]	1545892	1			T22	22		T26	7883		T27	50
all_pins[25]	transitions[0x0=>0x1]	926427	1			T22	5		T26	4572		T27	27
all_pins[25]	transitions[0x1=>0x0]	919000	1			T22	11		T26	4704		T27	26
all_pins[26]	values[0x0]	2529167	1			T21	1		T22	65		T23	1
all_pins[26]	values[0x1]	1539557	1			T22	9		T26	7931		T27	35
all_pins[26]	transitions[0x0=>0x1]	917842	1			T22	7		T26	4740		T27	17
all_pins[26]	transitions[0x1=>0x0]	924177	1			T22	20		T26	4692		T27	32
all_pins[27]	values[0x0]	2529871	1			T21	1		T22	67		T23	1
all_pins[27]	values[0x1]	1538853	1			T22	7		T26	7984		T27	19
all_pins[27]	transitions[0x0=>0x1]	919838	1			T22	5		T26	4808		T27	8
all_pins[27]	transitions[0x1=>0x0]	920542	1			T22	7		T26	4755		T27	24
all_pins[28]	values[0x0]	2527996	1			T21	1		T22	61		T23	1
all_pins[28]	values[0x1]	1540728	1			T22	13		T26	7949		T27	25
all_pins[28]	transitions[0x0=>0x1]	921724	1			T22	11		T26	4671		T27	17
all_pins[28]	transitions[0x1=>0x0]	919849	1			T22	5		T26	4706		T27	11
all_pins[29]	values[0x0]	2535429	1			T21	1		T22	53		T23	1
all_pins[29]	values[0x1]	1533295	1			T22	21		T26	8027		T27	28
all_pins[29]	transitions[0x0=>0x1]	919606	1			T22	17		T26	4692		T27	21
all_pins[29]	transitions[0x1=>0x0]	927039	1			T22	9		T26	4614		T27	18
all_pins[30]	values[0x0]	2532232	1			T21	1		T22	72		T23	1
all_pins[30]	values[0x1]	1536492	1			T22	2		T26	7959		T27	65
all_pins[30]	transitions[0x0=>0x1]	920432	1			T26	4652		T27	47		T28	10491
all_pins[30]	transitions[0x1=>0x0]	917235	1			T22	19		T26	4720		T27	10
all_pins[31]	values[0x0]	2526495	1			T21	1		T22	59		T23	1
all_pins[31]	values[0x1]	1542229	1			T22	15		T26	7883		T27	48
all_pins[31]	transitions[0x0=>0x1]	925111	1			T22	15		T26	4670		T27	25
all_pins[31]	transitions[0x1=>0x0]	919374	1			T22	2		T26	4746		T27	42