Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[1]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[2]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[3]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[4]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[5]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[6]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[7]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[8]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[9]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[10]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[11]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[12]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[13]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[14]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[15]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[16]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[17]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[18]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[19]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[20]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[21]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[22]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[23]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[24]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[25]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[26]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[27]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[28]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[29]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[30]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[31]	13508222	1			T21	631		T22	209		T23	204

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

262669133

1

T21

5553

T22

3257

T23

4583

auto[1]

169593971

1

T21

14639

T22

3431

T23

1945

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

346522522

1

T21

11427

T22

6266

T23

4001

auto[1]

85740582

1

T21

8765

T22

422

T23

2527

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

321062154

1

T21

11304

T22

5180

T23

3832

auto[1]

111200950

1

T21

8888

T22

1508

T23

2696

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5082854	1			T21	35		T22	84		T23	55
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3598677	1			T21	143		T22	52		T23	22
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1346114	1			T21	130		T22	4		T23	56
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1778335	1			T22	28		T23	38		T24	40
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	358998	1			T21	164		T22	27		T24	5
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1343244	1			T21	159		T22	14		T23	33
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5075132	1			T21	30		T22	54		T23	81
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3607490	1			T21	186		T22	92		T23	13
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1346000	1			T21	140		T22	5		T23	46
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1785175	1			T22	34		T23	30		T24	8
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	360357	1			T21	158		T22	11		T26	10528
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1334068	1			T21	117		T22	13		T23	34
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5079202	1			T21	45		T22	100		T23	75
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3606770	1			T21	180		T22	78		T23	16
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1348972	1			T21	134		T23	42		T24	12
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1779901	1			T22	20		T23	40		T24	32
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	361220	1			T21	114		T22	11		T24	5
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1332157	1			T21	158		T23	31		T24	3
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5079570	1			T21	34		T22	59		T23	61
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3603347	1			T21	180		T22	62		T23	18
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1345822	1			T21	110		T22	9		T23	30
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1785771	1			T22	32		T23	52		T24	31
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	355821	1			T21	141		T22	27		T24	4
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1337891	1			T21	166		T22	20		T23	43
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5072292	1			T21	42		T22	72		T23	76
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3611357	1			T21	207		T22	94		T23	21
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1352038	1			T21	138		T22	1		T23	35
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1780316	1			T22	10		T23	30		T24	32
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	359111	1			T21	122		T22	21		T24	4
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1333108	1			T21	122		T22	11		T23	42
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5077745	1			T21	39		T22	97		T23	64
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3606550	1			T21	203		T22	64		T23	15
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1349200	1			T21	121		T22	7		T23	49
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1784194	1			T22	21		T23	36		T24	19
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	358426	1			T21	140		T22	17		T24	2
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1332107	1			T21	128		T22	3		T23	40
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5074724	1			T21	35		T22	74		T23	48
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3607344	1			T21	199		T22	81		T23	24
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1351545	1			T21	157		T22	3		T23	40
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1783103	1			T22	17		T23	40		T24	25
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	356284	1			T21	108		T22	18		T24	1
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1335222	1			T21	132		T22	16		T23	52
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5083944	1			T21	43		T22	54		T23	58
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3597353	1			T21	155		T22	119		T23	21
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1348843	1			T21	162		T22	16		T23	34
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1788410	1			T22	10		T23	37		T24	26
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	357485	1			T21	144		T22	10		T24	4
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1332187	1			T21	127		T23	54		T24	18
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5077202	1			T21	42		T22	57		T23	50
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3612529	1			T21	176		T22	81		T23	21
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1349107	1			T21	122		T22	7		T23	46
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1774270	1			T22	20		T23	36		T24	1
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	359462	1			T21	161		T22	19		T26	10404
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1335652	1			T21	130		T22	25		T23	51
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5083765	1			T21	47		T22	61		T23	65
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3598119	1			T21	149		T22	101		T23	17
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1348128	1			T21	132		T22	3		T23	26
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1783602	1			T22	10		T23	54		T24	29
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	357250	1			T21	151		T22	22		T24	5
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1337358	1			T21	152		T22	12		T23	42
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5071670	1			T21	44		T22	63		T23	75
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3608526	1			T21	188		T22	118		T23	23
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1343374	1			T21	164		T23	30		T24	8
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1784333	1			T22	18		T23	50		T24	20
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	359540	1			T21	106		T22	7		T24	1
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1340779	1			T21	129		T22	3		T23	26
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5071241	1			T21	37		T22	77		T23	67
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3613034	1			T21	189		T22	73		T23	16
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1351562	1			T21	121		T22	10		T23	26
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1783722	1			T22	33		T23	48		T24	10
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	359059	1			T21	120		T22	13		T26	10249
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1329604	1			T21	164		T22	3		T23	47
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5078927	1			T21	48		T22	67		T23	72
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3607820	1			T21	138		T22	106		T23	18
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1351521	1			T21	145		T23	50		T25	78
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1781433	1			T22	12		T23	30		T24	54
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	357535	1			T21	164		T22	13		T24	4
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1330986	1			T21	136		T22	11		T23	34
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5076467	1			T21	41		T22	84		T23	53
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3608606	1			T21	169		T22	65		T23	15
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1347294	1			T21	162		T22	5		T23	44
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1777467	1			T22	28		T23	32		T24	37
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	359287	1			T21	109		T22	13		T24	10
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1339101	1			T21	150		T22	14		T23	60
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5089910	1			T21	51		T22	91		T23	71
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3594056	1			T21	197		T22	77		T23	20
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1351148	1			T21	147		T22	11		T23	30
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1776221	1			T22	25		T23	53		T24	38
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	358967	1			T21	134		T22	3		T26	10054
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1337920	1			T21	102		T22	2		T23	30
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5072992	1			T21	42		T22	71		T23	73
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3608975	1			T21	174		T22	93		T23	22
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1352645	1			T21	132		T22	4		T23	25
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1779262	1			T22	3		T23	52		T24	33
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	358819	1			T21	126		T22	15		T24	4
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1335529	1			T21	157		T22	23		T23	32
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5069711	1			T21	36		T22	68		T23	62
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3614634	1			T21	196		T22	99		T23	21
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1343527	1			T21	144		T23	38		T24	8
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1786646	1			T22	23		T23	45		T24	24
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	362374	1			T21	118		T22	11		T24	3
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1331330	1			T21	137		T22	8		T23	38
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5082687	1			T21	40		T22	74		T23	66
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3608966	1			T21	176		T22	86		T23	19
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1347234	1			T21	108		T22	4		T23	36
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1783914	1			T22	23		T23	38		T24	33
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	358258	1			T21	142		T22	13		T24	6
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1327163	1			T21	165		T22	9		T23	45
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5089328	1			T21	40		T22	151		T23	70
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3600714	1			T21	186		T22	37		T23	23
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1343404	1			T21	150		T22	4		T23	24
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1785655	1			T22	14		T23	55		T24	28
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	359137	1			T21	124		T22	3		T24	4
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1329984	1			T21	131		T23	32		T24	2
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5083845	1			T21	44		T22	69		T23	82
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3611415	1			T21	164		T22	65		T23	18
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1344548	1			T21	128		T23	16		T24	6
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1778089	1			T22	38		T23	48		T24	43
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	361999	1			T21	163		T22	28		T24	3
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1328326	1			T21	132		T22	9		T23	40
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5084434	1			T21	40		T22	81		T23	69
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3605937	1			T21	182		T22	91		T23	20
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1345198	1			T21	122		T22	7		T23	24
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1786222	1			T22	11		T23	46		T24	25
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	359301	1			T21	149		T22	14		T26	9803
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1327130	1			T21	138		T22	5		T23	45
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5068991	1			T21	36		T22	89		T23	48
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3616275	1			T21	198		T22	74		T23	17
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1343580	1			T21	106		T22	3		T23	40
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1786639	1			T22	14		T23	55		T24	8
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	362041	1			T21	133		T22	27		T24	1
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1330696	1			T21	158		T22	2		T23	44
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5081075	1			T21	47		T22	76		T23	58
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3609592	1			T21	181		T22	80		T23	25
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1344029	1			T21	132		T23	30		T24	2
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1784932	1			T22	14		T23	64		T24	38
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	357536	1			T21	130		T22	26		T24	4
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1331058	1			T21	141		T22	13		T23	27
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5076737	1			T21	41		T22	73		T23	54
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3610482	1			T21	178		T22	102		T23	21
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1344632	1			T21	136		T22	4		T23	42
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1786028	1			T22	14		T23	37		T24	11
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	360121	1			T21	132		T22	14		T24	3
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1330222	1			T21	144		T22	2		T23	50
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5083474	1			T21	41		T22	82		T23	54
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3603576	1			T21	173		T22	47		T23	23
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1344121	1			T21	130		T23	32		T24	2
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1781921	1			T22	33		T23	43		T24	33
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	360616	1			T21	133		T22	32		T24	5
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1334514	1			T21	154		T22	15		T23	52
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5085088	1			T21	43		T22	75		T23	63
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3603768	1			T21	188		T22	105		T23	15
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1342506	1			T21	144		T22	12		T23	58
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1782330	1			T22	16		T23	26		T24	19
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	360928	1			T21	136		T22	1		T24	3
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1333602	1			T21	120		T23	42		T24	4
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5078389	1			T21	31		T22	108		T23	60
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3617257	1			T21	183		T22	63		T23	17
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1343134	1			T21	118		T22	5		T23	52
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1783014	1			T22	24		T23	30		T24	42
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	357367	1			T21	149		T22	8		T24	5
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1329061	1			T21	150		T22	1		T23	45
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5081810	1			T21	48		T22	82		T23	60
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3607481	1			T21	179		T22	68		T23	21
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1346631	1			T21	140		T22	7		T23	44
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1785210	1			T22	8		T23	38		T24	24
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	357560	1			T21	128		T22	38		T24	5
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1329530	1			T21	136		T22	6		T23	41
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5083287	1			T21	41		T22	44		T23	49
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3605538	1			T21	165		T22	100		T23	22
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1343554	1			T21	122		T22	3		T23	26
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1784213	1			T22	27		T23	72		T24	29
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	361053	1			T21	156		T22	33		T24	5
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1330577	1			T21	147		T22	2		T23	35
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5068720	1			T21	40		T22	85		T23	64
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3617684	1			T21	170		T22	62		T23	17
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1339796	1			T21	117		T22	5		T23	56
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1788463	1			T22	44		T23	31		T24	42
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	359586	1			T21	140		T22	11		T24	3
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1333973	1			T21	164		T22	2		T23	36
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5080643	1			T21	42		T22	72		T23	57
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3612119	1			T21	222		T22	85		T23	20
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1345550	1			T21	127		T22	4		T23	31
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1782437	1			T22	10		T23	50		T24	26
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	359317	1			T21	134		T22	26		T24	3
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1328156	1			T21	106		T22	12		T23	46
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5086887	1			T21	39		T22	57		T23	50
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3607814	1			T21	177		T22	64		T23	19
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1340849	1			T21	108		T22	2		T23	44
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1779556	1			T22	27		T23	35		T24	16
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	360375	1			T21	143		T22	38		T24	2
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1332741	1			T21	164		T22	21		T23	56

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal