Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[1]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[2]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[3]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[4]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[5]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[6]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[7]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[8]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[9]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[10]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[11]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[12]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[13]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[14]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[15]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[16]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[17]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[18]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[19]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[20]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[21]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[22]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[23]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[24]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[25]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[26]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[27]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[28]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[29]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[30]	13508222	1			T21	631		T22	209		T23	204
bins_for_gpio_bits[31]	13508222	1			T21	631		T22	209		T23	204

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

262669133

1

T21

5553

T22

3257

T23

4583

auto[1]

169593971

1

T21

14639

T22

3431

T23

1945

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

262658742

1

T21

5560

T22

3256

T23

4572

auto[1]

169604362

1

T21

14632

T22

3432

T23

1956

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7967717	1			T21	140		T22	116		T23	141
bins_for_gpio_bits[0]	auto[0]	auto[1]	239250	1			T21	25		T23	7		T24	1
bins_for_gpio_bits[0]	auto[1]	auto[0]	239586	1			T21	25		T23	8		T24	1
bins_for_gpio_bits[0]	auto[1]	auto[1]	5061669	1			T21	441		T22	93		T23	48
bins_for_gpio_bits[1]	auto[0]	auto[0]	7966782	1			T21	131		T22	92		T23	146
bins_for_gpio_bits[1]	auto[0]	auto[1]	239190	1			T21	39		T23	11		T24	1
bins_for_gpio_bits[1]	auto[1]	auto[0]	239525	1			T21	39		T22	1		T23	11
bins_for_gpio_bits[1]	auto[1]	auto[1]	5062725	1			T21	422		T22	116		T23	36
bins_for_gpio_bits[2]	auto[0]	auto[0]	7968857	1			T21	146		T22	120		T23	147
bins_for_gpio_bits[2]	auto[0]	auto[1]	238889	1			T21	33		T23	9		T24	1
bins_for_gpio_bits[2]	auto[1]	auto[0]	239218	1			T21	33		T23	10		T24	1
bins_for_gpio_bits[2]	auto[1]	auto[1]	5061258	1			T21	419		T22	89		T23	38
bins_for_gpio_bits[3]	auto[0]	auto[0]	7971687	1			T21	116		T22	100		T23	133
bins_for_gpio_bits[3]	auto[0]	auto[1]	239210	1			T21	28		T23	9		T24	3
bins_for_gpio_bits[3]	auto[1]	auto[0]	239476	1			T21	28		T23	10		T24	3
bins_for_gpio_bits[3]	auto[1]	auto[1]	5057849	1			T21	459		T22	109		T23	52
bins_for_gpio_bits[4]	auto[0]	auto[0]	7965750	1			T21	147		T22	83		T23	130
bins_for_gpio_bits[4]	auto[0]	auto[1]	238548	1			T21	33		T23	11		T24	2
bins_for_gpio_bits[4]	auto[1]	auto[0]	238896	1			T21	33		T23	11		T24	2
bins_for_gpio_bits[4]	auto[1]	auto[1]	5065028	1			T21	418		T22	126		T23	52
bins_for_gpio_bits[5]	auto[0]	auto[0]	7971926	1			T21	129		T22	125		T23	139
bins_for_gpio_bits[5]	auto[0]	auto[1]	238933	1			T21	32		T23	10		T24	1
bins_for_gpio_bits[5]	auto[1]	auto[0]	239213	1			T21	31		T23	10		T24	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	5058150	1			T21	439		T22	84		T23	45
bins_for_gpio_bits[6]	auto[0]	auto[0]	7970278	1			T21	156		T22	94		T23	116
bins_for_gpio_bits[6]	auto[0]	auto[1]	238745	1			T21	37		T23	12		T24	1
bins_for_gpio_bits[6]	auto[1]	auto[0]	239094	1			T21	36		T23	12		T24	1
bins_for_gpio_bits[6]	auto[1]	auto[1]	5060105	1			T21	402		T22	115		T23	64
bins_for_gpio_bits[7]	auto[0]	auto[0]	7981911	1			T21	169		T22	79		T23	117
bins_for_gpio_bits[7]	auto[0]	auto[1]	238966	1			T21	36		T22	1		T23	12
bins_for_gpio_bits[7]	auto[1]	auto[0]	239286	1			T21	36		T22	1		T23	12
bins_for_gpio_bits[7]	auto[1]	auto[1]	5048059	1			T21	390		T22	128		T23	63
bins_for_gpio_bits[8]	auto[0]	auto[0]	7961577	1			T21	135		T22	84		T23	120
bins_for_gpio_bits[8]	auto[0]	auto[1]	238655	1			T21	29		T23	11		T25	16
bins_for_gpio_bits[8]	auto[1]	auto[0]	239002	1			T21	29		T23	12		T25	16
bins_for_gpio_bits[8]	auto[1]	auto[1]	5068988	1			T21	438		T22	125		T23	61
bins_for_gpio_bits[9]	auto[0]	auto[0]	7975915	1			T21	148		T22	74		T23	137
bins_for_gpio_bits[9]	auto[0]	auto[1]	239262	1			T21	31		T23	8		T24	1
bins_for_gpio_bits[9]	auto[1]	auto[0]	239580	1			T21	31		T23	8		T24	1
bins_for_gpio_bits[9]	auto[1]	auto[1]	5053465	1			T21	421		T22	135		T23	51
bins_for_gpio_bits[10]	auto[0]	auto[0]	7959567	1			T21	175		T22	81		T23	145
bins_for_gpio_bits[10]	auto[0]	auto[1]	239471	1			T21	33		T23	10		T24	1
bins_for_gpio_bits[10]	auto[1]	auto[0]	239810	1			T21	33		T23	10		T24	1
bins_for_gpio_bits[10]	auto[1]	auto[1]	5069374	1			T21	390		T22	128		T23	39
bins_for_gpio_bits[11]	auto[0]	auto[0]	7967543	1			T21	126		T22	120		T23	129
bins_for_gpio_bits[11]	auto[0]	auto[1]	238613	1			T21	33		T23	11		T25	11
bins_for_gpio_bits[11]	auto[1]	auto[0]	238982	1			T21	32		T23	12		T25	11
bins_for_gpio_bits[11]	auto[1]	auto[1]	5063084	1			T21	440		T22	89		T23	52
bins_for_gpio_bits[12]	auto[0]	auto[0]	7972529	1			T21	163		T22	79		T23	142
bins_for_gpio_bits[12]	auto[0]	auto[1]	239061	1			T21	31		T23	10		T24	4
bins_for_gpio_bits[12]	auto[1]	auto[0]	239352	1			T21	30		T23	10		T24	4
bins_for_gpio_bits[12]	auto[1]	auto[1]	5057280	1			T21	407		T22	130		T23	42
bins_for_gpio_bits[13]	auto[0]	auto[0]	7961628	1			T21	166		T22	117		T23	119
bins_for_gpio_bits[13]	auto[0]	auto[1]	239299	1			T21	37		T23	10		T24	3
bins_for_gpio_bits[13]	auto[1]	auto[0]	239600	1			T21	37		T23	10		T24	3
bins_for_gpio_bits[13]	auto[1]	auto[1]	5067695	1			T21	391		T22	92		T23	65
bins_for_gpio_bits[14]	auto[0]	auto[0]	7977281	1			T21	165		T22	127		T23	146
bins_for_gpio_bits[14]	auto[0]	auto[1]	239674	1			T21	34		T23	8		T25	14
bins_for_gpio_bits[14]	auto[1]	auto[0]	239998	1			T21	33		T23	8		T25	14
bins_for_gpio_bits[14]	auto[1]	auto[1]	5051269	1			T21	399		T22	82		T23	42
bins_for_gpio_bits[15]	auto[0]	auto[0]	7965477	1			T21	139		T22	77		T23	141
bins_for_gpio_bits[15]	auto[0]	auto[1]	239087	1			T21	35		T22	1		T23	9
bins_for_gpio_bits[15]	auto[1]	auto[0]	239422	1			T21	35		T22	1		T23	9
bins_for_gpio_bits[15]	auto[1]	auto[1]	5064236	1			T21	422		T22	130		T23	45
bins_for_gpio_bits[16]	auto[0]	auto[0]	7960712	1			T21	142		T22	91		T23	136
bins_for_gpio_bits[16]	auto[0]	auto[1]	238863	1			T21	38		T23	9		T24	2
bins_for_gpio_bits[16]	auto[1]	auto[0]	239172	1			T21	38		T23	9		T24	2
bins_for_gpio_bits[16]	auto[1]	auto[1]	5069475	1			T21	413		T22	118		T23	50
bins_for_gpio_bits[17]	auto[0]	auto[0]	7975021	1			T21	120		T22	101		T23	127
bins_for_gpio_bits[17]	auto[0]	auto[1]	238518	1			T21	28		T23	12		T24	2
bins_for_gpio_bits[17]	auto[1]	auto[0]	238814	1			T21	28		T23	13		T24	2
bins_for_gpio_bits[17]	auto[1]	auto[1]	5055869	1			T21	455		T22	108		T23	52
bins_for_gpio_bits[18]	auto[0]	auto[0]	7978886	1			T21	157		T22	169		T23	143
bins_for_gpio_bits[18]	auto[0]	auto[1]	239198	1			T21	33		T23	6		T24	1
bins_for_gpio_bits[18]	auto[1]	auto[0]	239501	1			T21	33		T23	6		T24	1
bins_for_gpio_bits[18]	auto[1]	auto[1]	5050637	1			T21	408		T22	40		T23	49
bins_for_gpio_bits[19]	auto[0]	auto[0]	7967466	1			T21	139		T22	107		T23	136
bins_for_gpio_bits[19]	auto[0]	auto[1]	238673	1			T21	33		T23	10		T24	1
bins_for_gpio_bits[19]	auto[1]	auto[0]	239016	1			T21	33		T23	10		T24	1
bins_for_gpio_bits[19]	auto[1]	auto[1]	5063067	1			T21	426		T22	102		T23	48
bins_for_gpio_bits[20]	auto[0]	auto[0]	7976536	1			T21	123		T22	99		T23	128
bins_for_gpio_bits[20]	auto[0]	auto[1]	238982	1			T21	39		T23	10		T24	1
bins_for_gpio_bits[20]	auto[1]	auto[0]	239318	1			T21	39		T23	11		T24	1
bins_for_gpio_bits[20]	auto[1]	auto[1]	5053386	1			T21	430		T22	110		T23	55
bins_for_gpio_bits[21]	auto[0]	auto[0]	7959364	1			T21	111		T22	106		T23	133
bins_for_gpio_bits[21]	auto[0]	auto[1]	239540	1			T21	31		T23	10		T24	1
bins_for_gpio_bits[21]	auto[1]	auto[0]	239846	1			T21	31		T23	10		T24	1
bins_for_gpio_bits[21]	auto[1]	auto[1]	5069472	1			T21	458		T22	103		T23	51
bins_for_gpio_bits[22]	auto[0]	auto[0]	7970905	1			T21	145		T22	90		T23	143
bins_for_gpio_bits[22]	auto[0]	auto[1]	238795	1			T21	34		T23	8		T24	1
bins_for_gpio_bits[22]	auto[1]	auto[0]	239131	1			T21	34		T23	9		T24	1
bins_for_gpio_bits[22]	auto[1]	auto[1]	5059391	1			T21	418		T22	119		T23	44
bins_for_gpio_bits[23]	auto[0]	auto[0]	7968196	1			T21	143		T22	91		T23	120
bins_for_gpio_bits[23]	auto[0]	auto[1]	238846	1			T21	34		T23	13		T25	14
bins_for_gpio_bits[23]	auto[1]	auto[0]	239201	1			T21	34		T23	13		T25	15
bins_for_gpio_bits[23]	auto[1]	auto[1]	5061979	1			T21	420		T22	118		T23	58
bins_for_gpio_bits[24]	auto[0]	auto[0]	7969814	1			T21	139		T22	115		T23	120
bins_for_gpio_bits[24]	auto[0]	auto[1]	239370	1			T21	32		T23	9		T24	3
bins_for_gpio_bits[24]	auto[1]	auto[0]	239702	1			T21	32		T23	9		T24	3
bins_for_gpio_bits[24]	auto[1]	auto[1]	5059336	1			T21	428		T22	94		T23	66
bins_for_gpio_bits[25]	auto[0]	auto[0]	7970469	1			T21	155		T22	103		T23	135
bins_for_gpio_bits[25]	auto[0]	auto[1]	239123	1			T21	32		T23	12		T24	2
bins_for_gpio_bits[25]	auto[1]	auto[0]	239455	1			T21	32		T23	12		T24	2
bins_for_gpio_bits[25]	auto[1]	auto[1]	5059175	1			T21	412		T22	106		T23	45
bins_for_gpio_bits[26]	auto[0]	auto[0]	7965320	1			T21	118		T22	137		T23	130
bins_for_gpio_bits[26]	auto[0]	auto[1]	238889	1			T21	31		T23	11		T24	1
bins_for_gpio_bits[26]	auto[1]	auto[0]	239217	1			T21	31		T23	12		T24	1
bins_for_gpio_bits[26]	auto[1]	auto[1]	5064796	1			T21	451		T22	72		T23	51
bins_for_gpio_bits[27]	auto[0]	auto[0]	7974440	1			T21	153		T22	97		T23	131
bins_for_gpio_bits[27]	auto[0]	auto[1]	238865	1			T21	35		T23	10		T24	3
bins_for_gpio_bits[27]	auto[1]	auto[0]	239211	1			T21	35		T23	11		T24	3
bins_for_gpio_bits[27]	auto[1]	auto[1]	5055706	1			T21	408		T22	112		T23	52
bins_for_gpio_bits[28]	auto[0]	auto[0]	7971985	1			T21	130		T22	74		T23	138
bins_for_gpio_bits[28]	auto[0]	auto[1]	238764	1			T21	33		T23	8		T25	18
bins_for_gpio_bits[28]	auto[1]	auto[0]	239069	1			T21	33		T23	9		T25	18
bins_for_gpio_bits[28]	auto[1]	auto[1]	5058404	1			T21	435		T22	135		T23	49
bins_for_gpio_bits[29]	auto[0]	auto[0]	7956805	1			T21	124		T22	134		T23	143
bins_for_gpio_bits[29]	auto[0]	auto[1]	239842	1			T21	34		T23	8		T24	1
bins_for_gpio_bits[29]	auto[1]	auto[0]	240174	1			T21	33		T23	8		T24	1
bins_for_gpio_bits[29]	auto[1]	auto[1]	5071401	1			T21	440		T22	75		T23	45
bins_for_gpio_bits[30]	auto[0]	auto[0]	7969618	1			T21	139		T22	86		T23	128
bins_for_gpio_bits[30]	auto[0]	auto[1]	238689	1			T21	31		T23	10		T24	1
bins_for_gpio_bits[30]	auto[1]	auto[0]	239012	1			T21	30		T23	10		T24	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	5060903	1			T21	431		T22	123		T23	56
bins_for_gpio_bits[31]	auto[0]	auto[0]	7967782	1			T21	118		T22	86		T23	118
bins_for_gpio_bits[31]	auto[0]	auto[1]	239188	1			T21	29		T23	11		T25	17
bins_for_gpio_bits[31]	auto[1]	auto[0]	239510	1			T21	29		T23	11		T25	18
bins_for_gpio_bits[31]	auto[1]	auto[1]	5061742	1			T21	455		T22	123		T23	64