Unified Coverage Report :: Group Instance : intr_event_falling_pin26

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7875592

1

T21

357

T22

86

T23

122

auto[1]

5804563

1

T22

55

T26

29017

T27

110

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12945311

1

T21

357

T22

141

T23

122

auto[1]

734844

1

T26

3473

T27

7

T28

8295

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7899225

1

T21

357

T22

123

T23

122

auto[1]

5780930

1

T22

18

T26

29390

T27

208

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2519429

1

T22

7

T26

12937

T27

124

auto[1]

auto[0]

auto[1]

366395

1

T26

1815

T27

1

T28

3994

auto[1]

auto[1]

auto[0]

2526657

1

T22

11

T26

12980

T27

77

auto[1]

auto[1]

auto[1]

368449

1

T26

1658

T27

6

T28

4301

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7925302

1

T21

357

T22

78

T23

122

auto[1]

5754853

1

T22

63

T26

29592

T27

137

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12951216

1

T21

357

T22

141

T23

122

auto[1]

728939

1

T26

3528

T27

4

T28

8259

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7946540

1

T21

357

T22

115

T23

122

auto[1]

5733615

1

T22

26

T26

28973

T27

87

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2512876

1

T22

16

T26

11625

T27

35

auto[1]

auto[0]

auto[1]

366167

1

T26

1561

T27

3

T28

4116

auto[1]

auto[1]

auto[0]

2491800

1

T22

10

T26

13820

T27

48

auto[1]

auto[1]

auto[1]

362772

1

T26

1967

T27

1

T28

4143

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7914613

1

T21

357

T22

112

T23

122

auto[1]

5765542

1

T22

29

T26

28815

T27

97

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12938543

1

T21

357

T22

141

T23

122

auto[1]

741612

1

T26

3253

T27

5

T28

8816

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7867940

1

T21

357

T22

109

T23

122

auto[1]

5812215

1

T22

32

T26

27439

T27

101

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2539385

1

T22

26

T26

12171

T27

59

auto[1]

auto[0]

auto[1]

371771

1

T26

1608

T27

5

T28

4561

auto[1]

auto[1]

auto[0]

2531218

1

T22

6

T26

12015

T27

37

auto[1]

auto[1]

auto[1]

369841

1

T26

1645

T28

4255

T29

109

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7918995

1

T21

357

T22

110

T23

122

auto[1]

5761160

1

T22

31

T26

28926

T27

171

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12946625

1

T21

357

T22

140

T23

122

auto[1]

733530

1

T22

1

T26

3398

T27

4

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7913604

1

T21

357

T22

103

T23

122

auto[1]

5766551

1

T22

38

T26

27835

T27

185

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2523903

1

T22

20

T26

12318

T27

87

auto[1]

auto[0]

auto[1]

367561

1

T26

1709

T27

2

T28

4113

auto[1]

auto[1]

auto[0]

2509118

1

T22

17

T26

12119

T27

94

auto[1]

auto[1]

auto[1]

365969

1

T22

1

T26

1689

T27

2

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7900167

1

T21

357

T22

105

T23

122

auto[1]

5779988

1

T22

36

T26

29139

T27

142

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12948034

1

T21

357

T22

138

T23

122

auto[1]

732121

1

T22

3

T26

3910

T27

6

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7924812

1

T21

357

T22

95

T23

122

auto[1]

5755343

1

T22

46

T26

30391

T27

135

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2509205

1

T22

29

T26

13097

T27

64

auto[1]

auto[0]

auto[1]

364863

1

T22

2

T26

1966

T27

2

auto[1]

auto[1]

auto[0]

2514017

1

T22

14

T26

13384

T27

65

auto[1]

auto[1]

auto[1]

367258

1

T22

1

T26

1944

T27

4

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7913261

1

T21

357

T22

110

T23

122

auto[1]

5766894

1

T22

31

T26

27607

T27

165

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12950141

1

T21

357

T22

140

T23

122

auto[1]

730014

1

T22

1

T26

3461

T27

4

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7942583

1

T21

357

T22

89

T23

122

auto[1]

5737572

1

T22

52

T26

28613

T27

164

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2513024

1

T22

37

T26

12819

T27

57

auto[1]

auto[0]

auto[1]

366502

1

T22

1

T26

1798

T27

2

auto[1]

auto[1]

auto[0]

2494534

1

T22

14

T26

12333

T27

103

auto[1]

auto[1]

auto[1]

363512

1

T26

1663

T27

2

T28

4380

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7899570

1

T21

357

T22

122

T23

122

auto[1]

5780585

1

T22

19

T26

28493

T27

125

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12944169

1

T21

357

T22

141

T23

122

auto[1]

735986

1

T26

3580

T27

2

T28

8527

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7905031

1

T21

357

T22

104

T23

122

auto[1]

5775124

1

T22

37

T26

29156

T27

102

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2531582

1

T22

24

T26

12587

T27

63

auto[1]

auto[0]

auto[1]

369668

1

T26

1698

T27

2

T28

4286

auto[1]

auto[1]

auto[0]

2507556

1

T22

13

T26

12989

T27

37

auto[1]

auto[1]

auto[1]

366318

1

T26

1882

T28

4241

T29

116

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7905320

1

T21

357

T22

94

T23

122

auto[1]

5774835

1

T22

47

T26

29250

T27

186

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12946094

1

T21

357

T22

139

T23

122

auto[1]

734061

1

T22

2

T26

3608

T27

6

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7907871

1

T21

357

T22

69

T23

122

auto[1]

5772284

1

T22

72

T26

29155

T27

131

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2518498

1

T22

33

T26

12794

T27

43

auto[1]

auto[0]

auto[1]

367048

1

T26

1828

T28

4582

T29

86

auto[1]

auto[1]

auto[0]

2519725

1

T22

37

T26

12753

T27

82

auto[1]

auto[1]

auto[1]

367013

1

T22

2

T26

1780

T27

6

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7896413

1

T21

357

T22

107

T23

122

auto[1]

5783742

1

T22

34

T26

29615

T27

159

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12947902

1

T21

357

T22

138

T23

122

auto[1]

732253

1

T22

3

T26

3654

T27

5

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7917010

1

T21

357

T22

92

T23

122

auto[1]

5763145

1

T22

49

T26

28942

T27

122

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2509832

1

T22

34

T26

12598

T27

54

auto[1]

auto[0]

auto[1]

365828

1

T22

2

T26

1856

T27

3

auto[1]

auto[1]

auto[0]

2521060

1

T22

12

T26

12690

T27

63

auto[1]

auto[1]

auto[1]

366425

1

T22

1

T26

1798

T27

2

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7870281

1

T21

357

T22

94

T23

122

auto[1]

5809874

1

T22

47

T26

30173

T27

151

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12949036

1

T21

357

T22

140

T23

122

auto[1]

731119

1

T22

1

T26

3472

T27

2

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7926451

1

T21

357

T22

104

T23

122

auto[1]

5753704

1

T22

37

T26

28285

T27

117

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2487261

1

T22

23

T26

11854

T27

62

auto[1]

auto[0]

auto[1]

361561

1

T26

1671

T28

4171

T29

71

auto[1]

auto[1]

auto[0]

2535324

1

T22

13

T26

12959

T27

53

auto[1]

auto[1]

auto[1]

369558

1

T22

1

T26

1801

T27

2

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7911404

1

T21

357

T22

112

T23

122

auto[1]

5768751

1

T22

29

T26

29738

T27

145

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12943305

1

T21

357

T22

141

T23

122

auto[1]

736850

1

T26

3647

T27

8

T28

8802

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7906606

1

T21

357

T22

110

T23

122

auto[1]

5773549

1

T22

31

T26

29170

T27

181

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2517913

1

T22

29

T26

12100

T27

72

auto[1]

auto[0]

auto[1]

368127

1

T26

1674

T27

4

T28

4543

auto[1]

auto[1]

auto[0]

2518786

1

T22

2

T26

13423

T27

101

auto[1]

auto[1]

auto[1]

368723

1

T26

1973

T27

4

T28

4259

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7905960

1

T21

357

T22

93

T23

122

auto[1]

5774195

1

T22

48

T26

28695

T27

115

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12946723

1

T21

357

T22

140

T23

122

auto[1]

733432

1

T22

1

T26

3225

T27

6

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7918417

1

T21

357

T22

95

T23

122

auto[1]

5761738

1

T22

46

T26

26304

T27

109

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2502033

1

T22

40

T26

12238

T27

66

auto[1]

auto[0]

auto[1]

364806

1

T22

1

T26

1748

T27

5

auto[1]

auto[1]

auto[0]

2526273

1

T22

5

T26

10841

T27

37

auto[1]

auto[1]

auto[1]

368626

1

T26

1477

T27

1

T28

4510

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7918379

1

T21

357

T22

87

T23

122

auto[1]

5761776

1

T22

54

T26

28941

T27

203

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12944554

1

T21

357

T22

138

T23

122

auto[1]

735601

1

T22

3

T26

3449

T27

5

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7916724

1

T21

357

T22

75

T23

122

auto[1]

5763431

1

T22

66

T26

27667

T27

180

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2516827

1

T22

25

T26

11601

T27

67

auto[1]

auto[0]

auto[1]

367796

1

T22

1

T26

1616

T27

3

auto[1]

auto[1]

auto[0]

2511003

1

T22

38

T26

12617

T27

108

auto[1]

auto[1]

auto[1]

367805

1

T22

2

T26

1833

T27

2

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7886415

1

T21

357

T22

90

T23

122

auto[1]

5793740

1

T22

51

T26

28318

T27

162

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12942920

1

T21

357

T22

139

T23

122

auto[1]

737235

1

T22

2

T26

3421

T27

5

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7891980

1

T21

357

T22

94

T23

122

auto[1]

5788175

1

T22

47

T26

28100

T27

92

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2520353

1

T22

27

T26

12515

T27

35

auto[1]

auto[0]

auto[1]

367660

1

T22

1

T26

1703

T27

1

auto[1]

auto[1]

auto[0]

2530587

1

T22

18

T26

12164

T27

52

auto[1]

auto[1]

auto[1]

369575

1

T22

1

T26

1718

T27

4

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7876663

1

T21

357

T22

76

T23

122

auto[1]

5803492

1

T22

65

T26

28856

T27

121

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12945868

1

T21

357

T22

140

T23

122

auto[1]

734287

1

T22

1

T26

3648

T27

5

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7912943

1

T21

357

T22

122

T23

122

auto[1]

5767212

1

T22

19

T26

29133

T27

112

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2510327

1

T22

9

T26

13037

T27

57

auto[1]

auto[0]

auto[1]

366075

1

T22

1

T26

1889

T27

4

auto[1]

auto[1]

auto[0]

2522598

1

T22

9

T26

12448

T27

50

auto[1]

auto[1]

auto[1]

368212

1

T26

1759

T27

1

T28

4564

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7906709

1

T21

357

T22

97

T23

122

auto[1]

5773446

1

T22

44

T26

28665

T27

124

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12948736

1

T21

357

T22

139

T23

122

auto[1]

731419

1

T22

2

T26

3505

T27

7

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7922822

1

T21

357

T22

97

T23

122

auto[1]

5757333

1

T22

44

T26

28099

T27

220

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2530316

1

T22

28

T26

12531

T27

108

auto[1]

auto[0]

auto[1]

368855

1

T22

2

T26

1831

T27

4

auto[1]

auto[1]

auto[0]

2495598

1

T22

14

T26

12063

T27

105

auto[1]

auto[1]

auto[1]

362564

1

T26

1674

T27

3

T28

3973

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7887222

1

T21

357

T22

105

T23

122

auto[1]

5792933

1

T22

36

T26

28176

T27

172

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12945120

1

T21

357

T22

138

T23

122

auto[1]

735035

1

T22

3

T26

3632

T27

7

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7905251

1

T21

357

T22

95

T23

122

auto[1]

5774904

1

T22

46

T26

29747

T27

132

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2519128

1

T22

16

T26

13302

T27

60

auto[1]

auto[0]

auto[1]

367645

1

T22

1

T26

1888

T27

2

auto[1]

auto[1]

auto[0]

2520741

1

T22

27

T26

12813

T27

65

auto[1]

auto[1]

auto[1]

367390

1

T22

2

T26

1744

T27

5

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7913556

1

T21

357

T22

84

T23

122

auto[1]

5766599

1

T22

57

T26

29498

T27

131

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12943727

1

T21

357

T22

139

T23

122

auto[1]

736428

1

T22

2

T26

3573

T27

6

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7903083

1

T21

357

T22

73

T23

122

auto[1]

5777072

1

T22

68

T26

29033

T27

155

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2524794

1

T22

27

T26

11801

T27

67

auto[1]

auto[0]

auto[1]

369373

1

T22

1

T26

1639

T27

4

auto[1]

auto[1]

auto[0]

2515850

1

T22

39

T26

13659

T27

82

auto[1]

auto[1]

auto[1]

367055

1

T22

1

T26

1934

T27

2

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7876573

1

T21

357

T22

89

T23

122

auto[1]

5803582

1

T22

52

T26

29478

T27

167

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12940133

1

T21

357

T22

141

T23

122

auto[1]

740022

1

T26

3529

T27

3

T28

8411

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7880782

1

T21

357

T22

114

T23

122

auto[1]

5799373

1

T22

27

T26

28148

T27

125

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2508649

1

T22

13

T26

11763

T27

39

auto[1]

auto[0]

auto[1]

366198

1

T26

1717

T28

4381

T29

136

auto[1]

auto[1]

auto[0]

2550702

1

T22

14

T26

12856

T27

83

auto[1]

auto[1]

auto[1]

373824

1

T26

1812

T27

3

T28

4030

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7887050

1

T21

357

T22

121

T23

122

auto[1]

5793105

1

T22

20

T26

28455

T27

111

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12941239

1

T21

357

T22

140

T23

122

auto[1]

738916

1

T22

1

T26

3317

T27

3