Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7918230 |
1 |
|
|
T21 |
357 |
|
T22 |
120 |
|
T23 |
122 |
| auto[1] |
5761925 |
1 |
|
|
T22 |
21 |
|
T26 |
27569 |
|
T27 |
192 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12940013 |
1 |
|
|
T21 |
357 |
|
T22 |
138 |
|
T23 |
122 |
| auto[1] |
740142 |
1 |
|
|
T22 |
3 |
|
T26 |
3477 |
|
T27 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7879106 |
1 |
|
|
T21 |
357 |
|
T22 |
75 |
|
T23 |
122 |
| auto[1] |
5801049 |
1 |
|
|
T22 |
66 |
|
T26 |
28351 |
|
T27 |
188 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2537242 |
1 |
|
|
T22 |
53 |
|
T26 |
12730 |
|
T27 |
62 |
| auto[1] |
auto[0] |
auto[1] |
371704 |
1 |
|
|
T22 |
2 |
|
T26 |
1857 |
|
T27 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2523665 |
1 |
|
|
T22 |
10 |
|
T26 |
12144 |
|
T27 |
117 |
| auto[1] |
auto[1] |
auto[1] |
368438 |
1 |
|
|
T22 |
1 |
|
T26 |
1620 |
|
T27 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |