Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7913854 |
1 |
|
|
T21 |
357 |
|
T22 |
97 |
|
T23 |
122 |
| auto[1] |
5766301 |
1 |
|
|
T22 |
44 |
|
T26 |
30013 |
|
T27 |
95 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12943090 |
1 |
|
|
T21 |
357 |
|
T22 |
140 |
|
T23 |
122 |
| auto[1] |
737065 |
1 |
|
|
T22 |
1 |
|
T26 |
3472 |
|
T27 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7895028 |
1 |
|
|
T21 |
357 |
|
T22 |
86 |
|
T23 |
122 |
| auto[1] |
5785127 |
1 |
|
|
T22 |
55 |
|
T26 |
29043 |
|
T27 |
203 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2540091 |
1 |
|
|
T22 |
25 |
|
T26 |
12570 |
|
T27 |
127 |
| auto[1] |
auto[0] |
auto[1] |
371205 |
1 |
|
|
T22 |
1 |
|
T26 |
1615 |
|
T27 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2507971 |
1 |
|
|
T22 |
29 |
|
T26 |
13001 |
|
T27 |
70 |
| auto[1] |
auto[1] |
auto[1] |
365860 |
1 |
|
|
T26 |
1857 |
|
T27 |
1 |
|
T28 |
4204 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |