Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7875592 |
1 |
|
|
T21 |
357 |
|
T22 |
86 |
|
T23 |
122 |
| auto[1] |
5804563 |
1 |
|
|
T22 |
55 |
|
T26 |
29017 |
|
T27 |
110 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11348121 |
1 |
|
|
T21 |
357 |
|
T22 |
140 |
|
T23 |
122 |
| auto[1] |
2332034 |
1 |
|
|
T22 |
1 |
|
T26 |
16591 |
|
T27 |
29 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7905549 |
1 |
|
|
T21 |
357 |
|
T22 |
104 |
|
T23 |
122 |
| auto[1] |
5774606 |
1 |
|
|
T22 |
37 |
|
T26 |
27026 |
|
T27 |
96 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1712912 |
1 |
|
|
T22 |
16 |
|
T26 |
5001 |
|
T27 |
38 |
| auto[1] |
auto[0] |
auto[1] |
1160821 |
1 |
|
|
T26 |
8091 |
|
T27 |
7 |
|
T28 |
12797 |
| auto[1] |
auto[1] |
auto[0] |
1729660 |
1 |
|
|
T22 |
20 |
|
T26 |
5434 |
|
T27 |
29 |
| auto[1] |
auto[1] |
auto[1] |
1171213 |
1 |
|
|
T22 |
1 |
|
T26 |
8500 |
|
T27 |
22 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |