Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7925302 |
1 |
|
|
T21 |
357 |
|
T22 |
78 |
|
T23 |
122 |
| auto[1] |
5754853 |
1 |
|
|
T22 |
63 |
|
T26 |
29592 |
|
T27 |
137 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11355282 |
1 |
|
|
T21 |
357 |
|
T22 |
110 |
|
T23 |
122 |
| auto[1] |
2324873 |
1 |
|
|
T22 |
31 |
|
T26 |
18075 |
|
T27 |
31 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7926872 |
1 |
|
|
T21 |
357 |
|
T22 |
101 |
|
T23 |
122 |
| auto[1] |
5753283 |
1 |
|
|
T22 |
40 |
|
T26 |
29144 |
|
T27 |
203 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1718101 |
1 |
|
|
T26 |
5601 |
|
T27 |
93 |
|
T28 |
22297 |
| auto[1] |
auto[0] |
auto[1] |
1163816 |
1 |
|
|
T22 |
11 |
|
T26 |
9205 |
|
T27 |
21 |
| auto[1] |
auto[1] |
auto[0] |
1710309 |
1 |
|
|
T22 |
9 |
|
T26 |
5468 |
|
T27 |
79 |
| auto[1] |
auto[1] |
auto[1] |
1161057 |
1 |
|
|
T22 |
20 |
|
T26 |
8870 |
|
T27 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |