Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7914613 |
1 |
|
|
T21 |
357 |
|
T22 |
112 |
|
T23 |
122 |
| auto[1] |
5765542 |
1 |
|
|
T22 |
29 |
|
T26 |
28815 |
|
T27 |
97 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11343206 |
1 |
|
|
T21 |
357 |
|
T22 |
127 |
|
T23 |
122 |
| auto[1] |
2336949 |
1 |
|
|
T22 |
14 |
|
T26 |
18402 |
|
T27 |
31 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7899641 |
1 |
|
|
T21 |
357 |
|
T22 |
122 |
|
T23 |
122 |
| auto[1] |
5780514 |
1 |
|
|
T22 |
19 |
|
T26 |
29523 |
|
T27 |
109 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1717989 |
1 |
|
|
T22 |
5 |
|
T26 |
5619 |
|
T27 |
40 |
| auto[1] |
auto[0] |
auto[1] |
1168161 |
1 |
|
|
T22 |
12 |
|
T26 |
9323 |
|
T27 |
12 |
| auto[1] |
auto[1] |
auto[0] |
1725576 |
1 |
|
|
T26 |
5502 |
|
T27 |
38 |
|
T28 |
21226 |
| auto[1] |
auto[1] |
auto[1] |
1168788 |
1 |
|
|
T22 |
2 |
|
T26 |
9079 |
|
T27 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |