Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7918995 |
1 |
|
|
T21 |
357 |
|
T22 |
110 |
|
T23 |
122 |
| auto[1] |
5761160 |
1 |
|
|
T22 |
31 |
|
T26 |
28926 |
|
T27 |
171 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11359002 |
1 |
|
|
T21 |
357 |
|
T22 |
139 |
|
T23 |
122 |
| auto[1] |
2321153 |
1 |
|
|
T22 |
2 |
|
T26 |
17165 |
|
T27 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7923245 |
1 |
|
|
T21 |
357 |
|
T22 |
131 |
|
T23 |
122 |
| auto[1] |
5756910 |
1 |
|
|
T22 |
10 |
|
T26 |
28110 |
|
T27 |
145 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1724159 |
1 |
|
|
T26 |
5259 |
|
T27 |
43 |
|
T28 |
20497 |
| auto[1] |
auto[0] |
auto[1] |
1164825 |
1 |
|
|
T26 |
8580 |
|
T27 |
1 |
|
T28 |
12266 |
| auto[1] |
auto[1] |
auto[0] |
1711598 |
1 |
|
|
T22 |
8 |
|
T26 |
5686 |
|
T27 |
85 |
| auto[1] |
auto[1] |
auto[1] |
1156328 |
1 |
|
|
T22 |
2 |
|
T26 |
8585 |
|
T27 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |