Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7900167 |
1 |
|
|
T21 |
357 |
|
T22 |
105 |
|
T23 |
122 |
| auto[1] |
5779988 |
1 |
|
|
T22 |
36 |
|
T26 |
29139 |
|
T27 |
142 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11369023 |
1 |
|
|
T21 |
357 |
|
T22 |
138 |
|
T23 |
122 |
| auto[1] |
2311132 |
1 |
|
|
T22 |
3 |
|
T26 |
18659 |
|
T27 |
21 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7954972 |
1 |
|
|
T21 |
357 |
|
T22 |
137 |
|
T23 |
122 |
| auto[1] |
5725183 |
1 |
|
|
T22 |
4 |
|
T26 |
30394 |
|
T27 |
149 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1709838 |
1 |
|
|
T26 |
5762 |
|
T27 |
56 |
|
T28 |
19573 |
| auto[1] |
auto[0] |
auto[1] |
1152314 |
1 |
|
|
T26 |
9190 |
|
T27 |
14 |
|
T28 |
12283 |
| auto[1] |
auto[1] |
auto[0] |
1704213 |
1 |
|
|
T22 |
1 |
|
T26 |
5973 |
|
T27 |
72 |
| auto[1] |
auto[1] |
auto[1] |
1158818 |
1 |
|
|
T22 |
3 |
|
T26 |
9469 |
|
T27 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |