Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7889744 |
1 |
|
|
T21 |
357 |
|
T22 |
79 |
|
T23 |
122 |
| auto[1] |
5790411 |
1 |
|
|
T22 |
62 |
|
T26 |
27388 |
|
T27 |
155 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2530335 |
1 |
|
|
T22 |
56 |
|
T26 |
12114 |
|
T27 |
105 |
| auto[1] |
auto[0] |
auto[1] |
370035 |
1 |
|
|
T22 |
1 |
|
T26 |
1638 |
|
T27 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2521160 |
1 |
|
|
T22 |
5 |
|
T26 |
11957 |
|
T27 |
47 |
| auto[1] |
auto[1] |
auto[1] |
368881 |
1 |
|
|
T26 |
1679 |
|
T27 |
1 |
|
T28 |
4039 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |