Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7913261 |
1 |
|
|
T21 |
357 |
|
T22 |
110 |
|
T23 |
122 |
| auto[1] |
5766894 |
1 |
|
|
T22 |
31 |
|
T26 |
27607 |
|
T27 |
165 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11345907 |
1 |
|
|
T21 |
357 |
|
T22 |
140 |
|
T23 |
122 |
| auto[1] |
2334248 |
1 |
|
|
T22 |
1 |
|
T26 |
16183 |
|
T27 |
32 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7912053 |
1 |
|
|
T21 |
357 |
|
T22 |
130 |
|
T23 |
122 |
| auto[1] |
5768102 |
1 |
|
|
T22 |
11 |
|
T26 |
26298 |
|
T27 |
152 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1719373 |
1 |
|
|
T22 |
10 |
|
T26 |
4938 |
|
T27 |
22 |
| auto[1] |
auto[0] |
auto[1] |
1170381 |
1 |
|
|
T22 |
1 |
|
T26 |
8022 |
|
T27 |
18 |
| auto[1] |
auto[1] |
auto[0] |
1714481 |
1 |
|
|
T26 |
5177 |
|
T27 |
98 |
|
T28 |
20716 |
| auto[1] |
auto[1] |
auto[1] |
1163867 |
1 |
|
|
T26 |
8161 |
|
T27 |
14 |
|
T28 |
12312 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |