Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7899570 |
1 |
|
|
T21 |
357 |
|
T22 |
122 |
|
T23 |
122 |
| auto[1] |
5780585 |
1 |
|
|
T22 |
19 |
|
T26 |
28493 |
|
T27 |
125 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11354395 |
1 |
|
|
T21 |
357 |
|
T22 |
140 |
|
T23 |
122 |
| auto[1] |
2325760 |
1 |
|
|
T22 |
1 |
|
T26 |
17951 |
|
T27 |
71 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7913727 |
1 |
|
|
T21 |
357 |
|
T22 |
129 |
|
T23 |
122 |
| auto[1] |
5766428 |
1 |
|
|
T22 |
12 |
|
T26 |
28881 |
|
T27 |
225 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1723559 |
1 |
|
|
T22 |
11 |
|
T26 |
5558 |
|
T27 |
59 |
| auto[1] |
auto[0] |
auto[1] |
1161854 |
1 |
|
|
T22 |
1 |
|
T26 |
9077 |
|
T27 |
49 |
| auto[1] |
auto[1] |
auto[0] |
1717109 |
1 |
|
|
T26 |
5372 |
|
T27 |
95 |
|
T28 |
20565 |
| auto[1] |
auto[1] |
auto[1] |
1163906 |
1 |
|
|
T26 |
8874 |
|
T27 |
22 |
|
T28 |
12777 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |