Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7905320 |
1 |
|
|
T21 |
357 |
|
T22 |
94 |
|
T23 |
122 |
| auto[1] |
5774835 |
1 |
|
|
T22 |
47 |
|
T26 |
29250 |
|
T27 |
186 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11339208 |
1 |
|
|
T21 |
357 |
|
T22 |
131 |
|
T23 |
122 |
| auto[1] |
2340947 |
1 |
|
|
T22 |
10 |
|
T26 |
17269 |
|
T27 |
26 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7885499 |
1 |
|
|
T21 |
357 |
|
T22 |
126 |
|
T23 |
122 |
| auto[1] |
5794656 |
1 |
|
|
T22 |
15 |
|
T26 |
27938 |
|
T27 |
136 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1730419 |
1 |
|
|
T22 |
5 |
|
T26 |
5227 |
|
T27 |
38 |
| auto[1] |
auto[0] |
auto[1] |
1170198 |
1 |
|
|
T22 |
5 |
|
T26 |
8512 |
|
T27 |
16 |
| auto[1] |
auto[1] |
auto[0] |
1723290 |
1 |
|
|
T26 |
5442 |
|
T27 |
72 |
|
T28 |
20802 |
| auto[1] |
auto[1] |
auto[1] |
1170749 |
1 |
|
|
T22 |
5 |
|
T26 |
8757 |
|
T27 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |