Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7870281 |
1 |
|
|
T21 |
357 |
|
T22 |
94 |
|
T23 |
122 |
| auto[1] |
5809874 |
1 |
|
|
T22 |
47 |
|
T26 |
30173 |
|
T27 |
151 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11329945 |
1 |
|
|
T21 |
357 |
|
T22 |
130 |
|
T23 |
122 |
| auto[1] |
2350210 |
1 |
|
|
T22 |
11 |
|
T26 |
17687 |
|
T27 |
29 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7855646 |
1 |
|
|
T21 |
357 |
|
T22 |
110 |
|
T23 |
122 |
| auto[1] |
5824509 |
1 |
|
|
T22 |
31 |
|
T26 |
28997 |
|
T27 |
147 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1732498 |
1 |
|
|
T22 |
13 |
|
T26 |
5212 |
|
T27 |
81 |
| auto[1] |
auto[0] |
auto[1] |
1176028 |
1 |
|
|
T22 |
8 |
|
T26 |
8265 |
|
T27 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1741801 |
1 |
|
|
T22 |
7 |
|
T26 |
6098 |
|
T27 |
37 |
| auto[1] |
auto[1] |
auto[1] |
1174182 |
1 |
|
|
T22 |
3 |
|
T26 |
9422 |
|
T27 |
24 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |