Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7905960 |
1 |
|
|
T21 |
357 |
|
T22 |
93 |
|
T23 |
122 |
| auto[1] |
5774195 |
1 |
|
|
T22 |
48 |
|
T26 |
28695 |
|
T27 |
115 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11344226 |
1 |
|
|
T21 |
357 |
|
T22 |
114 |
|
T23 |
122 |
| auto[1] |
2335929 |
1 |
|
|
T22 |
27 |
|
T26 |
17244 |
|
T27 |
65 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7897603 |
1 |
|
|
T21 |
357 |
|
T22 |
99 |
|
T23 |
122 |
| auto[1] |
5782552 |
1 |
|
|
T22 |
42 |
|
T26 |
28270 |
|
T27 |
227 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1729886 |
1 |
|
|
T22 |
14 |
|
T26 |
5392 |
|
T27 |
114 |
| auto[1] |
auto[0] |
auto[1] |
1175013 |
1 |
|
|
T22 |
5 |
|
T26 |
8421 |
|
T27 |
22 |
| auto[1] |
auto[1] |
auto[0] |
1716737 |
1 |
|
|
T22 |
1 |
|
T26 |
5634 |
|
T27 |
48 |
| auto[1] |
auto[1] |
auto[1] |
1160916 |
1 |
|
|
T22 |
22 |
|
T26 |
8823 |
|
T27 |
43 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |