Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7876663 |
1 |
|
|
T21 |
357 |
|
T22 |
76 |
|
T23 |
122 |
| auto[1] |
5803492 |
1 |
|
|
T22 |
65 |
|
T26 |
28856 |
|
T27 |
121 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11358573 |
1 |
|
|
T21 |
357 |
|
T22 |
132 |
|
T23 |
122 |
| auto[1] |
2321582 |
1 |
|
|
T22 |
9 |
|
T26 |
17354 |
|
T27 |
79 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7943034 |
1 |
|
|
T21 |
357 |
|
T22 |
132 |
|
T23 |
122 |
| auto[1] |
5737121 |
1 |
|
|
T22 |
9 |
|
T26 |
28186 |
|
T27 |
182 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1688483 |
1 |
|
|
T26 |
5370 |
|
T27 |
51 |
|
T28 |
20042 |
| auto[1] |
auto[0] |
auto[1] |
1154831 |
1 |
|
|
T22 |
8 |
|
T26 |
8604 |
|
T27 |
52 |
| auto[1] |
auto[1] |
auto[0] |
1727056 |
1 |
|
|
T26 |
5462 |
|
T27 |
52 |
|
T28 |
21596 |
| auto[1] |
auto[1] |
auto[1] |
1166751 |
1 |
|
|
T22 |
1 |
|
T26 |
8750 |
|
T27 |
27 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |