Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7882781 |
1 |
|
|
T21 |
357 |
|
T22 |
113 |
|
T23 |
122 |
| auto[1] |
5797374 |
1 |
|
|
T22 |
28 |
|
T26 |
28706 |
|
T27 |
81 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12945287 |
1 |
|
|
T21 |
357 |
|
T22 |
140 |
|
T23 |
122 |
| auto[1] |
734868 |
1 |
|
|
T22 |
1 |
|
T26 |
3669 |
|
T27 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7906472 |
1 |
|
|
T21 |
357 |
|
T22 |
98 |
|
T23 |
122 |
| auto[1] |
5773683 |
1 |
|
|
T22 |
43 |
|
T26 |
29746 |
|
T27 |
135 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2498990 |
1 |
|
|
T22 |
40 |
|
T26 |
12982 |
|
T27 |
98 |
| auto[1] |
auto[0] |
auto[1] |
363294 |
1 |
|
|
T26 |
1865 |
|
T27 |
3 |
|
T28 |
4197 |
| auto[1] |
auto[1] |
auto[0] |
2539825 |
1 |
|
|
T22 |
2 |
|
T26 |
13095 |
|
T27 |
32 |
| auto[1] |
auto[1] |
auto[1] |
371574 |
1 |
|
|
T22 |
1 |
|
T26 |
1804 |
|
T27 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |