Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7906709 |
1 |
|
|
T21 |
357 |
|
T22 |
97 |
|
T23 |
122 |
| auto[1] |
5773446 |
1 |
|
|
T22 |
44 |
|
T26 |
28665 |
|
T27 |
124 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11343844 |
1 |
|
|
T21 |
357 |
|
T22 |
135 |
|
T23 |
122 |
| auto[1] |
2336311 |
1 |
|
|
T22 |
6 |
|
T26 |
18344 |
|
T27 |
49 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7900152 |
1 |
|
|
T21 |
357 |
|
T22 |
128 |
|
T23 |
122 |
| auto[1] |
5780003 |
1 |
|
|
T22 |
13 |
|
T26 |
29754 |
|
T27 |
184 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1725456 |
1 |
|
|
T22 |
1 |
|
T26 |
5687 |
|
T27 |
78 |
| auto[1] |
auto[0] |
auto[1] |
1168885 |
1 |
|
|
T26 |
8559 |
|
T27 |
42 |
|
T28 |
13287 |
| auto[1] |
auto[1] |
auto[0] |
1718236 |
1 |
|
|
T22 |
6 |
|
T26 |
5723 |
|
T27 |
57 |
| auto[1] |
auto[1] |
auto[1] |
1167426 |
1 |
|
|
T22 |
6 |
|
T26 |
9785 |
|
T27 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |