Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7887222 |
1 |
|
|
T21 |
357 |
|
T22 |
105 |
|
T23 |
122 |
| auto[1] |
5792933 |
1 |
|
|
T22 |
36 |
|
T26 |
28176 |
|
T27 |
172 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11348945 |
1 |
|
|
T21 |
357 |
|
T22 |
131 |
|
T23 |
122 |
| auto[1] |
2331210 |
1 |
|
|
T22 |
10 |
|
T26 |
17231 |
|
T27 |
21 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7919457 |
1 |
|
|
T21 |
357 |
|
T22 |
109 |
|
T23 |
122 |
| auto[1] |
5760698 |
1 |
|
|
T22 |
32 |
|
T26 |
27840 |
|
T27 |
137 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1710500 |
1 |
|
|
T22 |
19 |
|
T26 |
5564 |
|
T27 |
65 |
| auto[1] |
auto[0] |
auto[1] |
1169388 |
1 |
|
|
T22 |
9 |
|
T26 |
8997 |
|
T27 |
11 |
| auto[1] |
auto[1] |
auto[0] |
1718988 |
1 |
|
|
T22 |
3 |
|
T26 |
5045 |
|
T27 |
51 |
| auto[1] |
auto[1] |
auto[1] |
1161822 |
1 |
|
|
T22 |
1 |
|
T26 |
8234 |
|
T27 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |