Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7913556 |
1 |
|
|
T21 |
357 |
|
T22 |
84 |
|
T23 |
122 |
| auto[1] |
5766599 |
1 |
|
|
T22 |
57 |
|
T26 |
29498 |
|
T27 |
131 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11344940 |
1 |
|
|
T21 |
357 |
|
T22 |
135 |
|
T23 |
122 |
| auto[1] |
2335215 |
1 |
|
|
T22 |
6 |
|
T26 |
18321 |
|
T27 |
46 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7904877 |
1 |
|
|
T21 |
357 |
|
T22 |
114 |
|
T23 |
122 |
| auto[1] |
5775278 |
1 |
|
|
T22 |
27 |
|
T26 |
29579 |
|
T27 |
115 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1720651 |
1 |
|
|
T22 |
5 |
|
T26 |
5742 |
|
T27 |
42 |
| auto[1] |
auto[0] |
auto[1] |
1169407 |
1 |
|
|
T26 |
8811 |
|
T27 |
29 |
|
T28 |
12445 |
| auto[1] |
auto[1] |
auto[0] |
1719412 |
1 |
|
|
T22 |
16 |
|
T26 |
5516 |
|
T27 |
27 |
| auto[1] |
auto[1] |
auto[1] |
1165808 |
1 |
|
|
T22 |
6 |
|
T26 |
9510 |
|
T27 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |