Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7911538 |
1 |
|
|
T21 |
357 |
|
T22 |
110 |
|
T23 |
122 |
| auto[1] |
5768617 |
1 |
|
|
T22 |
31 |
|
T26 |
28338 |
|
T27 |
151 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12949617 |
1 |
|
|
T21 |
357 |
|
T22 |
139 |
|
T23 |
122 |
| auto[1] |
730538 |
1 |
|
|
T22 |
2 |
|
T26 |
3397 |
|
T27 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7939555 |
1 |
|
|
T21 |
357 |
|
T22 |
99 |
|
T23 |
122 |
| auto[1] |
5740600 |
1 |
|
|
T22 |
42 |
|
T26 |
28648 |
|
T27 |
76 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2500090 |
1 |
|
|
T22 |
33 |
|
T26 |
12440 |
|
T27 |
31 |
| auto[1] |
auto[0] |
auto[1] |
364261 |
1 |
|
|
T22 |
2 |
|
T26 |
1539 |
|
T27 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2509972 |
1 |
|
|
T22 |
7 |
|
T26 |
12811 |
|
T27 |
42 |
| auto[1] |
auto[1] |
auto[1] |
366277 |
1 |
|
|
T26 |
1858 |
|
T27 |
2 |
|
T28 |
4052 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |