Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7950406 |
1 |
|
|
T21 |
357 |
|
T22 |
99 |
|
T23 |
122 |
| auto[1] |
5729749 |
1 |
|
|
T22 |
42 |
|
T26 |
29301 |
|
T27 |
112 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12942650 |
1 |
|
|
T21 |
357 |
|
T22 |
139 |
|
T23 |
122 |
| auto[1] |
737505 |
1 |
|
|
T22 |
2 |
|
T26 |
3672 |
|
T27 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7892794 |
1 |
|
|
T21 |
357 |
|
T22 |
95 |
|
T23 |
122 |
| auto[1] |
5787361 |
1 |
|
|
T22 |
46 |
|
T26 |
29185 |
|
T27 |
194 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2533975 |
1 |
|
|
T22 |
31 |
|
T26 |
12735 |
|
T27 |
117 |
| auto[1] |
auto[0] |
auto[1] |
369731 |
1 |
|
|
T22 |
2 |
|
T26 |
1861 |
|
T27 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2515881 |
1 |
|
|
T22 |
13 |
|
T26 |
12778 |
|
T27 |
72 |
| auto[1] |
auto[1] |
auto[1] |
367774 |
1 |
|
|
T26 |
1811 |
|
T27 |
1 |
|
T28 |
4218 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |