Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7903259 |
1 |
|
|
T21 |
357 |
|
T22 |
98 |
|
T23 |
122 |
| auto[1] |
5776896 |
1 |
|
|
T22 |
43 |
|
T26 |
27938 |
|
T27 |
198 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12937179 |
1 |
|
|
T21 |
357 |
|
T22 |
139 |
|
T23 |
122 |
| auto[1] |
742976 |
1 |
|
|
T22 |
2 |
|
T26 |
3735 |
|
T27 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7867074 |
1 |
|
|
T21 |
357 |
|
T22 |
77 |
|
T23 |
122 |
| auto[1] |
5813081 |
1 |
|
|
T22 |
64 |
|
T26 |
29035 |
|
T27 |
158 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2526047 |
1 |
|
|
T22 |
35 |
|
T26 |
13088 |
|
T27 |
38 |
| auto[1] |
auto[0] |
auto[1] |
369425 |
1 |
|
|
T22 |
1 |
|
T26 |
1998 |
|
T27 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2544058 |
1 |
|
|
T22 |
27 |
|
T26 |
12212 |
|
T27 |
111 |
| auto[1] |
auto[1] |
auto[1] |
373551 |
1 |
|
|
T22 |
1 |
|
T26 |
1737 |
|
T27 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |