Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7894537 |
1 |
|
|
T21 |
357 |
|
T22 |
133 |
|
T23 |
122 |
| auto[1] |
5785618 |
1 |
|
|
T22 |
8 |
|
T26 |
29167 |
|
T27 |
171 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12945109 |
1 |
|
|
T21 |
357 |
|
T22 |
140 |
|
T23 |
122 |
| auto[1] |
735046 |
1 |
|
|
T22 |
1 |
|
T26 |
3668 |
|
T27 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7909705 |
1 |
|
|
T21 |
357 |
|
T22 |
103 |
|
T23 |
122 |
| auto[1] |
5770450 |
1 |
|
|
T22 |
38 |
|
T26 |
29805 |
|
T27 |
190 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2512096 |
1 |
|
|
T22 |
37 |
|
T26 |
12692 |
|
T27 |
69 |
| auto[1] |
auto[0] |
auto[1] |
365154 |
1 |
|
|
T22 |
1 |
|
T26 |
1759 |
|
T27 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2523308 |
1 |
|
|
T26 |
13445 |
|
T27 |
114 |
|
T28 |
28358 |
| auto[1] |
auto[1] |
auto[1] |
369892 |
1 |
|
|
T26 |
1909 |
|
T27 |
3 |
|
T28 |
4080 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |