Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7922486 |
1 |
|
|
T21 |
357 |
|
T22 |
112 |
|
T23 |
122 |
| auto[1] |
5757669 |
1 |
|
|
T22 |
29 |
|
T26 |
29219 |
|
T27 |
171 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12946127 |
1 |
|
|
T21 |
357 |
|
T22 |
140 |
|
T23 |
122 |
| auto[1] |
734028 |
1 |
|
|
T22 |
1 |
|
T26 |
3437 |
|
T27 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7906683 |
1 |
|
|
T21 |
357 |
|
T22 |
101 |
|
T23 |
122 |
| auto[1] |
5773472 |
1 |
|
|
T22 |
40 |
|
T26 |
28293 |
|
T27 |
178 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2527843 |
1 |
|
|
T22 |
27 |
|
T26 |
11733 |
|
T27 |
82 |
| auto[1] |
auto[0] |
auto[1] |
368776 |
1 |
|
|
T22 |
1 |
|
T26 |
1604 |
|
T27 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2511601 |
1 |
|
|
T22 |
12 |
|
T26 |
13123 |
|
T27 |
90 |
| auto[1] |
auto[1] |
auto[1] |
365252 |
1 |
|
|
T26 |
1833 |
|
T27 |
2 |
|
T28 |
4651 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |