Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7883013 |
1 |
|
|
T21 |
357 |
|
T22 |
112 |
|
T23 |
122 |
| auto[1] |
5797142 |
1 |
|
|
T22 |
29 |
|
T26 |
28741 |
|
T27 |
136 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12950204 |
1 |
|
|
T21 |
357 |
|
T22 |
138 |
|
T23 |
122 |
| auto[1] |
729951 |
1 |
|
|
T22 |
3 |
|
T26 |
3567 |
|
T27 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7937427 |
1 |
|
|
T21 |
357 |
|
T22 |
86 |
|
T23 |
122 |
| auto[1] |
5742728 |
1 |
|
|
T22 |
55 |
|
T26 |
28654 |
|
T27 |
126 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2513981 |
1 |
|
|
T22 |
48 |
|
T26 |
12245 |
|
T27 |
85 |
| auto[1] |
auto[0] |
auto[1] |
367080 |
1 |
|
|
T22 |
3 |
|
T26 |
1681 |
|
T27 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2498796 |
1 |
|
|
T22 |
4 |
|
T26 |
12842 |
|
T27 |
36 |
| auto[1] |
auto[1] |
auto[1] |
362871 |
1 |
|
|
T26 |
1886 |
|
T27 |
1 |
|
T28 |
4064 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |