| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.63 | 99.06 | 99.24 | 100.00 | 99.80 | 99.68 | 99.99 |
| T757 | /workspace/coverage/cover_reg_top/31.gpio_intr_test.1443804329 | Jul 11 04:52:38 PM PDT 24 | Jul 11 04:52:48 PM PDT 24 | 15051344 ps | ||
| T758 | /workspace/coverage/cover_reg_top/39.gpio_intr_test.375461122 | Jul 11 04:52:36 PM PDT 24 | Jul 11 04:52:46 PM PDT 24 | 12792480 ps | ||
| T759 | /workspace/coverage/cover_reg_top/42.gpio_intr_test.1597555327 | Jul 11 04:52:34 PM PDT 24 | Jul 11 04:52:46 PM PDT 24 | 12517668 ps | ||
| T760 | /workspace/coverage/cover_reg_top/20.gpio_intr_test.944848436 | Jul 11 04:53:00 PM PDT 24 | Jul 11 04:53:06 PM PDT 24 | 118834916 ps | ||
| T761 | /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.878500105 | Jul 11 04:52:26 PM PDT 24 | Jul 11 04:52:39 PM PDT 24 | 371325698 ps | ||
| T100 | /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3275951336 | Jul 11 04:52:31 PM PDT 24 | Jul 11 04:52:43 PM PDT 24 | 19744099 ps | ||
| T762 | /workspace/coverage/cover_reg_top/21.gpio_intr_test.1196465653 | Jul 11 04:52:32 PM PDT 24 | Jul 11 04:52:43 PM PDT 24 | 19193443 ps | ||
| T49 | /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.509720695 | Jul 11 04:52:21 PM PDT 24 | Jul 11 04:52:35 PM PDT 24 | 126247078 ps | ||
| T763 | /workspace/coverage/cover_reg_top/41.gpio_intr_test.2528011955 | Jul 11 04:52:39 PM PDT 24 | Jul 11 04:52:49 PM PDT 24 | 41047211 ps | ||
| T764 | /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2317377731 | Jul 11 04:52:25 PM PDT 24 | Jul 11 04:52:37 PM PDT 24 | 13003911 ps | ||
| T765 | /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2853366919 | Jul 11 04:52:33 PM PDT 24 | Jul 11 04:52:47 PM PDT 24 | 186558761 ps | ||
| T766 | /workspace/coverage/cover_reg_top/24.gpio_intr_test.1962099723 | Jul 11 04:52:35 PM PDT 24 | Jul 11 04:52:46 PM PDT 24 | 20874545 ps | ||
| T767 | /workspace/coverage/cover_reg_top/18.gpio_csr_rw.792739174 | Jul 11 04:52:27 PM PDT 24 | Jul 11 04:52:40 PM PDT 24 | 53418932 ps | ||
| T768 | /workspace/coverage/cover_reg_top/23.gpio_intr_test.3170734548 | Jul 11 04:52:36 PM PDT 24 | Jul 11 04:52:47 PM PDT 24 | 14472112 ps | ||
| T101 | /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.726145376 | Jul 11 04:52:42 PM PDT 24 | Jul 11 04:52:51 PM PDT 24 | 17017813 ps | ||
| T769 | /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.180642699 | Jul 11 04:52:17 PM PDT 24 | Jul 11 04:52:28 PM PDT 24 | 22045094 ps | ||
| T770 | /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1439750086 | Jul 11 04:52:14 PM PDT 24 | Jul 11 04:52:23 PM PDT 24 | 28644704 ps | ||
| T771 | /workspace/coverage/cover_reg_top/13.gpio_intr_test.1836726956 | Jul 11 04:52:23 PM PDT 24 | Jul 11 04:52:36 PM PDT 24 | 12693925 ps | ||
| T772 | /workspace/coverage/cover_reg_top/3.gpio_csr_rw.632160641 | Jul 11 04:52:16 PM PDT 24 | Jul 11 04:52:26 PM PDT 24 | 51677140 ps | ||
| T773 | /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2393306220 | Jul 11 04:52:26 PM PDT 24 | Jul 11 04:52:40 PM PDT 24 | 30329596 ps | ||
| T774 | /workspace/coverage/cover_reg_top/8.gpio_intr_test.2372797888 | Jul 11 04:52:20 PM PDT 24 | Jul 11 04:52:32 PM PDT 24 | 187571542 ps | ||
| T775 | /workspace/coverage/cover_reg_top/25.gpio_intr_test.316463646 | Jul 11 04:52:36 PM PDT 24 | Jul 11 04:52:46 PM PDT 24 | 13039771 ps | ||
| T776 | /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2086287781 | Jul 11 04:52:22 PM PDT 24 | Jul 11 04:52:35 PM PDT 24 | 32458213 ps | ||
| T777 | /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1089950986 | Jul 11 04:52:26 PM PDT 24 | Jul 11 04:52:39 PM PDT 24 | 132272921 ps | ||
| T778 | /workspace/coverage/cover_reg_top/40.gpio_intr_test.2267444150 | Jul 11 04:52:36 PM PDT 24 | Jul 11 04:52:47 PM PDT 24 | 38554944 ps | ||
| T779 | /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3982054603 | Jul 11 04:52:27 PM PDT 24 | Jul 11 04:52:40 PM PDT 24 | 70338385 ps | ||
| T780 | /workspace/coverage/cover_reg_top/12.gpio_tl_errors.991957157 | Jul 11 04:52:22 PM PDT 24 | Jul 11 04:52:37 PM PDT 24 | 120095847 ps | ||
| T781 | /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2631132939 | Jul 11 04:52:14 PM PDT 24 | Jul 11 04:52:24 PM PDT 24 | 286920276 ps | ||
| T782 | /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2770449521 | Jul 11 04:52:25 PM PDT 24 | Jul 11 04:52:37 PM PDT 24 | 188821308 ps | ||
| T783 | /workspace/coverage/cover_reg_top/2.gpio_intr_test.2583356492 | Jul 11 04:52:16 PM PDT 24 | Jul 11 04:52:27 PM PDT 24 | 26040261 ps | ||
| T784 | /workspace/coverage/cover_reg_top/11.gpio_intr_test.3262995953 | Jul 11 04:52:27 PM PDT 24 | Jul 11 04:52:39 PM PDT 24 | 58920817 ps | ||
| T785 | /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.572328535 | Jul 11 04:52:15 PM PDT 24 | Jul 11 04:52:26 PM PDT 24 | 21087074 ps | ||
| T786 | /workspace/coverage/cover_reg_top/15.gpio_intr_test.46103058 | Jul 11 04:52:29 PM PDT 24 | Jul 11 04:52:41 PM PDT 24 | 66072353 ps | ||
| T787 | /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2471751660 | Jul 11 04:52:27 PM PDT 24 | Jul 11 04:52:40 PM PDT 24 | 93287559 ps | ||
| T788 | /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.4069688225 | Jul 11 04:52:40 PM PDT 24 | Jul 11 04:52:50 PM PDT 24 | 44953722 ps | ||
| T789 | /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3161423272 | Jul 11 04:52:24 PM PDT 24 | Jul 11 04:52:37 PM PDT 24 | 33518467 ps | ||
| T790 | /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2569890912 | Jul 11 04:52:27 PM PDT 24 | Jul 11 04:52:41 PM PDT 24 | 376449596 ps | ||
| T791 | /workspace/coverage/cover_reg_top/6.gpio_intr_test.3808718071 | Jul 11 04:52:16 PM PDT 24 | Jul 11 04:52:25 PM PDT 24 | 39958249 ps | ||
| T792 | /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3324832528 | Jul 11 04:52:28 PM PDT 24 | Jul 11 04:52:41 PM PDT 24 | 72614580 ps | ||
| T793 | /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2055681291 | Jul 11 04:52:16 PM PDT 24 | Jul 11 04:52:27 PM PDT 24 | 144437621 ps | ||
| T794 | /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.713649419 | Jul 11 04:52:20 PM PDT 24 | Jul 11 04:52:32 PM PDT 24 | 24366905 ps | ||
| T91 | /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.413650021 | Jul 11 04:52:17 PM PDT 24 | Jul 11 04:52:28 PM PDT 24 | 16131198 ps | ||
| T795 | /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2303124916 | Jul 11 04:52:12 PM PDT 24 | Jul 11 04:52:21 PM PDT 24 | 151426288 ps | ||
| T796 | /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3998738404 | Jul 11 04:52:25 PM PDT 24 | Jul 11 04:52:38 PM PDT 24 | 52282197 ps | ||
| T797 | /workspace/coverage/cover_reg_top/10.gpio_intr_test.3353768845 | Jul 11 04:52:24 PM PDT 24 | Jul 11 04:52:37 PM PDT 24 | 70553950 ps | ||
| T798 | /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1757512634 | Jul 11 04:52:32 PM PDT 24 | Jul 11 04:52:44 PM PDT 24 | 69296911 ps | ||
| T799 | /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1922968761 | Jul 11 04:52:20 PM PDT 24 | Jul 11 04:52:34 PM PDT 24 | 32283469 ps | ||
| T800 | /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2916563875 | Jul 11 04:52:24 PM PDT 24 | Jul 11 04:52:37 PM PDT 24 | 149578315 ps | ||
| T801 | /workspace/coverage/cover_reg_top/4.gpio_intr_test.2690898259 | Jul 11 04:52:16 PM PDT 24 | Jul 11 04:52:27 PM PDT 24 | 35476320 ps | ||
| T802 | /workspace/coverage/cover_reg_top/32.gpio_intr_test.3440527618 | Jul 11 04:52:34 PM PDT 24 | Jul 11 04:52:46 PM PDT 24 | 14147503 ps | ||
| T803 | /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2095333590 | Jul 11 04:52:40 PM PDT 24 | Jul 11 04:52:50 PM PDT 24 | 140859250 ps | ||
| T804 | /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.4105576970 | Jul 11 04:52:17 PM PDT 24 | Jul 11 04:52:29 PM PDT 24 | 19142018 ps | ||
| T805 | /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2227716090 | Jul 11 04:52:27 PM PDT 24 | Jul 11 04:52:41 PM PDT 24 | 87818384 ps | ||
| T806 | /workspace/coverage/cover_reg_top/33.gpio_intr_test.3723077728 | Jul 11 04:52:35 PM PDT 24 | Jul 11 04:52:46 PM PDT 24 | 162668627 ps | ||
| T807 | /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.325951105 | Jul 11 04:52:17 PM PDT 24 | Jul 11 04:52:28 PM PDT 24 | 15366038 ps | ||
| T808 | /workspace/coverage/cover_reg_top/35.gpio_intr_test.2965964550 | Jul 11 04:52:35 PM PDT 24 | Jul 11 04:52:46 PM PDT 24 | 35446524 ps | ||
| T92 | /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2878876072 | Jul 11 04:52:23 PM PDT 24 | Jul 11 04:52:36 PM PDT 24 | 229228216 ps | ||
| T809 | /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.615100929 | Jul 11 04:52:23 PM PDT 24 | Jul 11 04:52:36 PM PDT 24 | 104352604 ps | ||
| T810 | /workspace/coverage/cover_reg_top/37.gpio_intr_test.1564690073 | Jul 11 04:52:38 PM PDT 24 | Jul 11 04:52:48 PM PDT 24 | 15737566 ps | ||
| T811 | /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2872041031 | Jul 11 04:52:24 PM PDT 24 | Jul 11 04:52:37 PM PDT 24 | 112633383 ps | ||
| T812 | /workspace/coverage/cover_reg_top/30.gpio_intr_test.3154384569 | Jul 11 04:52:34 PM PDT 24 | Jul 11 04:52:46 PM PDT 24 | 64124207 ps | ||
| T813 | /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3286353563 | Jul 11 04:52:14 PM PDT 24 | Jul 11 04:52:23 PM PDT 24 | 14924423 ps | ||
| T814 | /workspace/coverage/cover_reg_top/0.gpio_intr_test.2715573474 | Jul 11 04:52:15 PM PDT 24 | Jul 11 04:52:26 PM PDT 24 | 28486606 ps | ||
| T815 | /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3764050484 | Jul 11 04:52:13 PM PDT 24 | Jul 11 04:52:22 PM PDT 24 | 52825649 ps | ||
| T816 | /workspace/coverage/cover_reg_top/16.gpio_intr_test.721520051 | Jul 11 04:52:42 PM PDT 24 | Jul 11 04:52:51 PM PDT 24 | 16099226 ps | ||
| T817 | /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2328246542 | Jul 11 04:52:11 PM PDT 24 | Jul 11 04:52:17 PM PDT 24 | 13258738 ps | ||
| T818 | /workspace/coverage/cover_reg_top/17.gpio_intr_test.2931271975 | Jul 11 04:52:28 PM PDT 24 | Jul 11 04:52:40 PM PDT 24 | 47702818 ps | ||
| T819 | /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3831614645 | Jul 11 04:52:17 PM PDT 24 | Jul 11 04:52:30 PM PDT 24 | 223961931 ps | ||
| T820 | /workspace/coverage/cover_reg_top/5.gpio_intr_test.3577162472 | Jul 11 04:52:17 PM PDT 24 | Jul 11 04:52:29 PM PDT 24 | 57211299 ps | ||
| T821 | /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1863055770 | Jul 11 04:52:28 PM PDT 24 | Jul 11 04:52:41 PM PDT 24 | 346157629 ps | ||
| T822 | /workspace/coverage/cover_reg_top/36.gpio_intr_test.3841187395 | Jul 11 04:52:36 PM PDT 24 | Jul 11 04:52:47 PM PDT 24 | 14421848 ps | ||
| T823 | /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3155590478 | Jul 11 04:52:19 PM PDT 24 | Jul 11 04:52:33 PM PDT 24 | 170117443 ps | ||
| T824 | /workspace/coverage/cover_reg_top/44.gpio_intr_test.1349495694 | Jul 11 04:52:35 PM PDT 24 | Jul 11 04:52:46 PM PDT 24 | 29603873 ps | ||
| T825 | /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1961432045 | Jul 11 04:52:29 PM PDT 24 | Jul 11 04:52:41 PM PDT 24 | 40374956 ps | ||
| T826 | /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2240069604 | Jul 11 04:52:14 PM PDT 24 | Jul 11 04:52:22 PM PDT 24 | 112684227 ps | ||
| T827 | /workspace/coverage/cover_reg_top/28.gpio_intr_test.553409873 | Jul 11 04:52:35 PM PDT 24 | Jul 11 04:52:46 PM PDT 24 | 11028504 ps | ||
| T828 | /workspace/coverage/cover_reg_top/29.gpio_intr_test.2204052482 | Jul 11 04:52:31 PM PDT 24 | Jul 11 04:52:43 PM PDT 24 | 52138060 ps | ||
| T829 | /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2364643658 | Jul 11 04:52:22 PM PDT 24 | Jul 11 04:52:34 PM PDT 24 | 16708700 ps | ||
| T830 | /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2401094731 | Jul 11 04:52:21 PM PDT 24 | Jul 11 04:52:34 PM PDT 24 | 40901472 ps | ||
| T831 | /workspace/coverage/cover_reg_top/22.gpio_intr_test.2394316768 | Jul 11 04:52:32 PM PDT 24 | Jul 11 04:52:43 PM PDT 24 | 18950734 ps | ||
| T832 | /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.355922820 | Jul 11 04:52:10 PM PDT 24 | Jul 11 04:52:16 PM PDT 24 | 18432114 ps | ||
| T833 | /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.504080831 | Jul 11 04:52:23 PM PDT 24 | Jul 11 04:52:39 PM PDT 24 | 264224250 ps | ||
| T834 | /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.61197294 | Jul 11 04:52:23 PM PDT 24 | Jul 11 04:52:36 PM PDT 24 | 34385471 ps | ||
| T835 | /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1043644754 | Jul 11 04:52:32 PM PDT 24 | Jul 11 04:52:43 PM PDT 24 | 14013305 ps | ||
| T836 | /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2275381659 | Jul 11 04:52:19 PM PDT 24 | Jul 11 04:52:32 PM PDT 24 | 119250853 ps | ||
| T837 | /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1863301572 | Jul 11 04:52:25 PM PDT 24 | Jul 11 04:52:39 PM PDT 24 | 232848512 ps | ||
| T838 | /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2172368194 | Jul 11 04:52:21 PM PDT 24 | Jul 11 04:52:34 PM PDT 24 | 23410196 ps | ||
| T839 | /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3760195421 | Jul 11 04:52:17 PM PDT 24 | Jul 11 04:52:28 PM PDT 24 | 54083106 ps | ||
| T840 | /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2214527238 | Jul 11 04:52:15 PM PDT 24 | Jul 11 04:52:27 PM PDT 24 | 131387203 ps | ||
| T93 | /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1842026212 | Jul 11 04:52:16 PM PDT 24 | Jul 11 04:52:26 PM PDT 24 | 145158660 ps | ||
| T841 | /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.4102580797 | Jul 11 04:52:14 PM PDT 24 | Jul 11 04:52:25 PM PDT 24 | 757608439 ps | ||
| T842 | /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2986192995 | Jul 11 04:27:34 PM PDT 24 | Jul 11 04:27:39 PM PDT 24 | 47783953 ps | ||
| T843 | /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.845202499 | Jul 11 04:26:48 PM PDT 24 | Jul 11 04:26:52 PM PDT 24 | 54227960 ps | ||
| T844 | /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2229865680 | Jul 11 04:26:50 PM PDT 24 | Jul 11 04:26:54 PM PDT 24 | 388419512 ps | ||
| T845 | /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3691341003 | Jul 11 04:27:55 PM PDT 24 | Jul 11 04:27:57 PM PDT 24 | 500240894 ps | ||
| T846 | /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1865038037 | Jul 11 04:26:48 PM PDT 24 | Jul 11 04:26:53 PM PDT 24 | 55889179 ps | ||
| T847 | /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2068468056 | Jul 11 04:28:25 PM PDT 24 | Jul 11 04:28:28 PM PDT 24 | 55464260 ps | ||
| T848 | /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.792892469 | Jul 11 04:26:50 PM PDT 24 | Jul 11 04:26:54 PM PDT 24 | 65231924 ps | ||
| T849 | /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1731477715 | Jul 11 04:26:42 PM PDT 24 | Jul 11 04:26:45 PM PDT 24 | 173962821 ps | ||
| T850 | /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.16321213 | Jul 11 04:26:35 PM PDT 24 | Jul 11 04:26:40 PM PDT 24 | 78159490 ps | ||
| T851 | /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1303581371 | Jul 11 04:27:08 PM PDT 24 | Jul 11 04:27:11 PM PDT 24 | 41684531 ps | ||
| T852 | /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2128003559 | Jul 11 04:26:48 PM PDT 24 | Jul 11 04:26:53 PM PDT 24 | 44614687 ps | ||
| T853 | /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3376144364 | Jul 11 04:26:32 PM PDT 24 | Jul 11 04:26:36 PM PDT 24 | 27226869 ps | ||
| T854 | /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3047599490 | Jul 11 04:27:02 PM PDT 24 | Jul 11 04:27:04 PM PDT 24 | 97227153 ps | ||
| T855 | /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.699450641 | Jul 11 04:28:30 PM PDT 24 | Jul 11 04:28:33 PM PDT 24 | 484678971 ps | ||
| T856 | /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3019265804 | Jul 11 04:27:30 PM PDT 24 | Jul 11 04:27:33 PM PDT 24 | 40135166 ps | ||
| T857 | /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.203382584 | Jul 11 04:27:07 PM PDT 24 | Jul 11 04:27:09 PM PDT 24 | 131976068 ps | ||
| T858 | /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3081320816 | Jul 11 04:26:59 PM PDT 24 | Jul 11 04:27:02 PM PDT 24 | 224117282 ps | ||
| T859 | /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1166931324 | Jul 11 04:26:53 PM PDT 24 | Jul 11 04:26:55 PM PDT 24 | 37798897 ps | ||
| T860 | /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.420703931 | Jul 11 04:27:00 PM PDT 24 | Jul 11 04:27:08 PM PDT 24 | 80635515 ps | ||
| T861 | /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.226578795 | Jul 11 04:26:54 PM PDT 24 | Jul 11 04:26:56 PM PDT 24 | 66391064 ps | ||
| T862 | /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3890768779 | Jul 11 04:26:42 PM PDT 24 | Jul 11 04:26:46 PM PDT 24 | 89984830 ps | ||
| T863 | /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1394434022 | Jul 11 04:26:55 PM PDT 24 | Jul 11 04:26:57 PM PDT 24 | 24598267 ps | ||
| T864 | /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3547193492 | Jul 11 04:26:40 PM PDT 24 | Jul 11 04:26:44 PM PDT 24 | 29968914 ps | ||
| T865 | /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1845000839 | Jul 11 04:27:31 PM PDT 24 | Jul 11 04:27:33 PM PDT 24 | 76200497 ps | ||
| T866 | /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1471273502 | Jul 11 04:28:21 PM PDT 24 | Jul 11 04:28:24 PM PDT 24 | 48576864 ps | ||
| T867 | /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2347769401 | Jul 11 04:27:07 PM PDT 24 | Jul 11 04:27:11 PM PDT 24 | 152567761 ps | ||
| T868 | /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.138535372 | Jul 11 04:27:30 PM PDT 24 | Jul 11 04:27:32 PM PDT 24 | 49667090 ps | ||
| T869 | /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3658804844 | Jul 11 04:28:16 PM PDT 24 | Jul 11 04:28:20 PM PDT 24 | 37006817 ps | ||
| T870 | /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2822986253 | Jul 11 04:27:03 PM PDT 24 | Jul 11 04:27:05 PM PDT 24 | 35273344 ps | ||
| T871 | /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2188804075 | Jul 11 04:28:21 PM PDT 24 | Jul 11 04:28:24 PM PDT 24 | 67861800 ps | ||
| T872 | /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4127554425 | Jul 11 04:27:03 PM PDT 24 | Jul 11 04:27:06 PM PDT 24 | 111007688 ps | ||
| T873 | /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.606157243 | Jul 11 04:26:50 PM PDT 24 | Jul 11 04:26:55 PM PDT 24 | 53084628 ps | ||
| T874 | /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2144195327 | Jul 11 04:27:02 PM PDT 24 | Jul 11 04:27:05 PM PDT 24 | 43982418 ps | ||
| T875 | /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2476054544 | Jul 11 04:27:08 PM PDT 24 | Jul 11 04:27:11 PM PDT 24 | 122383890 ps | ||
| T876 | /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3476475904 | Jul 11 04:27:00 PM PDT 24 | Jul 11 04:27:03 PM PDT 24 | 117989053 ps | ||
| T877 | /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1804821283 | Jul 11 04:26:42 PM PDT 24 | Jul 11 04:26:47 PM PDT 24 | 77994815 ps | ||
| T878 | /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2209755022 | Jul 11 04:26:54 PM PDT 24 | Jul 11 04:26:57 PM PDT 24 | 488781846 ps | ||
| T879 | /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3238689918 | Jul 11 04:26:33 PM PDT 24 | Jul 11 04:26:36 PM PDT 24 | 128854644 ps | ||
| T880 | /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.12124148 | Jul 11 04:26:48 PM PDT 24 | Jul 11 04:26:53 PM PDT 24 | 60533653 ps | ||
| T881 | /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4021054869 | Jul 11 04:26:31 PM PDT 24 | Jul 11 04:26:35 PM PDT 24 | 29665364 ps | ||
| T882 | /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1581404631 | Jul 11 04:27:34 PM PDT 24 | Jul 11 04:27:39 PM PDT 24 | 141335778 ps | ||
| T883 | /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1838917631 | Jul 11 04:27:31 PM PDT 24 | Jul 11 04:27:33 PM PDT 24 | 162935753 ps | ||
| T884 | /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1236583906 | Jul 11 04:26:59 PM PDT 24 | Jul 11 04:27:02 PM PDT 24 | 54568235 ps | ||
| T885 | /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1289384819 | Jul 11 04:26:36 PM PDT 24 | Jul 11 04:26:40 PM PDT 24 | 81887001 ps | ||
| T886 | /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1717127450 | Jul 11 04:27:36 PM PDT 24 | Jul 11 04:27:41 PM PDT 24 | 98697721 ps | ||
| T887 | /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2515259221 | Jul 11 04:27:07 PM PDT 24 | Jul 11 04:27:11 PM PDT 24 | 145609895 ps | ||
| T888 | /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2485447831 | Jul 11 04:26:25 PM PDT 24 | Jul 11 04:26:27 PM PDT 24 | 91063044 ps | ||
| T889 | /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.56527922 | Jul 11 04:26:59 PM PDT 24 | Jul 11 04:27:02 PM PDT 24 | 61619819 ps | ||
| T890 | /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3860603432 | Jul 11 04:27:03 PM PDT 24 | Jul 11 04:27:06 PM PDT 24 | 93581967 ps | ||
| T891 | /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3568766343 | Jul 11 04:27:32 PM PDT 24 | Jul 11 04:27:37 PM PDT 24 | 329542876 ps | ||
| T892 | /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3689223153 | Jul 11 04:26:45 PM PDT 24 | Jul 11 04:26:50 PM PDT 24 | 176935465 ps | ||
| T893 | /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1630165163 | Jul 11 04:28:03 PM PDT 24 | Jul 11 04:28:05 PM PDT 24 | 74574104 ps | ||
| T894 | /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2736706034 | Jul 11 04:27:37 PM PDT 24 | Jul 11 04:27:41 PM PDT 24 | 241706720 ps | ||
| T895 | /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2711026991 | Jul 11 04:27:59 PM PDT 24 | Jul 11 04:28:02 PM PDT 24 | 549215617 ps | ||
| T896 | /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.326320682 | Jul 11 04:27:00 PM PDT 24 | Jul 11 04:27:03 PM PDT 24 | 420507788 ps | ||
| T897 | /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.723056319 | Jul 11 04:27:36 PM PDT 24 | Jul 11 04:27:40 PM PDT 24 | 118052710 ps | ||
| T898 | /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2655214649 | Jul 11 04:27:28 PM PDT 24 | Jul 11 04:27:30 PM PDT 24 | 94300365 ps | ||
| T899 | /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1752525590 | Jul 11 04:27:31 PM PDT 24 | Jul 11 04:27:34 PM PDT 24 | 45902811 ps | ||
| T900 | /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1708643566 | Jul 11 04:28:21 PM PDT 24 | Jul 11 04:28:24 PM PDT 24 | 123250167 ps | ||
| T901 | /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4218121003 | Jul 11 04:26:37 PM PDT 24 | Jul 11 04:26:41 PM PDT 24 | 157619960 ps | ||
| T902 | /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3428640676 | Jul 11 04:27:33 PM PDT 24 | Jul 11 04:27:37 PM PDT 24 | 126837007 ps | ||
| T903 | /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1672517114 | Jul 11 04:27:07 PM PDT 24 | Jul 11 04:27:11 PM PDT 24 | 327517188 ps | ||
| T904 | /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.350176435 | Jul 11 04:26:48 PM PDT 24 | Jul 11 04:26:53 PM PDT 24 | 39603660 ps | ||
| T905 | /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3655254119 | Jul 11 04:27:08 PM PDT 24 | Jul 11 04:27:11 PM PDT 24 | 40612110 ps | ||
| T906 | /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.779394229 | Jul 11 04:27:02 PM PDT 24 | Jul 11 04:27:09 PM PDT 24 | 93209574 ps | ||
| T907 | /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.361652410 | Jul 11 04:27:07 PM PDT 24 | Jul 11 04:27:11 PM PDT 24 | 221430464 ps | ||
| T908 | /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.941812996 | Jul 11 04:27:32 PM PDT 24 | Jul 11 04:27:35 PM PDT 24 | 23573612 ps | ||
| T909 | /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2087168041 | Jul 11 04:27:03 PM PDT 24 | Jul 11 04:27:06 PM PDT 24 | 119648509 ps | ||
| T910 | /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1427722454 | Jul 11 04:27:07 PM PDT 24 | Jul 11 04:27:11 PM PDT 24 | 99337680 ps | ||
| T911 | /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.558004054 | Jul 11 04:27:32 PM PDT 24 | Jul 11 04:27:36 PM PDT 24 | 174060388 ps | ||
| T912 | /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3704492132 | Jul 11 04:27:05 PM PDT 24 | Jul 11 04:27:07 PM PDT 24 | 37402195 ps | ||
| T913 | /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1022403218 | Jul 11 04:27:07 PM PDT 24 | Jul 11 04:27:09 PM PDT 24 | 813180535 ps | ||
| T914 | /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2899421053 | Jul 11 04:27:02 PM PDT 24 | Jul 11 04:27:05 PM PDT 24 | 63444193 ps | ||
| T915 | /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3294510889 | Jul 11 04:26:42 PM PDT 24 | Jul 11 04:26:47 PM PDT 24 | 329826938 ps | ||
| T916 | /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.936657197 | Jul 11 04:27:32 PM PDT 24 | Jul 11 04:27:34 PM PDT 24 | 38228472 ps | ||
| T917 | /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3883281877 | Jul 11 04:26:56 PM PDT 24 | Jul 11 04:26:58 PM PDT 24 | 40052412 ps | ||
| T918 | /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3735137559 | Jul 11 04:27:57 PM PDT 24 | Jul 11 04:28:01 PM PDT 24 | 93181418 ps | ||
| T919 | /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2327936787 | Jul 11 04:26:42 PM PDT 24 | Jul 11 04:26:46 PM PDT 24 | 105411575 ps | ||
| T920 | /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.914818604 | Jul 11 04:26:59 PM PDT 24 | Jul 11 04:27:02 PM PDT 24 | 133108092 ps | ||
| T921 | /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2712456849 | Jul 11 04:26:33 PM PDT 24 | Jul 11 04:26:36 PM PDT 24 | 21953938 ps | ||
| T922 | /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2688281072 | Jul 11 04:28:15 PM PDT 24 | Jul 11 04:28:18 PM PDT 24 | 31498229 ps | ||
| T923 | /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4085426172 | Jul 11 04:27:05 PM PDT 24 | Jul 11 04:27:08 PM PDT 24 | 85733514 ps | ||
| T924 | /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1210419823 | Jul 11 04:26:45 PM PDT 24 | Jul 11 04:26:49 PM PDT 24 | 158976354 ps | ||
| T925 | /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1244140566 | Jul 11 04:27:01 PM PDT 24 | Jul 11 04:27:03 PM PDT 24 | 34201352 ps | ||
| T926 | /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1282977811 | Jul 11 04:27:05 PM PDT 24 | Jul 11 04:27:08 PM PDT 24 | 58559602 ps | ||
| T927 | /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1987301137 | Jul 11 04:27:01 PM PDT 24 | Jul 11 04:27:04 PM PDT 24 | 147133189 ps | ||
| T928 | /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2297441272 | Jul 11 04:26:58 PM PDT 24 | Jul 11 04:27:00 PM PDT 24 | 180288194 ps | ||
| T929 | /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2839784022 | Jul 11 04:27:39 PM PDT 24 | Jul 11 04:27:43 PM PDT 24 | 304328081 ps | ||
| T930 | /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3801663253 | Jul 11 04:27:29 PM PDT 24 | Jul 11 04:27:31 PM PDT 24 | 276428091 ps | ||
| T931 | /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1166294877 | Jul 11 04:27:27 PM PDT 24 | Jul 11 04:27:30 PM PDT 24 | 163718472 ps | ||
| T932 | /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.152565245 | Jul 11 04:27:02 PM PDT 24 | Jul 11 04:27:04 PM PDT 24 | 78721839 ps | ||
| T933 | /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2932273347 | Jul 11 04:28:09 PM PDT 24 | Jul 11 04:28:12 PM PDT 24 | 31512779 ps | ||
| T934 | /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3467251795 | Jul 11 04:27:05 PM PDT 24 | Jul 11 04:27:08 PM PDT 24 | 38630785 ps | ||
| T935 | /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2859958618 | Jul 11 04:26:45 PM PDT 24 | Jul 11 04:26:50 PM PDT 24 | 49993719 ps | ||
| T936 | /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.4151137009 | Jul 11 04:26:42 PM PDT 24 | Jul 11 04:26:45 PM PDT 24 | 240458686 ps | ||
| T937 | /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2185487127 | Jul 11 04:26:42 PM PDT 24 | Jul 11 04:26:46 PM PDT 24 | 37948007 ps | ||
| T938 | /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2388470934 | Jul 11 04:28:14 PM PDT 24 | Jul 11 04:28:16 PM PDT 24 | 41050727 ps | ||
| T939 | /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.984019169 | Jul 11 04:27:07 PM PDT 24 | Jul 11 04:27:11 PM PDT 24 | 159013180 ps | ||
| T940 | /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.543763167 | Jul 11 04:27:33 PM PDT 24 | Jul 11 04:27:38 PM PDT 24 | 48835740 ps | ||
| T941 | /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.269889991 | Jul 11 04:26:48 PM PDT 24 | Jul 11 04:26:53 PM PDT 24 | 320514832 ps |
| Test location | /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.4268737235 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 74118564629 ps |
| CPU time | 356.08 seconds |
| Started | Jul 11 04:32:05 PM PDT 24 |
| Finished | Jul 11 04:38:29 PM PDT 24 |
| Peak memory | 198524 kb |
| Host | smart-f6ce6223-4019-4c8c-a1b6-3cd9ffda062a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =4268737235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.4268737235 |
| Directory | /workspace/37.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3115336870 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 97830206 ps |
| CPU time | 1.13 seconds |
| Started | Jul 11 04:30:59 PM PDT 24 |
| Finished | Jul 11 04:31:06 PM PDT 24 |
| Peak memory | 197952 kb |
| Host | smart-83b9ced6-1838-4241-922f-461776f7f311 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115336870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3115336870 |
| Directory | /workspace/35.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1937771260 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1997333417 ps |
| CPU time | 6.62 seconds |
| Started | Jul 11 04:30:18 PM PDT 24 |
| Finished | Jul 11 04:30:38 PM PDT 24 |
| Peak memory | 198592 kb |
| Host | smart-9e1a3d95-83bc-4599-8669-8ec7e852f2ef |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937771260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra ndom_long_reg_writes_reg_reads.1937771260 |
| Directory | /workspace/14.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/1.gpio_sec_cm.2537884944 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 135854421 ps |
| CPU time | 0.8 seconds |
| Started | Jul 11 04:29:51 PM PDT 24 |
| Finished | Jul 11 04:29:54 PM PDT 24 |
| Peak memory | 214052 kb |
| Host | smart-92276b66-28ea-41ee-8f32-da156692f160 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537884944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2537884944 |
| Directory | /workspace/1.gpio_sec_cm/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2593981260 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 133555854 ps |
| CPU time | 0.86 seconds |
| Started | Jul 11 04:52:15 PM PDT 24 |
| Finished | Jul 11 04:52:26 PM PDT 24 |
| Peak memory | 196600 kb |
| Host | smart-d67f921d-80f9-4456-ac41-9908f6296342 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593981260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM _TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_aliasing.2593981260 |
| Directory | /workspace/1.gpio_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1839767468 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 351783996 ps |
| CPU time | 1.39 seconds |
| Started | Jul 11 04:52:25 PM PDT 24 |
| Finished | Jul 11 04:52:38 PM PDT 24 |
| Peak memory | 198680 kb |
| Host | smart-6f577d69-3829-4ced-bc9f-7db34a635d20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839767468 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 6.gpio_tl_intg_err.1839767468 |
| Directory | /workspace/6.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1778443894 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 65834482 ps |
| CPU time | 0.96 seconds |
| Started | Jul 11 04:30:16 PM PDT 24 |
| Finished | Jul 11 04:30:29 PM PDT 24 |
| Peak memory | 196856 kb |
| Host | smart-1c78ade0-7435-4348-872a-28634d294540 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778443894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1778443894 |
| Directory | /workspace/14.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/19.gpio_alert_test.2531830249 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 39342457 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:30:27 PM PDT 24 |
| Finished | Jul 11 04:30:39 PM PDT 24 |
| Peak memory | 194688 kb |
| Host | smart-50f830fb-9375-476a-84c3-3c29e71c4578 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531830249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2531830249 |
| Directory | /workspace/19.gpio_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1863055770 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 346157629 ps |
| CPU time | 1.42 seconds |
| Started | Jul 11 04:52:28 PM PDT 24 |
| Finished | Jul 11 04:52:41 PM PDT 24 |
| Peak memory | 198700 kb |
| Host | smart-067bb315-779c-4cd7-8859-56f618709168 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863055770 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 18.gpio_tl_intg_err.1863055770 |
| Directory | /workspace/18.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.4246009892 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 39343857 ps |
| CPU time | 0.82 seconds |
| Started | Jul 11 04:52:21 PM PDT 24 |
| Finished | Jul 11 04:52:34 PM PDT 24 |
| Peak memory | 197204 kb |
| Host | smart-90ccf65d-c241-4f9f-a227-807f56592909 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246009892 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 10.gpio_same_csr_outstanding.4246009892 |
| Directory | /workspace/10.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2246352493 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 683974042 ps |
| CPU time | 1.13 seconds |
| Started | Jul 11 04:52:14 PM PDT 24 |
| Finished | Jul 11 04:52:23 PM PDT 24 |
| Peak memory | 198636 kb |
| Host | smart-f5167a8b-ab94-4a46-804d-984237b40689 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246352493 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 1.gpio_tl_intg_err.2246352493 |
| Directory | /workspace/1.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2483873753 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 22781317 ps |
| CPU time | 0.64 seconds |
| Started | Jul 11 04:52:13 PM PDT 24 |
| Finished | Jul 11 04:52:22 PM PDT 24 |
| Peak memory | 195416 kb |
| Host | smart-3820aaee-b089-4ab0-9467-695a94228575 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483873753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM _TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_aliasing.2483873753 |
| Directory | /workspace/0.gpio_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3210201824 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 367032532 ps |
| CPU time | 1.48 seconds |
| Started | Jul 11 04:52:15 PM PDT 24 |
| Finished | Jul 11 04:52:25 PM PDT 24 |
| Peak memory | 197328 kb |
| Host | smart-fd7c81cc-ace1-4584-a455-1de2e0e41359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210201824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3210201824 |
| Directory | /workspace/0.gpio_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.355922820 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 18432114 ps |
| CPU time | 0.71 seconds |
| Started | Jul 11 04:52:10 PM PDT 24 |
| Finished | Jul 11 04:52:16 PM PDT 24 |
| Peak memory | 196056 kb |
| Host | smart-4a584199-84b9-4451-9aba-84189aa628ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355922820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.355922820 |
| Directory | /workspace/0.gpio_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2303124916 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 151426288 ps |
| CPU time | 1.43 seconds |
| Started | Jul 11 04:52:12 PM PDT 24 |
| Finished | Jul 11 04:52:21 PM PDT 24 |
| Peak memory | 198744 kb |
| Host | smart-60242c67-3834-4ed2-b7e5-4dd689addc3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303124916 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2303124916 |
| Directory | /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2328246542 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 13258738 ps |
| CPU time | 0.62 seconds |
| Started | Jul 11 04:52:11 PM PDT 24 |
| Finished | Jul 11 04:52:17 PM PDT 24 |
| Peak memory | 195032 kb |
| Host | smart-1917c445-237d-4c24-89fd-5bf0ba8d83d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328246542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio _csr_rw.2328246542 |
| Directory | /workspace/0.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_intr_test.2715573474 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 28486606 ps |
| CPU time | 0.68 seconds |
| Started | Jul 11 04:52:15 PM PDT 24 |
| Finished | Jul 11 04:52:26 PM PDT 24 |
| Peak memory | 194288 kb |
| Host | smart-b57a2feb-cf15-45b4-bd0d-ccb4de3bc9b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715573474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2715573474 |
| Directory | /workspace/0.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1439750086 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 28644704 ps |
| CPU time | 0.74 seconds |
| Started | Jul 11 04:52:14 PM PDT 24 |
| Finished | Jul 11 04:52:23 PM PDT 24 |
| Peak memory | 196804 kb |
| Host | smart-eba2cc51-c343-434d-86a6-085cb84da9f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439750086 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.gpio_same_csr_outstanding.1439750086 |
| Directory | /workspace/0.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2055681291 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 144437621 ps |
| CPU time | 1.66 seconds |
| Started | Jul 11 04:52:16 PM PDT 24 |
| Finished | Jul 11 04:52:27 PM PDT 24 |
| Peak memory | 198604 kb |
| Host | smart-ba2701c2-2766-4d98-a203-0c0f976aefb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055681291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2055681291 |
| Directory | /workspace/0.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3380369563 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 151053193 ps |
| CPU time | 1.16 seconds |
| Started | Jul 11 04:52:10 PM PDT 24 |
| Finished | Jul 11 04:52:16 PM PDT 24 |
| Peak memory | 198612 kb |
| Host | smart-720aeaff-f34d-4eba-8e65-578375c2573e |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380369563 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 0.gpio_tl_intg_err.3380369563 |
| Directory | /workspace/0.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.4102580797 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 757608439 ps |
| CPU time | 2.12 seconds |
| Started | Jul 11 04:52:14 PM PDT 24 |
| Finished | Jul 11 04:52:25 PM PDT 24 |
| Peak memory | 197204 kb |
| Host | smart-bb8538d3-2e3d-4201-bd49-7b3afafaf593 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102580797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.4102580797 |
| Directory | /workspace/1.gpio_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.413650021 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 16131198 ps |
| CPU time | 0.6 seconds |
| Started | Jul 11 04:52:17 PM PDT 24 |
| Finished | Jul 11 04:52:28 PM PDT 24 |
| Peak memory | 195532 kb |
| Host | smart-45704ff7-f6d7-4662-9385-247843864ed5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413650021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.413650021 |
| Directory | /workspace/1.gpio_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3063261012 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 22510913 ps |
| CPU time | 0.92 seconds |
| Started | Jul 11 04:52:17 PM PDT 24 |
| Finished | Jul 11 04:52:29 PM PDT 24 |
| Peak memory | 198512 kb |
| Host | smart-debaaf3f-a07d-4118-bf9b-e3b22308d737 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063261012 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3063261012 |
| Directory | /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3738390306 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 78507094 ps |
| CPU time | 0.6 seconds |
| Started | Jul 11 04:52:12 PM PDT 24 |
| Finished | Jul 11 04:52:20 PM PDT 24 |
| Peak memory | 195328 kb |
| Host | smart-505e621a-7793-4c56-b7e8-e0cac7164033 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738390306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio _csr_rw.3738390306 |
| Directory | /workspace/1.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_intr_test.2528263015 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 13725601 ps |
| CPU time | 0.6 seconds |
| Started | Jul 11 04:52:17 PM PDT 24 |
| Finished | Jul 11 04:52:29 PM PDT 24 |
| Peak memory | 194824 kb |
| Host | smart-ebd541b2-adf8-4a6d-868d-bd2db4b88028 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528263015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2528263015 |
| Directory | /workspace/1.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3764050484 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 52825649 ps |
| CPU time | 0.86 seconds |
| Started | Jul 11 04:52:13 PM PDT 24 |
| Finished | Jul 11 04:52:22 PM PDT 24 |
| Peak memory | 197120 kb |
| Host | smart-97cf7348-3be6-4f11-b5a5-46532771e934 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764050484 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.gpio_same_csr_outstanding.3764050484 |
| Directory | /workspace/1.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3155590478 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 170117443 ps |
| CPU time | 2.49 seconds |
| Started | Jul 11 04:52:19 PM PDT 24 |
| Finished | Jul 11 04:52:33 PM PDT 24 |
| Peak memory | 198640 kb |
| Host | smart-da0ee7aa-0a76-4754-8fdf-c43f601f9c19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155590478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3155590478 |
| Directory | /workspace/1.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2393306220 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 30329596 ps |
| CPU time | 1.31 seconds |
| Started | Jul 11 04:52:26 PM PDT 24 |
| Finished | Jul 11 04:52:40 PM PDT 24 |
| Peak memory | 198736 kb |
| Host | smart-78346651-a4ce-4f52-923b-da58f2b417e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393306220 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2393306220 |
| Directory | /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2364643658 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 16708700 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:52:22 PM PDT 24 |
| Finished | Jul 11 04:52:34 PM PDT 24 |
| Peak memory | 195836 kb |
| Host | smart-c624f2ad-c4db-45b5-a77e-0c0ca8ea5e81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364643658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi o_csr_rw.2364643658 |
| Directory | /workspace/10.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_intr_test.3353768845 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 70553950 ps |
| CPU time | 0.57 seconds |
| Started | Jul 11 04:52:24 PM PDT 24 |
| Finished | Jul 11 04:52:37 PM PDT 24 |
| Peak memory | 194292 kb |
| Host | smart-bcfcb64e-dd85-4839-aae0-6d95158340f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353768845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3353768845 |
| Directory | /workspace/10.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2296275494 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 119581696 ps |
| CPU time | 2.14 seconds |
| Started | Jul 11 04:52:25 PM PDT 24 |
| Finished | Jul 11 04:52:38 PM PDT 24 |
| Peak memory | 198700 kb |
| Host | smart-516f3955-c8c5-4ce7-b923-7681ed95c272 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296275494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2296275494 |
| Directory | /workspace/10.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3554091011 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 39880336 ps |
| CPU time | 0.85 seconds |
| Started | Jul 11 04:52:23 PM PDT 24 |
| Finished | Jul 11 04:52:36 PM PDT 24 |
| Peak memory | 197816 kb |
| Host | smart-82e5ad29-ae3f-4e12-9001-c2bd6ad4a04c |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554091011 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 10.gpio_tl_intg_err.3554091011 |
| Directory | /workspace/10.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.713649419 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 24366905 ps |
| CPU time | 1.02 seconds |
| Started | Jul 11 04:52:20 PM PDT 24 |
| Finished | Jul 11 04:52:32 PM PDT 24 |
| Peak memory | 198608 kb |
| Host | smart-96b1397e-71ec-49ba-be32-2fe52f3a1753 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713649419 -asser t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.713649419 |
| Directory | /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2317377731 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 13003911 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:52:25 PM PDT 24 |
| Finished | Jul 11 04:52:37 PM PDT 24 |
| Peak memory | 194016 kb |
| Host | smart-145d50e6-0a28-4436-bf4a-e9dbcec292a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317377731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi o_csr_rw.2317377731 |
| Directory | /workspace/11.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_intr_test.3262995953 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 58920817 ps |
| CPU time | 0.6 seconds |
| Started | Jul 11 04:52:27 PM PDT 24 |
| Finished | Jul 11 04:52:39 PM PDT 24 |
| Peak memory | 194432 kb |
| Host | smart-b5788b10-317d-4ca4-b193-c686d5e5cc96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262995953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3262995953 |
| Directory | /workspace/11.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3806337032 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 36075666 ps |
| CPU time | 0.9 seconds |
| Started | Jul 11 04:52:21 PM PDT 24 |
| Finished | Jul 11 04:52:35 PM PDT 24 |
| Peak memory | 196944 kb |
| Host | smart-42d3d730-7888-43b1-b3de-a2ad8e74dd69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806337032 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 11.gpio_same_csr_outstanding.3806337032 |
| Directory | /workspace/11.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2076778240 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 145985473 ps |
| CPU time | 1.09 seconds |
| Started | Jul 11 04:52:22 PM PDT 24 |
| Finished | Jul 11 04:52:36 PM PDT 24 |
| Peak memory | 198432 kb |
| Host | smart-1291bdfa-39bb-43e6-912c-1796a4f202a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076778240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2076778240 |
| Directory | /workspace/11.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2916563875 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 149578315 ps |
| CPU time | 1.18 seconds |
| Started | Jul 11 04:52:24 PM PDT 24 |
| Finished | Jul 11 04:52:37 PM PDT 24 |
| Peak memory | 198348 kb |
| Host | smart-a5cf6627-6422-4ece-858a-a3dae74158d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916563875 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 11.gpio_tl_intg_err.2916563875 |
| Directory | /workspace/11.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.95379528 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 89899445 ps |
| CPU time | 1.3 seconds |
| Started | Jul 11 04:52:22 PM PDT 24 |
| Finished | Jul 11 04:52:36 PM PDT 24 |
| Peak memory | 198632 kb |
| Host | smart-f798c6d3-1713-4c18-b040-0e7de9a52614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95379528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.95379528 |
| Directory | /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1791494206 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 34065926 ps |
| CPU time | 0.65 seconds |
| Started | Jul 11 04:52:21 PM PDT 24 |
| Finished | Jul 11 04:52:33 PM PDT 24 |
| Peak memory | 194904 kb |
| Host | smart-71b60312-2647-4829-b5dc-35579b956bb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791494206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi o_csr_rw.1791494206 |
| Directory | /workspace/12.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_intr_test.677193551 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 20948125 ps |
| CPU time | 0.57 seconds |
| Started | Jul 11 04:52:22 PM PDT 24 |
| Finished | Jul 11 04:52:34 PM PDT 24 |
| Peak memory | 194936 kb |
| Host | smart-a0cdb31b-c0d6-48d0-9af1-2d7f9df521eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677193551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.677193551 |
| Directory | /workspace/12.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1219484596 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 47053414 ps |
| CPU time | 0.74 seconds |
| Started | Jul 11 04:52:21 PM PDT 24 |
| Finished | Jul 11 04:52:32 PM PDT 24 |
| Peak memory | 197088 kb |
| Host | smart-75bb8082-5f0f-4909-933c-ea79f58cb23c |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219484596 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 12.gpio_same_csr_outstanding.1219484596 |
| Directory | /workspace/12.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_tl_errors.991957157 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 120095847 ps |
| CPU time | 2.69 seconds |
| Started | Jul 11 04:52:22 PM PDT 24 |
| Finished | Jul 11 04:52:37 PM PDT 24 |
| Peak memory | 198700 kb |
| Host | smart-2b0523b1-9364-4a6e-87eb-1ef870db5082 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991957157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.991957157 |
| Directory | /workspace/12.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1863301572 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 232848512 ps |
| CPU time | 1.43 seconds |
| Started | Jul 11 04:52:25 PM PDT 24 |
| Finished | Jul 11 04:52:39 PM PDT 24 |
| Peak memory | 198596 kb |
| Host | smart-ca8b5119-388c-44c7-8d98-366151ce5d6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863301572 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 12.gpio_tl_intg_err.1863301572 |
| Directory | /workspace/12.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.615100929 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 104352604 ps |
| CPU time | 1.18 seconds |
| Started | Jul 11 04:52:23 PM PDT 24 |
| Finished | Jul 11 04:52:36 PM PDT 24 |
| Peak memory | 198648 kb |
| Host | smart-1aa4400d-79e6-43fc-b464-45d5a166d03b |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615100929 -asser t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.615100929 |
| Directory | /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2086287781 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 32458213 ps |
| CPU time | 0.56 seconds |
| Started | Jul 11 04:52:22 PM PDT 24 |
| Finished | Jul 11 04:52:35 PM PDT 24 |
| Peak memory | 195328 kb |
| Host | smart-4aa81c0a-9c9f-45fa-bc17-ea8958599b23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086287781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi o_csr_rw.2086287781 |
| Directory | /workspace/13.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_intr_test.1836726956 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 12693925 ps |
| CPU time | 0.6 seconds |
| Started | Jul 11 04:52:23 PM PDT 24 |
| Finished | Jul 11 04:52:36 PM PDT 24 |
| Peak memory | 194284 kb |
| Host | smart-d2209e71-70e3-447b-b08d-cba7081f5a3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836726956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1836726956 |
| Directory | /workspace/13.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3453873744 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 28676710 ps |
| CPU time | 0.75 seconds |
| Started | Jul 11 04:52:23 PM PDT 24 |
| Finished | Jul 11 04:52:36 PM PDT 24 |
| Peak memory | 195592 kb |
| Host | smart-3cdbe8f7-4439-4387-a76d-6edb986fbfd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453873744 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 13.gpio_same_csr_outstanding.3453873744 |
| Directory | /workspace/13.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1603329475 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 93941152 ps |
| CPU time | 1.3 seconds |
| Started | Jul 11 04:52:25 PM PDT 24 |
| Finished | Jul 11 04:52:39 PM PDT 24 |
| Peak memory | 198736 kb |
| Host | smart-8947683c-1575-4a5a-a216-cefb0826d749 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603329475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1603329475 |
| Directory | /workspace/13.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2770449521 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 188821308 ps |
| CPU time | 0.88 seconds |
| Started | Jul 11 04:52:25 PM PDT 24 |
| Finished | Jul 11 04:52:37 PM PDT 24 |
| Peak memory | 198428 kb |
| Host | smart-2b806f55-e5f0-410e-9494-ae851577ef09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770449521 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 13.gpio_tl_intg_err.2770449521 |
| Directory | /workspace/13.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1209056640 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 27158567 ps |
| CPU time | 1.28 seconds |
| Started | Jul 11 04:52:25 PM PDT 24 |
| Finished | Jul 11 04:52:39 PM PDT 24 |
| Peak memory | 198768 kb |
| Host | smart-658d118f-5562-4a35-a79e-e351404bda2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209056640 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1209056640 |
| Directory | /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1137582292 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 19987428 ps |
| CPU time | 0.62 seconds |
| Started | Jul 11 04:52:22 PM PDT 24 |
| Finished | Jul 11 04:52:35 PM PDT 24 |
| Peak memory | 196092 kb |
| Host | smart-18180eb5-65f9-4dbd-a0b5-395edb3f3c08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137582292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi o_csr_rw.1137582292 |
| Directory | /workspace/14.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_intr_test.3818244410 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 19471039 ps |
| CPU time | 0.6 seconds |
| Started | Jul 11 04:52:31 PM PDT 24 |
| Finished | Jul 11 04:52:43 PM PDT 24 |
| Peak memory | 194352 kb |
| Host | smart-4eba926a-e3b9-49ea-84ab-b17e01d7bfb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818244410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3818244410 |
| Directory | /workspace/14.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3161423272 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 33518467 ps |
| CPU time | 0.68 seconds |
| Started | Jul 11 04:52:24 PM PDT 24 |
| Finished | Jul 11 04:52:37 PM PDT 24 |
| Peak memory | 196092 kb |
| Host | smart-c6fb4eab-1aa2-466c-8715-c5787353e673 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161423272 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 14.gpio_same_csr_outstanding.3161423272 |
| Directory | /workspace/14.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2300819232 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 79518380 ps |
| CPU time | 1.98 seconds |
| Started | Jul 11 04:52:28 PM PDT 24 |
| Finished | Jul 11 04:52:41 PM PDT 24 |
| Peak memory | 198700 kb |
| Host | smart-5da6a4fe-208f-4234-a798-96d1ef0d5ccc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300819232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2300819232 |
| Directory | /workspace/14.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2471751660 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 93287559 ps |
| CPU time | 1.14 seconds |
| Started | Jul 11 04:52:27 PM PDT 24 |
| Finished | Jul 11 04:52:40 PM PDT 24 |
| Peak memory | 198712 kb |
| Host | smart-e759d59e-4762-4944-943b-63dc1971c5f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471751660 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 14.gpio_tl_intg_err.2471751660 |
| Directory | /workspace/14.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.4245058466 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 72716668 ps |
| CPU time | 0.96 seconds |
| Started | Jul 11 04:52:41 PM PDT 24 |
| Finished | Jul 11 04:52:51 PM PDT 24 |
| Peak memory | 198532 kb |
| Host | smart-cfdd25f8-2ba4-44ab-9244-f895424cce5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245058466 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.4245058466 |
| Directory | /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1043644754 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 14013305 ps |
| CPU time | 0.65 seconds |
| Started | Jul 11 04:52:32 PM PDT 24 |
| Finished | Jul 11 04:52:43 PM PDT 24 |
| Peak memory | 195532 kb |
| Host | smart-82207148-2cdf-4403-8a99-5776dccd3ffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043644754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi o_csr_rw.1043644754 |
| Directory | /workspace/15.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_intr_test.46103058 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 66072353 ps |
| CPU time | 0.68 seconds |
| Started | Jul 11 04:52:29 PM PDT 24 |
| Finished | Jul 11 04:52:41 PM PDT 24 |
| Peak memory | 194356 kb |
| Host | smart-6911d7e4-1dd1-4899-b70b-5442a3d5478b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46103058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.46103058 |
| Directory | /workspace/15.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.726145376 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 17017813 ps |
| CPU time | 0.72 seconds |
| Started | Jul 11 04:52:42 PM PDT 24 |
| Finished | Jul 11 04:52:51 PM PDT 24 |
| Peak memory | 195824 kb |
| Host | smart-5360fb40-84f0-4d01-be9d-a4b8edbf9884 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726145376 -assert nopostproc +UVM_TESTNAME=gpio_bas e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 15.gpio_same_csr_outstanding.726145376 |
| Directory | /workspace/15.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3797283996 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 551132977 ps |
| CPU time | 2.41 seconds |
| Started | Jul 11 04:52:27 PM PDT 24 |
| Finished | Jul 11 04:52:41 PM PDT 24 |
| Peak memory | 198608 kb |
| Host | smart-243e323e-d570-457a-a4c6-765434fc799d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797283996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.3797283996 |
| Directory | /workspace/15.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2095333590 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 140859250 ps |
| CPU time | 0.91 seconds |
| Started | Jul 11 04:52:40 PM PDT 24 |
| Finished | Jul 11 04:52:50 PM PDT 24 |
| Peak memory | 197864 kb |
| Host | smart-823d78e9-fa9f-4326-8ea9-b611532434b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095333590 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 15.gpio_tl_intg_err.2095333590 |
| Directory | /workspace/15.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3821816092 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 121594215 ps |
| CPU time | 0.95 seconds |
| Started | Jul 11 04:52:28 PM PDT 24 |
| Finished | Jul 11 04:52:40 PM PDT 24 |
| Peak memory | 198600 kb |
| Host | smart-ccbcb7eb-f446-4a73-92fc-cc97b7769d83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821816092 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3821816092 |
| Directory | /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1924334627 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 54418507 ps |
| CPU time | 0.63 seconds |
| Started | Jul 11 04:52:31 PM PDT 24 |
| Finished | Jul 11 04:52:43 PM PDT 24 |
| Peak memory | 195788 kb |
| Host | smart-70d26fd3-2fd1-4813-89f7-014ca71ff6fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924334627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi o_csr_rw.1924334627 |
| Directory | /workspace/16.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_intr_test.721520051 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 16099226 ps |
| CPU time | 0.62 seconds |
| Started | Jul 11 04:52:42 PM PDT 24 |
| Finished | Jul 11 04:52:51 PM PDT 24 |
| Peak memory | 195008 kb |
| Host | smart-ffbd183d-8a34-4d4e-b10d-19b74841330b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721520051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.721520051 |
| Directory | /workspace/16.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2065751361 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 218817536 ps |
| CPU time | 0.74 seconds |
| Started | Jul 11 04:52:28 PM PDT 24 |
| Finished | Jul 11 04:52:40 PM PDT 24 |
| Peak memory | 196736 kb |
| Host | smart-85235ae3-01f1-4d0c-ad08-497878c75346 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065751361 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 16.gpio_same_csr_outstanding.2065751361 |
| Directory | /workspace/16.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2569890912 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 376449596 ps |
| CPU time | 2.49 seconds |
| Started | Jul 11 04:52:27 PM PDT 24 |
| Finished | Jul 11 04:52:41 PM PDT 24 |
| Peak memory | 198744 kb |
| Host | smart-150dc65d-b76b-4668-9dff-c5c78deb2e0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569890912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2569890912 |
| Directory | /workspace/16.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.878500105 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 371325698 ps |
| CPU time | 1.18 seconds |
| Started | Jul 11 04:52:26 PM PDT 24 |
| Finished | Jul 11 04:52:39 PM PDT 24 |
| Peak memory | 198324 kb |
| Host | smart-eb8a289f-ca08-477d-a597-3175ff6a7fb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878500105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.gpio_tl_intg_err.878500105 |
| Directory | /workspace/16.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1089950986 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 132272921 ps |
| CPU time | 0.85 seconds |
| Started | Jul 11 04:52:26 PM PDT 24 |
| Finished | Jul 11 04:52:39 PM PDT 24 |
| Peak memory | 198492 kb |
| Host | smart-78477047-49b1-4f99-a421-467e644db004 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089950986 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1089950986 |
| Directory | /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_csr_rw.4016433801 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 30556534 ps |
| CPU time | 0.55 seconds |
| Started | Jul 11 04:52:25 PM PDT 24 |
| Finished | Jul 11 04:52:37 PM PDT 24 |
| Peak memory | 193940 kb |
| Host | smart-ea59baf3-ca6b-461c-bbe4-7f178e90a385 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016433801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi o_csr_rw.4016433801 |
| Directory | /workspace/17.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_intr_test.2931271975 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 47702818 ps |
| CPU time | 0.6 seconds |
| Started | Jul 11 04:52:28 PM PDT 24 |
| Finished | Jul 11 04:52:40 PM PDT 24 |
| Peak memory | 195012 kb |
| Host | smart-af2f6799-fd33-46f1-a42c-f10ebade9a7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931271975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2931271975 |
| Directory | /workspace/17.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3982054603 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 70338385 ps |
| CPU time | 0.82 seconds |
| Started | Jul 11 04:52:27 PM PDT 24 |
| Finished | Jul 11 04:52:40 PM PDT 24 |
| Peak memory | 197016 kb |
| Host | smart-bde4b5d8-f40c-4e37-b217-8f97387af3f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982054603 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 17.gpio_same_csr_outstanding.3982054603 |
| Directory | /workspace/17.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2853366919 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 186558761 ps |
| CPU time | 2.66 seconds |
| Started | Jul 11 04:52:33 PM PDT 24 |
| Finished | Jul 11 04:52:47 PM PDT 24 |
| Peak memory | 198708 kb |
| Host | smart-5759f181-45d9-48e1-aa53-f7ebcb813b59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853366919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2853366919 |
| Directory | /workspace/17.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2584086971 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 99877747 ps |
| CPU time | 1.37 seconds |
| Started | Jul 11 04:52:35 PM PDT 24 |
| Finished | Jul 11 04:52:47 PM PDT 24 |
| Peak memory | 198744 kb |
| Host | smart-0a05b2e8-2dee-419e-ac11-4f0ea606c3d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584086971 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 17.gpio_tl_intg_err.2584086971 |
| Directory | /workspace/17.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.47861734 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 105815168 ps |
| CPU time | 1.35 seconds |
| Started | Jul 11 04:52:28 PM PDT 24 |
| Finished | Jul 11 04:52:41 PM PDT 24 |
| Peak memory | 198816 kb |
| Host | smart-d7166f54-ca8f-4237-a8be-0d896acb29ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47861734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.47861734 |
| Directory | /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_csr_rw.792739174 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 53418932 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:52:27 PM PDT 24 |
| Finished | Jul 11 04:52:40 PM PDT 24 |
| Peak memory | 193868 kb |
| Host | smart-5131138c-7b8b-4f03-a009-a6bbd7a8dd09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792739174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio _csr_rw.792739174 |
| Directory | /workspace/18.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_intr_test.232024677 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 25437975 ps |
| CPU time | 0.61 seconds |
| Started | Jul 11 04:52:27 PM PDT 24 |
| Finished | Jul 11 04:52:40 PM PDT 24 |
| Peak memory | 194248 kb |
| Host | smart-84f8f676-f011-46ef-b410-2c8db70990e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232024677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.232024677 |
| Directory | /workspace/18.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3275951336 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 19744099 ps |
| CPU time | 0.66 seconds |
| Started | Jul 11 04:52:31 PM PDT 24 |
| Finished | Jul 11 04:52:43 PM PDT 24 |
| Peak memory | 195916 kb |
| Host | smart-4015f22a-379d-4d03-a8f9-5feb06b14078 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275951336 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 18.gpio_same_csr_outstanding.3275951336 |
| Directory | /workspace/18.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1614181898 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 99259990 ps |
| CPU time | 1.89 seconds |
| Started | Jul 11 04:52:28 PM PDT 24 |
| Finished | Jul 11 04:52:41 PM PDT 24 |
| Peak memory | 198696 kb |
| Host | smart-a21f9c40-66e8-4f67-b5b8-e40ed38bc64e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614181898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1614181898 |
| Directory | /workspace/18.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3324832528 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 72614580 ps |
| CPU time | 1.02 seconds |
| Started | Jul 11 04:52:28 PM PDT 24 |
| Finished | Jul 11 04:52:41 PM PDT 24 |
| Peak memory | 198556 kb |
| Host | smart-0c8ed222-334e-447a-9f51-68a6ba49babd |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324832528 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3324832528 |
| Directory | /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1961432045 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 40374956 ps |
| CPU time | 0.59 seconds |
| Started | Jul 11 04:52:29 PM PDT 24 |
| Finished | Jul 11 04:52:41 PM PDT 24 |
| Peak memory | 195860 kb |
| Host | smart-a6d2155d-0764-4efb-94f3-0aaa4ab1d95a |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961432045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi o_csr_rw.1961432045 |
| Directory | /workspace/19.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_intr_test.399897558 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 57083832 ps |
| CPU time | 0.68 seconds |
| Started | Jul 11 04:52:33 PM PDT 24 |
| Finished | Jul 11 04:52:45 PM PDT 24 |
| Peak memory | 194432 kb |
| Host | smart-f62a2c7d-1e7a-4b60-9882-49dd18544762 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399897558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.399897558 |
| Directory | /workspace/19.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.4069688225 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 44953722 ps |
| CPU time | 0.77 seconds |
| Started | Jul 11 04:52:40 PM PDT 24 |
| Finished | Jul 11 04:52:50 PM PDT 24 |
| Peak memory | 196664 kb |
| Host | smart-6f596962-7d68-46ce-82b2-5da277812bf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069688225 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 19.gpio_same_csr_outstanding.4069688225 |
| Directory | /workspace/19.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2227716090 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 87818384 ps |
| CPU time | 2.07 seconds |
| Started | Jul 11 04:52:27 PM PDT 24 |
| Finished | Jul 11 04:52:41 PM PDT 24 |
| Peak memory | 198580 kb |
| Host | smart-7dd0bc5b-331b-4477-8b14-a3bbd4b774c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227716090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2227716090 |
| Directory | /workspace/19.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3564917145 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 103138388 ps |
| CPU time | 1.36 seconds |
| Started | Jul 11 04:52:27 PM PDT 24 |
| Finished | Jul 11 04:52:40 PM PDT 24 |
| Peak memory | 198520 kb |
| Host | smart-cef60f42-7b06-467e-a3d8-db860e2892a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564917145 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 19.gpio_tl_intg_err.3564917145 |
| Directory | /workspace/19.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2878876072 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 229228216 ps |
| CPU time | 0.85 seconds |
| Started | Jul 11 04:52:23 PM PDT 24 |
| Finished | Jul 11 04:52:36 PM PDT 24 |
| Peak memory | 196568 kb |
| Host | smart-01486f65-ae16-4b5c-94da-23a714861ce6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878876072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM _TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_aliasing.2878876072 |
| Directory | /workspace/2.gpio_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.504080831 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 264224250 ps |
| CPU time | 3.24 seconds |
| Started | Jul 11 04:52:23 PM PDT 24 |
| Finished | Jul 11 04:52:39 PM PDT 24 |
| Peak memory | 197932 kb |
| Host | smart-ff9fb146-7e3b-41d5-bd43-72fb5c2417af |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504080831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.504080831 |
| Directory | /workspace/2.gpio_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2465367008 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 23809614 ps |
| CPU time | 0.67 seconds |
| Started | Jul 11 04:52:17 PM PDT 24 |
| Finished | Jul 11 04:52:28 PM PDT 24 |
| Peak memory | 195840 kb |
| Host | smart-68a1c467-a4af-4fd2-823a-0aa8e162f6c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465367008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2465367008 |
| Directory | /workspace/2.gpio_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2401094731 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 40901472 ps |
| CPU time | 1.1 seconds |
| Started | Jul 11 04:52:21 PM PDT 24 |
| Finished | Jul 11 04:52:34 PM PDT 24 |
| Peak memory | 198732 kb |
| Host | smart-a38a06ed-06f6-44a4-bc49-1c48adbf3960 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401094731 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2401094731 |
| Directory | /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1842026212 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 145158660 ps |
| CPU time | 0.62 seconds |
| Started | Jul 11 04:52:16 PM PDT 24 |
| Finished | Jul 11 04:52:26 PM PDT 24 |
| Peak memory | 195484 kb |
| Host | smart-78ab9a22-073d-4f70-b327-4a2e3cfb2fc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842026212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio _csr_rw.1842026212 |
| Directory | /workspace/2.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_intr_test.2583356492 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 26040261 ps |
| CPU time | 0.64 seconds |
| Started | Jul 11 04:52:16 PM PDT 24 |
| Finished | Jul 11 04:52:27 PM PDT 24 |
| Peak memory | 195004 kb |
| Host | smart-159d555d-713c-42db-bcfc-d9e89174035e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583356492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2583356492 |
| Directory | /workspace/2.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.309036438 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 16672861 ps |
| CPU time | 0.81 seconds |
| Started | Jul 11 04:52:19 PM PDT 24 |
| Finished | Jul 11 04:52:31 PM PDT 24 |
| Peak memory | 196968 kb |
| Host | smart-a9188bdb-3cec-4527-a804-309a3a96822f |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309036438 -assert nopostproc +UVM_TESTNAME=gpio_bas e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.gpio_same_csr_outstanding.309036438 |
| Directory | /workspace/2.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2214527238 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 131387203 ps |
| CPU time | 2.45 seconds |
| Started | Jul 11 04:52:15 PM PDT 24 |
| Finished | Jul 11 04:52:27 PM PDT 24 |
| Peak memory | 198700 kb |
| Host | smart-0052f461-7dfa-40f8-ba1f-6eb9d491fcd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214527238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2214527238 |
| Directory | /workspace/2.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3640204950 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 355419907 ps |
| CPU time | 0.9 seconds |
| Started | Jul 11 04:52:19 PM PDT 24 |
| Finished | Jul 11 04:52:31 PM PDT 24 |
| Peak memory | 198400 kb |
| Host | smart-812af1e4-1a79-4b27-a2ca-7b9704fa1eec |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640204950 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 2.gpio_tl_intg_err.3640204950 |
| Directory | /workspace/2.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.gpio_intr_test.944848436 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 118834916 ps |
| CPU time | 0.59 seconds |
| Started | Jul 11 04:53:00 PM PDT 24 |
| Finished | Jul 11 04:53:06 PM PDT 24 |
| Peak memory | 194276 kb |
| Host | smart-79675d41-7f65-43d8-b424-2cb63b5e38df |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944848436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.944848436 |
| Directory | /workspace/20.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.gpio_intr_test.1196465653 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 19193443 ps |
| CPU time | 0.65 seconds |
| Started | Jul 11 04:52:32 PM PDT 24 |
| Finished | Jul 11 04:52:43 PM PDT 24 |
| Peak memory | 194416 kb |
| Host | smart-7d6d2082-8421-42e2-a771-5a27a65cc0f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196465653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1196465653 |
| Directory | /workspace/21.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.gpio_intr_test.2394316768 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 18950734 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:52:32 PM PDT 24 |
| Finished | Jul 11 04:52:43 PM PDT 24 |
| Peak memory | 194268 kb |
| Host | smart-4110a74b-f96d-4cf1-9c66-f3d6d13382b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394316768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2394316768 |
| Directory | /workspace/22.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.gpio_intr_test.3170734548 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 14472112 ps |
| CPU time | 0.61 seconds |
| Started | Jul 11 04:52:36 PM PDT 24 |
| Finished | Jul 11 04:52:47 PM PDT 24 |
| Peak memory | 194384 kb |
| Host | smart-707340ff-547f-4f61-bc09-811334e2c8e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170734548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3170734548 |
| Directory | /workspace/23.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.gpio_intr_test.1962099723 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 20874545 ps |
| CPU time | 0.57 seconds |
| Started | Jul 11 04:52:35 PM PDT 24 |
| Finished | Jul 11 04:52:46 PM PDT 24 |
| Peak memory | 194292 kb |
| Host | smart-feb687e3-08f5-4b50-8d7a-163600205064 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962099723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1962099723 |
| Directory | /workspace/24.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.gpio_intr_test.316463646 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 13039771 ps |
| CPU time | 0.61 seconds |
| Started | Jul 11 04:52:36 PM PDT 24 |
| Finished | Jul 11 04:52:46 PM PDT 24 |
| Peak memory | 194948 kb |
| Host | smart-d2655335-dccd-4411-8e4f-1f0a3625aa5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316463646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.316463646 |
| Directory | /workspace/25.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.gpio_intr_test.1543952182 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 18472927 ps |
| CPU time | 0.6 seconds |
| Started | Jul 11 04:52:36 PM PDT 24 |
| Finished | Jul 11 04:52:47 PM PDT 24 |
| Peak memory | 195000 kb |
| Host | smart-599c9393-12fc-4a9d-96a9-0468f661f234 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543952182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1543952182 |
| Directory | /workspace/26.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.gpio_intr_test.1998437473 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 13570065 ps |
| CPU time | 0.59 seconds |
| Started | Jul 11 04:52:33 PM PDT 24 |
| Finished | Jul 11 04:52:44 PM PDT 24 |
| Peak memory | 194976 kb |
| Host | smart-2b791dab-affa-40ca-a9af-132997d13cb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998437473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1998437473 |
| Directory | /workspace/27.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.gpio_intr_test.553409873 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 11028504 ps |
| CPU time | 0.59 seconds |
| Started | Jul 11 04:52:35 PM PDT 24 |
| Finished | Jul 11 04:52:46 PM PDT 24 |
| Peak memory | 194220 kb |
| Host | smart-c918f1e6-efb1-4628-a3b1-9564b1bb8d62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553409873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.553409873 |
| Directory | /workspace/28.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.gpio_intr_test.2204052482 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 52138060 ps |
| CPU time | 0.64 seconds |
| Started | Jul 11 04:52:31 PM PDT 24 |
| Finished | Jul 11 04:52:43 PM PDT 24 |
| Peak memory | 194944 kb |
| Host | smart-2629059a-ce38-46f0-bf49-12b83069ddac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204052482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2204052482 |
| Directory | /workspace/29.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.983466455 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 64400831 ps |
| CPU time | 0.84 seconds |
| Started | Jul 11 04:52:20 PM PDT 24 |
| Finished | Jul 11 04:52:32 PM PDT 24 |
| Peak memory | 196540 kb |
| Host | smart-8155b853-2341-4902-9d01-cb21a96f5059 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983466455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3 .gpio_csr_aliasing.983466455 |
| Directory | /workspace/3.gpio_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3201081851 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 184292665 ps |
| CPU time | 1.65 seconds |
| Started | Jul 11 04:52:20 PM PDT 24 |
| Finished | Jul 11 04:52:33 PM PDT 24 |
| Peak memory | 197724 kb |
| Host | smart-8164bc1c-3eeb-456f-8d0d-dd27011b888a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201081851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3201081851 |
| Directory | /workspace/3.gpio_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.325951105 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 15366038 ps |
| CPU time | 0.63 seconds |
| Started | Jul 11 04:52:17 PM PDT 24 |
| Finished | Jul 11 04:52:28 PM PDT 24 |
| Peak memory | 194912 kb |
| Host | smart-2c9b7c10-aeb2-47dd-9493-bb6be343210f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325951105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.325951105 |
| Directory | /workspace/3.gpio_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1922968761 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 32283469 ps |
| CPU time | 1.61 seconds |
| Started | Jul 11 04:52:20 PM PDT 24 |
| Finished | Jul 11 04:52:34 PM PDT 24 |
| Peak memory | 196088 kb |
| Host | smart-f87e6744-2556-4574-ae07-d52606d01570 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922968761 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1922968761 |
| Directory | /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_rw.632160641 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 51677140 ps |
| CPU time | 0.57 seconds |
| Started | Jul 11 04:52:16 PM PDT 24 |
| Finished | Jul 11 04:52:26 PM PDT 24 |
| Peak memory | 194448 kb |
| Host | smart-e7d5acd2-5bde-4121-b01d-af2d27b9bb03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632160641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_ csr_rw.632160641 |
| Directory | /workspace/3.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_intr_test.2490533058 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 46782948 ps |
| CPU time | 0.63 seconds |
| Started | Jul 11 04:52:18 PM PDT 24 |
| Finished | Jul 11 04:52:29 PM PDT 24 |
| Peak memory | 194408 kb |
| Host | smart-6d22c2c2-d2fb-4ac2-9725-5d41d7f6b779 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490533058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2490533058 |
| Directory | /workspace/3.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.843216133 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 63859003 ps |
| CPU time | 0.83 seconds |
| Started | Jul 11 04:52:21 PM PDT 24 |
| Finished | Jul 11 04:52:34 PM PDT 24 |
| Peak memory | 197108 kb |
| Host | smart-f79bae3b-8f28-4e11-bacc-d9d72abc19a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843216133 -assert nopostproc +UVM_TESTNAME=gpio_bas e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.gpio_same_csr_outstanding.843216133 |
| Directory | /workspace/3.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_tl_errors.94853543 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 184680881 ps |
| CPU time | 3.38 seconds |
| Started | Jul 11 04:52:16 PM PDT 24 |
| Finished | Jul 11 04:52:30 PM PDT 24 |
| Peak memory | 198672 kb |
| Host | smart-33fc8fdf-9a9d-4d01-a74c-3ff757f411eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94853543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.94853543 |
| Directory | /workspace/3.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.4084236972 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 83335976 ps |
| CPU time | 1.15 seconds |
| Started | Jul 11 04:52:17 PM PDT 24 |
| Finished | Jul 11 04:52:28 PM PDT 24 |
| Peak memory | 198980 kb |
| Host | smart-0a5364da-269e-4086-95b7-b29f230840c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084236972 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 3.gpio_tl_intg_err.4084236972 |
| Directory | /workspace/3.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.gpio_intr_test.3154384569 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 64124207 ps |
| CPU time | 0.63 seconds |
| Started | Jul 11 04:52:34 PM PDT 24 |
| Finished | Jul 11 04:52:46 PM PDT 24 |
| Peak memory | 194600 kb |
| Host | smart-782a5c94-6181-42cc-ba0f-1fb0c9301f7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154384569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3154384569 |
| Directory | /workspace/30.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.gpio_intr_test.1443804329 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 15051344 ps |
| CPU time | 0.57 seconds |
| Started | Jul 11 04:52:38 PM PDT 24 |
| Finished | Jul 11 04:52:48 PM PDT 24 |
| Peak memory | 194260 kb |
| Host | smart-7ed1e40c-1f6b-4eb4-baab-652340e24402 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443804329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1443804329 |
| Directory | /workspace/31.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.gpio_intr_test.3440527618 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 14147503 ps |
| CPU time | 0.62 seconds |
| Started | Jul 11 04:52:34 PM PDT 24 |
| Finished | Jul 11 04:52:46 PM PDT 24 |
| Peak memory | 194292 kb |
| Host | smart-e6477a81-a94d-4ed1-adc6-c389199de319 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440527618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3440527618 |
| Directory | /workspace/32.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.gpio_intr_test.3723077728 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 162668627 ps |
| CPU time | 0.68 seconds |
| Started | Jul 11 04:52:35 PM PDT 24 |
| Finished | Jul 11 04:52:46 PM PDT 24 |
| Peak memory | 195000 kb |
| Host | smart-ae00f0bd-25e2-4a2c-a774-bb270e1b1369 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723077728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3723077728 |
| Directory | /workspace/33.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.gpio_intr_test.1515679082 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 31989603 ps |
| CPU time | 0.67 seconds |
| Started | Jul 11 04:52:39 PM PDT 24 |
| Finished | Jul 11 04:52:49 PM PDT 24 |
| Peak memory | 194256 kb |
| Host | smart-74911dc0-79b8-43b3-8d1b-35107b048f94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515679082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1515679082 |
| Directory | /workspace/34.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.gpio_intr_test.2965964550 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 35446524 ps |
| CPU time | 0.61 seconds |
| Started | Jul 11 04:52:35 PM PDT 24 |
| Finished | Jul 11 04:52:46 PM PDT 24 |
| Peak memory | 194304 kb |
| Host | smart-7f5672d8-a37a-4427-8a77-2a860db51af9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965964550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2965964550 |
| Directory | /workspace/35.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.gpio_intr_test.3841187395 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 14421848 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:52:36 PM PDT 24 |
| Finished | Jul 11 04:52:47 PM PDT 24 |
| Peak memory | 194156 kb |
| Host | smart-e66405d2-369b-48a3-8f51-4bc20525a06a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841187395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3841187395 |
| Directory | /workspace/36.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.gpio_intr_test.1564690073 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 15737566 ps |
| CPU time | 0.63 seconds |
| Started | Jul 11 04:52:38 PM PDT 24 |
| Finished | Jul 11 04:52:48 PM PDT 24 |
| Peak memory | 195044 kb |
| Host | smart-92addd74-dae0-41d5-a7f1-a0c476d29124 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564690073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1564690073 |
| Directory | /workspace/37.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.gpio_intr_test.3268514824 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 20360607 ps |
| CPU time | 0.57 seconds |
| Started | Jul 11 04:52:30 PM PDT 24 |
| Finished | Jul 11 04:52:43 PM PDT 24 |
| Peak memory | 194316 kb |
| Host | smart-7c9eb0dd-4281-4a38-8c96-9c3f8b9d1097 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268514824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3268514824 |
| Directory | /workspace/38.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.gpio_intr_test.375461122 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 12792480 ps |
| CPU time | 0.64 seconds |
| Started | Jul 11 04:52:36 PM PDT 24 |
| Finished | Jul 11 04:52:46 PM PDT 24 |
| Peak memory | 194436 kb |
| Host | smart-04365892-b8c9-4984-a801-d430c4c13b96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375461122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.375461122 |
| Directory | /workspace/39.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2181655191 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 72349123 ps |
| CPU time | 0.72 seconds |
| Started | Jul 11 04:52:15 PM PDT 24 |
| Finished | Jul 11 04:52:25 PM PDT 24 |
| Peak memory | 194708 kb |
| Host | smart-9db04168-862d-44dc-81e7-92c60bd0315c |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181655191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM _TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_aliasing.2181655191 |
| Directory | /workspace/4.gpio_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2631132939 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 286920276 ps |
| CPU time | 2.12 seconds |
| Started | Jul 11 04:52:14 PM PDT 24 |
| Finished | Jul 11 04:52:24 PM PDT 24 |
| Peak memory | 197592 kb |
| Host | smart-677569cd-b581-497f-9961-b4749583d89e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631132939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2631132939 |
| Directory | /workspace/4.gpio_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.738267494 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 24402716 ps |
| CPU time | 0.65 seconds |
| Started | Jul 11 04:52:16 PM PDT 24 |
| Finished | Jul 11 04:52:27 PM PDT 24 |
| Peak memory | 195248 kb |
| Host | smart-86263862-4aed-4db6-a8e1-94eb7e6775ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738267494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.738267494 |
| Directory | /workspace/4.gpio_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.180642699 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 22045094 ps |
| CPU time | 0.98 seconds |
| Started | Jul 11 04:52:17 PM PDT 24 |
| Finished | Jul 11 04:52:28 PM PDT 24 |
| Peak memory | 198808 kb |
| Host | smart-c7490df9-2128-49f1-b33b-aeddb1fc21cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180642699 -asser t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.180642699 |
| Directory | /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3760195421 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 54083106 ps |
| CPU time | 0.61 seconds |
| Started | Jul 11 04:52:17 PM PDT 24 |
| Finished | Jul 11 04:52:28 PM PDT 24 |
| Peak memory | 195444 kb |
| Host | smart-f0083abc-9c8d-4195-9a98-4465b4d2cb32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760195421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio _csr_rw.3760195421 |
| Directory | /workspace/4.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_intr_test.2690898259 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 35476320 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:52:16 PM PDT 24 |
| Finished | Jul 11 04:52:27 PM PDT 24 |
| Peak memory | 194284 kb |
| Host | smart-01177426-678f-49bf-944c-263f02841e30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690898259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2690898259 |
| Directory | /workspace/4.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2872041031 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 112633383 ps |
| CPU time | 0.76 seconds |
| Started | Jul 11 04:52:24 PM PDT 24 |
| Finished | Jul 11 04:52:37 PM PDT 24 |
| Peak memory | 196632 kb |
| Host | smart-25a1559b-cad0-4ee1-9154-220525c267d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872041031 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.gpio_same_csr_outstanding.2872041031 |
| Directory | /workspace/4.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3831614645 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 223961931 ps |
| CPU time | 2.16 seconds |
| Started | Jul 11 04:52:17 PM PDT 24 |
| Finished | Jul 11 04:52:30 PM PDT 24 |
| Peak memory | 198572 kb |
| Host | smart-5fe39cb0-cf76-492d-b5a9-5c9da909d9bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831614645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3831614645 |
| Directory | /workspace/4.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2344733312 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 368951337 ps |
| CPU time | 1.36 seconds |
| Started | Jul 11 04:52:16 PM PDT 24 |
| Finished | Jul 11 04:52:28 PM PDT 24 |
| Peak memory | 198592 kb |
| Host | smart-6667193a-875e-4429-bc48-864c7d5886ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344733312 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 4.gpio_tl_intg_err.2344733312 |
| Directory | /workspace/4.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.gpio_intr_test.2267444150 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 38554944 ps |
| CPU time | 0.57 seconds |
| Started | Jul 11 04:52:36 PM PDT 24 |
| Finished | Jul 11 04:52:47 PM PDT 24 |
| Peak memory | 194112 kb |
| Host | smart-7169e967-2673-4082-bcb6-2208c4f675ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267444150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2267444150 |
| Directory | /workspace/40.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.gpio_intr_test.2528011955 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 41047211 ps |
| CPU time | 0.62 seconds |
| Started | Jul 11 04:52:39 PM PDT 24 |
| Finished | Jul 11 04:52:49 PM PDT 24 |
| Peak memory | 194888 kb |
| Host | smart-cb61cfa6-dae8-4e89-9b98-e1f12503e602 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528011955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2528011955 |
| Directory | /workspace/41.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.gpio_intr_test.1597555327 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 12517668 ps |
| CPU time | 0.64 seconds |
| Started | Jul 11 04:52:34 PM PDT 24 |
| Finished | Jul 11 04:52:46 PM PDT 24 |
| Peak memory | 194832 kb |
| Host | smart-562133d8-ec2b-4b53-beab-c2cbab236d2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597555327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1597555327 |
| Directory | /workspace/42.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.gpio_intr_test.2940919685 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 32078357 ps |
| CPU time | 0.59 seconds |
| Started | Jul 11 04:52:38 PM PDT 24 |
| Finished | Jul 11 04:52:49 PM PDT 24 |
| Peak memory | 194892 kb |
| Host | smart-d370c7b1-892d-48a6-b980-5138c489556a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940919685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2940919685 |
| Directory | /workspace/43.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.gpio_intr_test.1349495694 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 29603873 ps |
| CPU time | 0.63 seconds |
| Started | Jul 11 04:52:35 PM PDT 24 |
| Finished | Jul 11 04:52:46 PM PDT 24 |
| Peak memory | 194328 kb |
| Host | smart-7932815a-d183-4e9b-a051-4d3b5650f60d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349495694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1349495694 |
| Directory | /workspace/44.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.gpio_intr_test.1827986348 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 26262899 ps |
| CPU time | 0.6 seconds |
| Started | Jul 11 04:52:33 PM PDT 24 |
| Finished | Jul 11 04:52:45 PM PDT 24 |
| Peak memory | 194324 kb |
| Host | smart-ac1599ff-8734-41d6-82f5-0e9907019ef1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827986348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1827986348 |
| Directory | /workspace/45.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.gpio_intr_test.4065441037 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 39206337 ps |
| CPU time | 0.59 seconds |
| Started | Jul 11 04:52:35 PM PDT 24 |
| Finished | Jul 11 04:52:46 PM PDT 24 |
| Peak memory | 194304 kb |
| Host | smart-1d048463-fa54-419b-a245-0629b6b2383a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065441037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.4065441037 |
| Directory | /workspace/46.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.gpio_intr_test.2524419661 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 175495747 ps |
| CPU time | 0.61 seconds |
| Started | Jul 11 04:52:36 PM PDT 24 |
| Finished | Jul 11 04:52:47 PM PDT 24 |
| Peak memory | 194200 kb |
| Host | smart-9f6ac315-03c0-481f-9241-37ee30554ce6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524419661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2524419661 |
| Directory | /workspace/47.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.gpio_intr_test.657973227 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 239070096 ps |
| CPU time | 0.61 seconds |
| Started | Jul 11 04:52:32 PM PDT 24 |
| Finished | Jul 11 04:52:44 PM PDT 24 |
| Peak memory | 194392 kb |
| Host | smart-d73bac11-3130-49b4-87d6-43e4ef58eeb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657973227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.657973227 |
| Directory | /workspace/48.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.gpio_intr_test.621430771 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 32241375 ps |
| CPU time | 0.62 seconds |
| Started | Jul 11 04:52:37 PM PDT 24 |
| Finished | Jul 11 04:52:47 PM PDT 24 |
| Peak memory | 194292 kb |
| Host | smart-baae6f1d-36c2-4f7b-9488-611d38ae746d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621430771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.621430771 |
| Directory | /workspace/49.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3286353563 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 14924423 ps |
| CPU time | 0.78 seconds |
| Started | Jul 11 04:52:14 PM PDT 24 |
| Finished | Jul 11 04:52:23 PM PDT 24 |
| Peak memory | 198412 kb |
| Host | smart-3e56e462-c6ae-4654-af99-9c31152fafbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286353563 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3286353563 |
| Directory | /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_csr_rw.492914608 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 19570255 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:52:24 PM PDT 24 |
| Finished | Jul 11 04:52:37 PM PDT 24 |
| Peak memory | 194940 kb |
| Host | smart-75c3539f-fa01-4b38-b5f6-0333f1ccb6ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492914608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_ csr_rw.492914608 |
| Directory | /workspace/5.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_intr_test.3577162472 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 57211299 ps |
| CPU time | 0.61 seconds |
| Started | Jul 11 04:52:17 PM PDT 24 |
| Finished | Jul 11 04:52:29 PM PDT 24 |
| Peak memory | 194264 kb |
| Host | smart-3bfc422b-8940-459c-a324-b755a0dc78e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577162472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3577162472 |
| Directory | /workspace/5.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2240069604 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 112684227 ps |
| CPU time | 0.78 seconds |
| Started | Jul 11 04:52:14 PM PDT 24 |
| Finished | Jul 11 04:52:22 PM PDT 24 |
| Peak memory | 197428 kb |
| Host | smart-46522ff1-e4f5-403d-92cf-40e5838deae2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240069604 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 5.gpio_same_csr_outstanding.2240069604 |
| Directory | /workspace/5.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2275381659 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 119250853 ps |
| CPU time | 2.07 seconds |
| Started | Jul 11 04:52:19 PM PDT 24 |
| Finished | Jul 11 04:52:32 PM PDT 24 |
| Peak memory | 198576 kb |
| Host | smart-0f4cf572-210c-4336-9327-c9de100188af |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275381659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2275381659 |
| Directory | /workspace/5.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.509720695 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 126247078 ps |
| CPU time | 1.4 seconds |
| Started | Jul 11 04:52:21 PM PDT 24 |
| Finished | Jul 11 04:52:35 PM PDT 24 |
| Peak memory | 198704 kb |
| Host | smart-5fadf071-6d01-4925-b078-bbf96effe8a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509720695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.gpio_tl_intg_err.509720695 |
| Directory | /workspace/5.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.61197294 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 34385471 ps |
| CPU time | 0.88 seconds |
| Started | Jul 11 04:52:23 PM PDT 24 |
| Finished | Jul 11 04:52:36 PM PDT 24 |
| Peak memory | 198436 kb |
| Host | smart-694ea974-2c0e-415f-b5a0-30d111296cf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61197294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.61197294 |
| Directory | /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2671846261 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 30490318 ps |
| CPU time | 0.6 seconds |
| Started | Jul 11 04:52:13 PM PDT 24 |
| Finished | Jul 11 04:52:22 PM PDT 24 |
| Peak memory | 195608 kb |
| Host | smart-1ab13df8-990c-454f-b3ed-30ebb0bcac92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671846261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio _csr_rw.2671846261 |
| Directory | /workspace/6.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_intr_test.3808718071 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 39958249 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:52:16 PM PDT 24 |
| Finished | Jul 11 04:52:25 PM PDT 24 |
| Peak memory | 194228 kb |
| Host | smart-ff848ceb-ea9a-427d-83b4-19fff17ac046 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808718071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3808718071 |
| Directory | /workspace/6.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.4105576970 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 19142018 ps |
| CPU time | 0.62 seconds |
| Started | Jul 11 04:52:17 PM PDT 24 |
| Finished | Jul 11 04:52:29 PM PDT 24 |
| Peak memory | 195192 kb |
| Host | smart-db6bbb35-17ca-4fee-8a53-24e0addc2ada |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105576970 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 6.gpio_same_csr_outstanding.4105576970 |
| Directory | /workspace/6.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2973271101 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 60256171 ps |
| CPU time | 3.06 seconds |
| Started | Jul 11 04:52:19 PM PDT 24 |
| Finished | Jul 11 04:52:33 PM PDT 24 |
| Peak memory | 198684 kb |
| Host | smart-a7e9e535-f3ac-469c-a7f6-20b820f822b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973271101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2973271101 |
| Directory | /workspace/6.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.671399971 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 30467538 ps |
| CPU time | 0.8 seconds |
| Started | Jul 11 04:55:09 PM PDT 24 |
| Finished | Jul 11 04:55:13 PM PDT 24 |
| Peak memory | 198496 kb |
| Host | smart-5530be3d-89b5-4cda-8803-5b2e136f99c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671399971 -asser t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.671399971 |
| Directory | /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3386710016 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 23563125 ps |
| CPU time | 0.63 seconds |
| Started | Jul 11 04:52:21 PM PDT 24 |
| Finished | Jul 11 04:52:34 PM PDT 24 |
| Peak memory | 196064 kb |
| Host | smart-c11f85b4-403e-4fd8-9b47-ebbf06d5465a |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386710016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio _csr_rw.3386710016 |
| Directory | /workspace/7.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_intr_test.173620236 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 18157271 ps |
| CPU time | 0.65 seconds |
| Started | Jul 11 04:52:19 PM PDT 24 |
| Finished | Jul 11 04:52:31 PM PDT 24 |
| Peak memory | 194256 kb |
| Host | smart-32790eac-6b71-49a1-8d20-752a6a71db1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173620236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.173620236 |
| Directory | /workspace/7.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2172368194 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 23410196 ps |
| CPU time | 0.83 seconds |
| Started | Jul 11 04:52:21 PM PDT 24 |
| Finished | Jul 11 04:52:34 PM PDT 24 |
| Peak memory | 197088 kb |
| Host | smart-2d6a3e28-0761-4d52-b1e2-0270b88c6d51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172368194 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 7.gpio_same_csr_outstanding.2172368194 |
| Directory | /workspace/7.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2102616155 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 448199876 ps |
| CPU time | 1.87 seconds |
| Started | Jul 11 04:52:17 PM PDT 24 |
| Finished | Jul 11 04:52:29 PM PDT 24 |
| Peak memory | 198748 kb |
| Host | smart-f33b8eb2-d0e4-43a9-980b-f55180935ce1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102616155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2102616155 |
| Directory | /workspace/7.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1773423451 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 133343433 ps |
| CPU time | 1.37 seconds |
| Started | Jul 11 04:52:26 PM PDT 24 |
| Finished | Jul 11 04:52:40 PM PDT 24 |
| Peak memory | 198700 kb |
| Host | smart-ad43586c-a5b6-4f43-bc24-68131a588066 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773423451 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 7.gpio_tl_intg_err.1773423451 |
| Directory | /workspace/7.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2424413900 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 61473326 ps |
| CPU time | 0.72 seconds |
| Started | Jul 11 04:54:08 PM PDT 24 |
| Finished | Jul 11 04:54:18 PM PDT 24 |
| Peak memory | 198424 kb |
| Host | smart-47d746f0-dc23-4e15-9604-3209caf816cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424413900 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2424413900 |
| Directory | /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3796997178 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 12892024 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:52:16 PM PDT 24 |
| Finished | Jul 11 04:52:26 PM PDT 24 |
| Peak memory | 194004 kb |
| Host | smart-bb3753c8-dcbe-4a9f-918b-c1c7430ac977 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796997178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio _csr_rw.3796997178 |
| Directory | /workspace/8.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_intr_test.2372797888 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 187571542 ps |
| CPU time | 0.59 seconds |
| Started | Jul 11 04:52:20 PM PDT 24 |
| Finished | Jul 11 04:52:32 PM PDT 24 |
| Peak memory | 194272 kb |
| Host | smart-d9d28242-d9c6-442f-8cf3-ef900c55f0ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372797888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2372797888 |
| Directory | /workspace/8.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.572328535 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 21087074 ps |
| CPU time | 0.83 seconds |
| Started | Jul 11 04:52:15 PM PDT 24 |
| Finished | Jul 11 04:52:26 PM PDT 24 |
| Peak memory | 197584 kb |
| Host | smart-ce278988-f0d3-49f3-bd51-1052f7e99f01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572328535 -assert nopostproc +UVM_TESTNAME=gpio_bas e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 8.gpio_same_csr_outstanding.572328535 |
| Directory | /workspace/8.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2594185941 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 144733295 ps |
| CPU time | 1.97 seconds |
| Started | Jul 11 04:52:23 PM PDT 24 |
| Finished | Jul 11 04:52:37 PM PDT 24 |
| Peak memory | 198592 kb |
| Host | smart-fa492c0f-3b1d-422c-8786-f6e84bb8792c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594185941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2594185941 |
| Directory | /workspace/8.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.508009244 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 41689798 ps |
| CPU time | 0.84 seconds |
| Started | Jul 11 04:52:20 PM PDT 24 |
| Finished | Jul 11 04:52:31 PM PDT 24 |
| Peak memory | 197720 kb |
| Host | smart-c89ece23-eaa2-4e11-9c73-61e58ee19c30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508009244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.gpio_tl_intg_err.508009244 |
| Directory | /workspace/8.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3998738404 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 52282197 ps |
| CPU time | 0.67 seconds |
| Started | Jul 11 04:52:25 PM PDT 24 |
| Finished | Jul 11 04:52:38 PM PDT 24 |
| Peak memory | 197532 kb |
| Host | smart-0aaeb94f-6ac5-4996-9aff-fe49d097e898 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998738404 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3998738404 |
| Directory | /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1817521155 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 18375271 ps |
| CPU time | 0.63 seconds |
| Started | Jul 11 04:52:20 PM PDT 24 |
| Finished | Jul 11 04:52:33 PM PDT 24 |
| Peak memory | 195192 kb |
| Host | smart-e5dc07bb-c00f-4bea-8572-8d0b9ac5e277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817521155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio _csr_rw.1817521155 |
| Directory | /workspace/9.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_intr_test.1277068002 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 14693534 ps |
| CPU time | 0.6 seconds |
| Started | Jul 11 04:52:23 PM PDT 24 |
| Finished | Jul 11 04:52:36 PM PDT 24 |
| Peak memory | 194288 kb |
| Host | smart-1fa76d45-57d9-4001-8e73-71313d1e63f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277068002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1277068002 |
| Directory | /workspace/9.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2798703582 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 162442195 ps |
| CPU time | 0.82 seconds |
| Started | Jul 11 04:52:21 PM PDT 24 |
| Finished | Jul 11 04:52:34 PM PDT 24 |
| Peak memory | 197600 kb |
| Host | smart-323e451f-1c0b-46d1-a774-9acbef552958 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798703582 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 9.gpio_same_csr_outstanding.2798703582 |
| Directory | /workspace/9.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1053478164 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 2186586210 ps |
| CPU time | 2.92 seconds |
| Started | Jul 11 04:52:24 PM PDT 24 |
| Finished | Jul 11 04:52:39 PM PDT 24 |
| Peak memory | 198632 kb |
| Host | smart-80f55443-bec1-4c4e-a0d5-6736c0f53dd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053478164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1053478164 |
| Directory | /workspace/9.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1757512634 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 69296911 ps |
| CPU time | 1.16 seconds |
| Started | Jul 11 04:52:32 PM PDT 24 |
| Finished | Jul 11 04:52:44 PM PDT 24 |
| Peak memory | 198672 kb |
| Host | smart-0fc35dfd-bafb-47f4-9b4d-af63f1de711a |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757512634 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 9.gpio_tl_intg_err.1757512634 |
| Directory | /workspace/9.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.gpio_alert_test.2585264881 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 20643599 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:29:50 PM PDT 24 |
| Finished | Jul 11 04:29:53 PM PDT 24 |
| Peak memory | 194572 kb |
| Host | smart-b5cd866e-99bc-436d-8dcd-e357f37f0e8f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585264881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2585264881 |
| Directory | /workspace/0.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1202668406 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 95626278 ps |
| CPU time | 0.71 seconds |
| Started | Jul 11 04:29:23 PM PDT 24 |
| Finished | Jul 11 04:29:26 PM PDT 24 |
| Peak memory | 195508 kb |
| Host | smart-2dd72832-7a21-43ec-8e2f-c1c47bf81a5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1202668406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1202668406 |
| Directory | /workspace/0.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/0.gpio_filter_stress.1225830957 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 721600068 ps |
| CPU time | 23.44 seconds |
| Started | Jul 11 04:30:00 PM PDT 24 |
| Finished | Jul 11 04:30:33 PM PDT 24 |
| Peak memory | 198524 kb |
| Host | smart-77bf8305-4940-4456-94d4-03834417895b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225830957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres s.1225830957 |
| Directory | /workspace/0.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/0.gpio_full_random.1762181889 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 229954068 ps |
| CPU time | 0.83 seconds |
| Started | Jul 11 04:29:53 PM PDT 24 |
| Finished | Jul 11 04:29:58 PM PDT 24 |
| Peak memory | 197104 kb |
| Host | smart-f40fe470-ccf5-423d-8343-94d841075c99 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762181889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1762181889 |
| Directory | /workspace/0.gpio_full_random/latest |
| Test location | /workspace/coverage/default/0.gpio_intr_rand_pgm.1914046162 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 165691083 ps |
| CPU time | 1.33 seconds |
| Started | Jul 11 04:29:52 PM PDT 24 |
| Finished | Jul 11 04:29:57 PM PDT 24 |
| Peak memory | 197648 kb |
| Host | smart-f53f2b22-bb3d-4259-bb34-116dba374667 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914046162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1914046162 |
| Directory | /workspace/0.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1838836752 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 145151947 ps |
| CPU time | 2.94 seconds |
| Started | Jul 11 04:29:38 PM PDT 24 |
| Finished | Jul 11 04:29:43 PM PDT 24 |
| Peak memory | 198592 kb |
| Host | smart-281c83e6-8a4e-4ce8-a92e-198773100687 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838836752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1838836752 |
| Directory | /workspace/0.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/0.gpio_rand_intr_trigger.2025398350 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 441970622 ps |
| CPU time | 2.1 seconds |
| Started | Jul 11 04:29:58 PM PDT 24 |
| Finished | Jul 11 04:30:07 PM PDT 24 |
| Peak memory | 198672 kb |
| Host | smart-357ea6d3-fcd6-4f86-aebf-63d093cc731b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025398350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger. 2025398350 |
| Directory | /workspace/0.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/0.gpio_random_dout_din.3099225845 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 213385501 ps |
| CPU time | 0.86 seconds |
| Started | Jul 11 04:30:04 PM PDT 24 |
| Finished | Jul 11 04:30:14 PM PDT 24 |
| Peak memory | 197124 kb |
| Host | smart-286eb893-3b9f-4f22-9bb1-f5bd28f9ae23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3099225845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3099225845 |
| Directory | /workspace/0.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1765575545 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 44360047 ps |
| CPU time | 0.89 seconds |
| Started | Jul 11 04:29:55 PM PDT 24 |
| Finished | Jul 11 04:30:01 PM PDT 24 |
| Peak memory | 196544 kb |
| Host | smart-0580fd28-029a-4b42-b009-dc98268424e5 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765575545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup _pulldown.1765575545 |
| Directory | /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1708849698 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 417735423 ps |
| CPU time | 4.42 seconds |
| Started | Jul 11 04:30:09 PM PDT 24 |
| Finished | Jul 11 04:30:21 PM PDT 24 |
| Peak memory | 198508 kb |
| Host | smart-c5b52019-53eb-4d6a-baf6-29b8651700f9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708849698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran dom_long_reg_writes_reg_reads.1708849698 |
| Directory | /workspace/0.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/0.gpio_sec_cm.2029655266 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 831377650 ps |
| CPU time | 0.92 seconds |
| Started | Jul 11 04:29:45 PM PDT 24 |
| Finished | Jul 11 04:29:48 PM PDT 24 |
| Peak memory | 215324 kb |
| Host | smart-3aae1f7f-0891-4a31-8d78-676ea0d879bd |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029655266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2029655266 |
| Directory | /workspace/0.gpio_sec_cm/latest |
| Test location | /workspace/coverage/default/0.gpio_smoke.1438203374 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 93072440 ps |
| CPU time | 1.23 seconds |
| Started | Jul 11 04:30:01 PM PDT 24 |
| Finished | Jul 11 04:30:11 PM PDT 24 |
| Peak memory | 198504 kb |
| Host | smart-ac9a0718-44de-478f-b301-ab74129614e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1438203374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1438203374 |
| Directory | /workspace/0.gpio_smoke/latest |
| Test location | /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.944625409 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 79421421 ps |
| CPU time | 1.21 seconds |
| Started | Jul 11 04:29:58 PM PDT 24 |
| Finished | Jul 11 04:30:06 PM PDT 24 |
| Peak memory | 197868 kb |
| Host | smart-b0e14a17-dd44-4485-8df6-193319886bf6 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944625409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.944625409 |
| Directory | /workspace/0.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/0.gpio_stress_all.2630157169 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1205371737 ps |
| CPU time | 25.82 seconds |
| Started | Jul 11 04:29:48 PM PDT 24 |
| Finished | Jul 11 04:30:16 PM PDT 24 |
| Peak memory | 198512 kb |
| Host | smart-4e164eed-035f-4d89-86f4-01c211f932e4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630157169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g pio_stress_all.2630157169 |
| Directory | /workspace/0.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/1.gpio_alert_test.3414642591 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 15434940 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:29:58 PM PDT 24 |
| Finished | Jul 11 04:30:06 PM PDT 24 |
| Peak memory | 194676 kb |
| Host | smart-815d39e8-105b-4f9e-9181-7300b1948478 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414642591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3414642591 |
| Directory | /workspace/1.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1479687377 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 22151356 ps |
| CPU time | 0.69 seconds |
| Started | Jul 11 04:29:58 PM PDT 24 |
| Finished | Jul 11 04:30:06 PM PDT 24 |
| Peak memory | 194628 kb |
| Host | smart-913e9154-2d1d-49c2-b87a-57a563bbe667 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1479687377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1479687377 |
| Directory | /workspace/1.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/1.gpio_filter_stress.622351510 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 2026863198 ps |
| CPU time | 29.67 seconds |
| Started | Jul 11 04:29:43 PM PDT 24 |
| Finished | Jul 11 04:30:14 PM PDT 24 |
| Peak memory | 198540 kb |
| Host | smart-e2368e00-3221-46ac-9031-ab354aeb26c5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622351510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress .622351510 |
| Directory | /workspace/1.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/1.gpio_full_random.3154618805 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 86908598 ps |
| CPU time | 0.68 seconds |
| Started | Jul 11 04:29:46 PM PDT 24 |
| Finished | Jul 11 04:29:49 PM PDT 24 |
| Peak memory | 195864 kb |
| Host | smart-d335fd74-6364-4e78-8cfe-2f86bf9b8231 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154618805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3154618805 |
| Directory | /workspace/1.gpio_full_random/latest |
| Test location | /workspace/coverage/default/1.gpio_intr_rand_pgm.630069515 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 79166600 ps |
| CPU time | 1.32 seconds |
| Started | Jul 11 04:29:49 PM PDT 24 |
| Finished | Jul 11 04:29:52 PM PDT 24 |
| Peak memory | 197768 kb |
| Host | smart-950a7853-b314-46a3-bfa6-1764fe65a1ee |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630069515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.630069515 |
| Directory | /workspace/1.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.636156084 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 238239174 ps |
| CPU time | 2.46 seconds |
| Started | Jul 11 04:29:37 PM PDT 24 |
| Finished | Jul 11 04:29:42 PM PDT 24 |
| Peak memory | 198296 kb |
| Host | smart-2bb82a5e-4fdf-4d21-bb4a-ae850e57326f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636156084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.gpio_intr_with_filter_rand_intr_event.636156084 |
| Directory | /workspace/1.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/1.gpio_rand_intr_trigger.124602471 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 571997285 ps |
| CPU time | 2.64 seconds |
| Started | Jul 11 04:30:02 PM PDT 24 |
| Finished | Jul 11 04:30:13 PM PDT 24 |
| Peak memory | 198596 kb |
| Host | smart-493de79b-6aab-446b-a0a8-6083e45d37a1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124602471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.124602471 |
| Directory | /workspace/1.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/1.gpio_random_dout_din.1783704843 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 19405507 ps |
| CPU time | 0.63 seconds |
| Started | Jul 11 04:29:48 PM PDT 24 |
| Finished | Jul 11 04:29:50 PM PDT 24 |
| Peak memory | 194940 kb |
| Host | smart-c6cb6d1a-4eeb-4ee4-ae59-e1a4f93b7ae1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1783704843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1783704843 |
| Directory | /workspace/1.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2265880573 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 19147577 ps |
| CPU time | 0.69 seconds |
| Started | Jul 11 04:29:24 PM PDT 24 |
| Finished | Jul 11 04:29:28 PM PDT 24 |
| Peak memory | 195916 kb |
| Host | smart-ac9e58f1-3ddc-4c17-8719-62c835195fbb |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265880573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup _pulldown.2265880573 |
| Directory | /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3890451895 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 21870445 ps |
| CPU time | 1.11 seconds |
| Started | Jul 11 04:29:28 PM PDT 24 |
| Finished | Jul 11 04:29:36 PM PDT 24 |
| Peak memory | 197452 kb |
| Host | smart-202858a2-4f6b-4c70-b082-b40c22120443 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890451895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran dom_long_reg_writes_reg_reads.3890451895 |
| Directory | /workspace/1.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/1.gpio_smoke.1931623959 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 68642966 ps |
| CPU time | 1.25 seconds |
| Started | Jul 11 04:29:25 PM PDT 24 |
| Finished | Jul 11 04:29:28 PM PDT 24 |
| Peak memory | 197428 kb |
| Host | smart-42054909-51fd-4c4c-a356-13840aea63cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1931623959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.1931623959 |
| Directory | /workspace/1.gpio_smoke/latest |
| Test location | /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.722460890 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 173594679 ps |
| CPU time | 1.33 seconds |
| Started | Jul 11 04:29:40 PM PDT 24 |
| Finished | Jul 11 04:29:44 PM PDT 24 |
| Peak memory | 197384 kb |
| Host | smart-8f80ab5b-ea43-4b6e-8ace-a84ee2d1e029 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722460890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.722460890 |
| Directory | /workspace/1.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/1.gpio_stress_all.445730686 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 6363725666 ps |
| CPU time | 70.12 seconds |
| Started | Jul 11 04:29:47 PM PDT 24 |
| Finished | Jul 11 04:30:59 PM PDT 24 |
| Peak memory | 198636 kb |
| Host | smart-e757b2dc-afa5-41d4-99c6-e39866bddfff |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445730686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp io_stress_all.445730686 |
| Directory | /workspace/1.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/10.gpio_alert_test.2121058626 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 19514783 ps |
| CPU time | 0.55 seconds |
| Started | Jul 11 04:29:59 PM PDT 24 |
| Finished | Jul 11 04:30:07 PM PDT 24 |
| Peak memory | 194632 kb |
| Host | smart-060d739b-26fb-4943-a0a9-ed988f122d2c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121058626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2121058626 |
| Directory | /workspace/10.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.987054005 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 27412407 ps |
| CPU time | 0.61 seconds |
| Started | Jul 11 04:29:58 PM PDT 24 |
| Finished | Jul 11 04:30:07 PM PDT 24 |
| Peak memory | 195256 kb |
| Host | smart-f3d1e5ab-0a4a-4cb9-a74e-c51f2d15a2d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=987054005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.987054005 |
| Directory | /workspace/10.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/10.gpio_filter_stress.3130346278 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 359106932 ps |
| CPU time | 17.59 seconds |
| Started | Jul 11 04:29:58 PM PDT 24 |
| Finished | Jul 11 04:30:23 PM PDT 24 |
| Peak memory | 197400 kb |
| Host | smart-3f1d82d1-6ec9-4e89-994a-dbeb4527553a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130346278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre ss.3130346278 |
| Directory | /workspace/10.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/10.gpio_full_random.584237996 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 735159150 ps |
| CPU time | 0.88 seconds |
| Started | Jul 11 04:30:48 PM PDT 24 |
| Finished | Jul 11 04:30:51 PM PDT 24 |
| Peak memory | 197660 kb |
| Host | smart-455fa57b-b857-4206-931e-5aac6732ab53 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584237996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.584237996 |
| Directory | /workspace/10.gpio_full_random/latest |
| Test location | /workspace/coverage/default/10.gpio_intr_rand_pgm.2600584961 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 37292596 ps |
| CPU time | 0.82 seconds |
| Started | Jul 11 04:29:55 PM PDT 24 |
| Finished | Jul 11 04:30:01 PM PDT 24 |
| Peak memory | 195912 kb |
| Host | smart-6d67f3f1-757c-4d81-bb30-cfde8bc1544e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600584961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2600584961 |
| Directory | /workspace/10.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.4144581021 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 28161885 ps |
| CPU time | 1.16 seconds |
| Started | Jul 11 04:30:00 PM PDT 24 |
| Finished | Jul 11 04:30:10 PM PDT 24 |
| Peak memory | 198344 kb |
| Host | smart-cf5a15e8-0f24-42bb-ad61-112a278e62c1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144581021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.gpio_intr_with_filter_rand_intr_event.4144581021 |
| Directory | /workspace/10.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/10.gpio_rand_intr_trigger.2160491500 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 91550420 ps |
| CPU time | 2.05 seconds |
| Started | Jul 11 04:30:50 PM PDT 24 |
| Finished | Jul 11 04:30:57 PM PDT 24 |
| Peak memory | 198672 kb |
| Host | smart-c77a96ac-580f-4c80-a6b1-5542c99c858b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160491500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger .2160491500 |
| Directory | /workspace/10.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/10.gpio_random_dout_din.2543363440 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 309565689 ps |
| CPU time | 1.12 seconds |
| Started | Jul 11 04:30:48 PM PDT 24 |
| Finished | Jul 11 04:30:52 PM PDT 24 |
| Peak memory | 196528 kb |
| Host | smart-601fcd0c-767e-41a2-8281-4f186f7b70b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2543363440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2543363440 |
| Directory | /workspace/10.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.493602221 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 17168270 ps |
| CPU time | 0.63 seconds |
| Started | Jul 11 04:29:58 PM PDT 24 |
| Finished | Jul 11 04:30:07 PM PDT 24 |
| Peak memory | 194980 kb |
| Host | smart-88a99317-9bba-40a0-b77f-4d9485958949 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493602221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup _pulldown.493602221 |
| Directory | /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.2344478483 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 377256336 ps |
| CPU time | 2.02 seconds |
| Started | Jul 11 04:30:43 PM PDT 24 |
| Finished | Jul 11 04:30:48 PM PDT 24 |
| Peak memory | 198548 kb |
| Host | smart-7bbe6f13-48dd-4e8f-b77a-7385a342b9ae |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344478483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra ndom_long_reg_writes_reg_reads.2344478483 |
| Directory | /workspace/10.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/10.gpio_smoke.3133524272 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 243800392 ps |
| CPU time | 0.83 seconds |
| Started | Jul 11 04:30:11 PM PDT 24 |
| Finished | Jul 11 04:30:18 PM PDT 24 |
| Peak memory | 197840 kb |
| Host | smart-0e4d2798-0ff8-4f22-9bc9-6df10f948cd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3133524272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3133524272 |
| Directory | /workspace/10.gpio_smoke/latest |
| Test location | /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3379796299 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 86214749 ps |
| CPU time | 0.93 seconds |
| Started | Jul 11 04:29:59 PM PDT 24 |
| Finished | Jul 11 04:30:08 PM PDT 24 |
| Peak memory | 195872 kb |
| Host | smart-d7df0346-7017-47ea-93c5-c2a2dca93b59 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379796299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3379796299 |
| Directory | /workspace/10.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/10.gpio_stress_all.1450467832 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 8179455873 ps |
| CPU time | 22.04 seconds |
| Started | Jul 11 04:30:15 PM PDT 24 |
| Finished | Jul 11 04:30:47 PM PDT 24 |
| Peak memory | 198756 kb |
| Host | smart-261470c8-c0b7-4770-a598-5b65d8a67b28 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450467832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. gpio_stress_all.1450467832 |
| Directory | /workspace/10.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/11.gpio_alert_test.1439426866 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 45458829 ps |
| CPU time | 0.61 seconds |
| Started | Jul 11 04:30:10 PM PDT 24 |
| Finished | Jul 11 04:30:17 PM PDT 24 |
| Peak memory | 194632 kb |
| Host | smart-850da1c2-5f7f-4e55-94c4-68ce9f331977 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439426866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1439426866 |
| Directory | /workspace/11.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.107526720 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 60299056 ps |
| CPU time | 0.63 seconds |
| Started | Jul 11 04:30:42 PM PDT 24 |
| Finished | Jul 11 04:30:47 PM PDT 24 |
| Peak memory | 195332 kb |
| Host | smart-63879301-7fc1-401a-a6c8-996f4886127c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107526720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.107526720 |
| Directory | /workspace/11.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/11.gpio_filter_stress.2257648846 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 2076446155 ps |
| CPU time | 27.74 seconds |
| Started | Jul 11 04:29:58 PM PDT 24 |
| Finished | Jul 11 04:30:33 PM PDT 24 |
| Peak memory | 197380 kb |
| Host | smart-bd2eb0a8-262e-420c-aaaa-d50462d35edf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257648846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre ss.2257648846 |
| Directory | /workspace/11.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/11.gpio_full_random.3701963445 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 32476534 ps |
| CPU time | 0.68 seconds |
| Started | Jul 11 04:30:11 PM PDT 24 |
| Finished | Jul 11 04:30:19 PM PDT 24 |
| Peak memory | 195864 kb |
| Host | smart-07264ac7-0da5-44d9-9f75-02bbee51fda6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701963445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3701963445 |
| Directory | /workspace/11.gpio_full_random/latest |
| Test location | /workspace/coverage/default/11.gpio_intr_rand_pgm.2156447576 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 45399707 ps |
| CPU time | 1.25 seconds |
| Started | Jul 11 04:30:18 PM PDT 24 |
| Finished | Jul 11 04:30:32 PM PDT 24 |
| Peak memory | 197528 kb |
| Host | smart-1cfc4ab7-868c-46a9-a13f-cf080f71f38c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156447576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2156447576 |
| Directory | /workspace/11.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3782977450 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 37403922 ps |
| CPU time | 1.49 seconds |
| Started | Jul 11 04:30:12 PM PDT 24 |
| Finished | Jul 11 04:30:21 PM PDT 24 |
| Peak memory | 197176 kb |
| Host | smart-c8e9c2c7-f309-4613-bddf-9b99ad97851a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782977450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3782977450 |
| Directory | /workspace/11.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/11.gpio_rand_intr_trigger.2290654130 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 758763295 ps |
| CPU time | 2.72 seconds |
| Started | Jul 11 04:30:22 PM PDT 24 |
| Finished | Jul 11 04:30:37 PM PDT 24 |
| Peak memory | 198588 kb |
| Host | smart-94b43e42-0a94-4011-90c7-50a42d7deb1c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290654130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger .2290654130 |
| Directory | /workspace/11.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/11.gpio_random_dout_din.819018855 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 38504536 ps |
| CPU time | 0.93 seconds |
| Started | Jul 11 04:31:01 PM PDT 24 |
| Finished | Jul 11 04:31:08 PM PDT 24 |
| Peak memory | 197228 kb |
| Host | smart-e488c2fe-fae7-47ca-bf39-6074f8098bfe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=819018855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.819018855 |
| Directory | /workspace/11.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3087164393 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 26386516 ps |
| CPU time | 0.95 seconds |
| Started | Jul 11 04:30:00 PM PDT 24 |
| Finished | Jul 11 04:30:10 PM PDT 24 |
| Peak memory | 197304 kb |
| Host | smart-f2d3edfc-d7cf-45e4-b09f-cbe098e6275c |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087164393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu p_pulldown.3087164393 |
| Directory | /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.811916993 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 39065602 ps |
| CPU time | 1.65 seconds |
| Started | Jul 11 04:30:09 PM PDT 24 |
| Finished | Jul 11 04:30:18 PM PDT 24 |
| Peak memory | 198524 kb |
| Host | smart-8d61fc3b-90cc-4acf-a8e2-62af295661cd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811916993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran dom_long_reg_writes_reg_reads.811916993 |
| Directory | /workspace/11.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/11.gpio_smoke.1052990941 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 43286076 ps |
| CPU time | 1.13 seconds |
| Started | Jul 11 04:31:02 PM PDT 24 |
| Finished | Jul 11 04:31:10 PM PDT 24 |
| Peak memory | 197340 kb |
| Host | smart-5510ceaf-9c87-4b72-a7b4-55c26b682a5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1052990941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1052990941 |
| Directory | /workspace/11.gpio_smoke/latest |
| Test location | /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3749359622 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 156186292 ps |
| CPU time | 1.27 seconds |
| Started | Jul 11 04:29:59 PM PDT 24 |
| Finished | Jul 11 04:30:09 PM PDT 24 |
| Peak memory | 196172 kb |
| Host | smart-60ce3938-7025-4ea2-bb74-4fcad50298ca |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749359622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3749359622 |
| Directory | /workspace/11.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/11.gpio_stress_all.2210451107 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 68884601304 ps |
| CPU time | 55.94 seconds |
| Started | Jul 11 04:30:13 PM PDT 24 |
| Finished | Jul 11 04:31:17 PM PDT 24 |
| Peak memory | 198684 kb |
| Host | smart-ee58f541-776e-424b-9a64-673b9c5faf8d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210451107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. gpio_stress_all.2210451107 |
| Directory | /workspace/11.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.215969808 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 15015952685 ps |
| CPU time | 240.68 seconds |
| Started | Jul 11 04:30:25 PM PDT 24 |
| Finished | Jul 11 04:34:38 PM PDT 24 |
| Peak memory | 198792 kb |
| Host | smart-ff7e94b8-ed96-43ca-b0a3-98e24a5b7d94 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =215969808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.215969808 |
| Directory | /workspace/11.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/12.gpio_alert_test.1792744529 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 28690144 ps |
| CPU time | 0.55 seconds |
| Started | Jul 11 04:30:12 PM PDT 24 |
| Finished | Jul 11 04:30:20 PM PDT 24 |
| Peak memory | 195192 kb |
| Host | smart-736dee4b-18d3-4f8f-9fe2-ff66658c1e25 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792744529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1792744529 |
| Directory | /workspace/12.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2662988094 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 78292624 ps |
| CPU time | 0.71 seconds |
| Started | Jul 11 04:30:15 PM PDT 24 |
| Finished | Jul 11 04:30:27 PM PDT 24 |
| Peak memory | 196524 kb |
| Host | smart-afc301df-dc78-4dcb-a972-d1ee0350f2c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2662988094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2662988094 |
| Directory | /workspace/12.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/12.gpio_filter_stress.1188287696 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 537065511 ps |
| CPU time | 26.62 seconds |
| Started | Jul 11 04:30:15 PM PDT 24 |
| Finished | Jul 11 04:30:53 PM PDT 24 |
| Peak memory | 197704 kb |
| Host | smart-ef7762a9-c2d1-49bb-8b4e-7cdbc90e899c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188287696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre ss.1188287696 |
| Directory | /workspace/12.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/12.gpio_full_random.3248868228 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 64764304 ps |
| CPU time | 0.91 seconds |
| Started | Jul 11 04:31:06 PM PDT 24 |
| Finished | Jul 11 04:31:17 PM PDT 24 |
| Peak memory | 197160 kb |
| Host | smart-c156e50f-12f0-4515-9d3b-d01e828cd1cd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248868228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3248868228 |
| Directory | /workspace/12.gpio_full_random/latest |
| Test location | /workspace/coverage/default/12.gpio_intr_rand_pgm.2608992126 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 316659221 ps |
| CPU time | 1.16 seconds |
| Started | Jul 11 04:30:14 PM PDT 24 |
| Finished | Jul 11 04:30:26 PM PDT 24 |
| Peak memory | 197020 kb |
| Host | smart-4a11f4b8-7bce-45d2-ab66-e311f88939d0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608992126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2608992126 |
| Directory | /workspace/12.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.947716280 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 63210324 ps |
| CPU time | 1.41 seconds |
| Started | Jul 11 04:30:12 PM PDT 24 |
| Finished | Jul 11 04:30:21 PM PDT 24 |
| Peak memory | 198524 kb |
| Host | smart-3a73adac-2dde-427b-8906-8849024f1a36 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947716280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 12.gpio_intr_with_filter_rand_intr_event.947716280 |
| Directory | /workspace/12.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/12.gpio_rand_intr_trigger.3843980741 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 78887748 ps |
| CPU time | 2.15 seconds |
| Started | Jul 11 04:30:16 PM PDT 24 |
| Finished | Jul 11 04:30:30 PM PDT 24 |
| Peak memory | 197704 kb |
| Host | smart-a615f7a3-2737-4a88-97b7-2474583bf6e4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843980741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger .3843980741 |
| Directory | /workspace/12.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/12.gpio_random_dout_din.3348434980 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 282648968 ps |
| CPU time | 1.12 seconds |
| Started | Jul 11 04:30:12 PM PDT 24 |
| Finished | Jul 11 04:30:21 PM PDT 24 |
| Peak memory | 196524 kb |
| Host | smart-ad1e0c59-f2aa-4a8c-a1fa-4f04cf7ed4c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3348434980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3348434980 |
| Directory | /workspace/12.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3372172801 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 85221587 ps |
| CPU time | 1.01 seconds |
| Started | Jul 11 04:30:00 PM PDT 24 |
| Finished | Jul 11 04:30:10 PM PDT 24 |
| Peak memory | 196416 kb |
| Host | smart-772af28b-8fcf-4f87-bf29-b60d4ec7d2fe |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372172801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu p_pulldown.3372172801 |
| Directory | /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2778378499 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1741700636 ps |
| CPU time | 5.1 seconds |
| Started | Jul 11 04:31:50 PM PDT 24 |
| Finished | Jul 11 04:32:18 PM PDT 24 |
| Peak memory | 198140 kb |
| Host | smart-464151e3-aefa-4d21-b5b8-c610b1dca02c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778378499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra ndom_long_reg_writes_reg_reads.2778378499 |
| Directory | /workspace/12.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/12.gpio_smoke.47674559 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 170676121 ps |
| CPU time | 1.19 seconds |
| Started | Jul 11 04:29:57 PM PDT 24 |
| Finished | Jul 11 04:30:04 PM PDT 24 |
| Peak memory | 197200 kb |
| Host | smart-f5a201a3-ef37-450b-a284-b0c50d62775b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47674559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.47674559 |
| Directory | /workspace/12.gpio_smoke/latest |
| Test location | /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1174339699 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 197900443 ps |
| CPU time | 0.73 seconds |
| Started | Jul 11 04:31:55 PM PDT 24 |
| Finished | Jul 11 04:32:21 PM PDT 24 |
| Peak memory | 196404 kb |
| Host | smart-c307be48-2831-415a-a1f1-39e329672ebf |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174339699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1174339699 |
| Directory | /workspace/12.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/12.gpio_stress_all.3815991337 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 144446056602 ps |
| CPU time | 135.73 seconds |
| Started | Jul 11 04:30:19 PM PDT 24 |
| Finished | Jul 11 04:32:48 PM PDT 24 |
| Peak memory | 198728 kb |
| Host | smart-5917c09c-34a1-47d6-b613-5936d896a142 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815991337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. gpio_stress_all.3815991337 |
| Directory | /workspace/12.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/13.gpio_alert_test.1408614204 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 21488032 ps |
| CPU time | 0.57 seconds |
| Started | Jul 11 04:30:10 PM PDT 24 |
| Finished | Jul 11 04:30:17 PM PDT 24 |
| Peak memory | 194624 kb |
| Host | smart-152f355d-1335-4388-8c93-66055c2ed872 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408614204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1408614204 |
| Directory | /workspace/13.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2011182365 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 49679444 ps |
| CPU time | 0.82 seconds |
| Started | Jul 11 04:30:26 PM PDT 24 |
| Finished | Jul 11 04:30:39 PM PDT 24 |
| Peak memory | 197140 kb |
| Host | smart-9399edb1-e573-4aab-8542-3ca7aadfcfc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2011182365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2011182365 |
| Directory | /workspace/13.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/13.gpio_filter_stress.1372304517 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 2605191087 ps |
| CPU time | 18.24 seconds |
| Started | Jul 11 04:30:11 PM PDT 24 |
| Finished | Jul 11 04:30:37 PM PDT 24 |
| Peak memory | 197548 kb |
| Host | smart-82a2a446-cbb7-47c7-bd70-62828c48c418 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372304517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre ss.1372304517 |
| Directory | /workspace/13.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/13.gpio_full_random.2428839685 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 244073363 ps |
| CPU time | 0.95 seconds |
| Started | Jul 11 04:31:48 PM PDT 24 |
| Finished | Jul 11 04:32:13 PM PDT 24 |
| Peak memory | 196940 kb |
| Host | smart-509f15b1-c8a0-45bb-b0d8-bf6394fb5405 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428839685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2428839685 |
| Directory | /workspace/13.gpio_full_random/latest |
| Test location | /workspace/coverage/default/13.gpio_intr_rand_pgm.698244759 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 48515339 ps |
| CPU time | 1.21 seconds |
| Started | Jul 11 04:30:30 PM PDT 24 |
| Finished | Jul 11 04:30:42 PM PDT 24 |
| Peak memory | 197808 kb |
| Host | smart-c9c41985-a0bc-4cc4-b88f-c6efede8aa89 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698244759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.698244759 |
| Directory | /workspace/13.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1820903295 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 309949240 ps |
| CPU time | 2.58 seconds |
| Started | Jul 11 04:30:03 PM PDT 24 |
| Finished | Jul 11 04:30:15 PM PDT 24 |
| Peak memory | 198640 kb |
| Host | smart-a46d7ad6-33c6-49ee-883d-5ac4aa7c108e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820903295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1820903295 |
| Directory | /workspace/13.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/13.gpio_rand_intr_trigger.2267835672 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 600420245 ps |
| CPU time | 2.98 seconds |
| Started | Jul 11 04:30:05 PM PDT 24 |
| Finished | Jul 11 04:30:16 PM PDT 24 |
| Peak memory | 197940 kb |
| Host | smart-3d915665-0628-4796-ad96-0a17b00985db |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267835672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger .2267835672 |
| Directory | /workspace/13.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/13.gpio_random_dout_din.3984988928 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 21652527 ps |
| CPU time | 0.83 seconds |
| Started | Jul 11 04:30:40 PM PDT 24 |
| Finished | Jul 11 04:30:45 PM PDT 24 |
| Peak memory | 196944 kb |
| Host | smart-d909ddf8-9779-4f8a-b768-8a55d076b8d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3984988928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3984988928 |
| Directory | /workspace/13.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3199078448 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 47950229 ps |
| CPU time | 1.08 seconds |
| Started | Jul 11 04:30:12 PM PDT 24 |
| Finished | Jul 11 04:30:21 PM PDT 24 |
| Peak memory | 196480 kb |
| Host | smart-8f6f86be-5032-4ba5-8aed-b3488c89cb6c |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199078448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu p_pulldown.3199078448 |
| Directory | /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2313706044 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 1826104161 ps |
| CPU time | 5.07 seconds |
| Started | Jul 11 04:31:25 PM PDT 24 |
| Finished | Jul 11 04:31:50 PM PDT 24 |
| Peak memory | 197580 kb |
| Host | smart-803a2dc5-c713-4a0d-b064-9db4fa25392a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313706044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra ndom_long_reg_writes_reg_reads.2313706044 |
| Directory | /workspace/13.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/13.gpio_smoke.553506139 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 353687086 ps |
| CPU time | 1.36 seconds |
| Started | Jul 11 04:30:05 PM PDT 24 |
| Finished | Jul 11 04:30:15 PM PDT 24 |
| Peak memory | 197256 kb |
| Host | smart-4266a5b1-bf98-4b2c-8e6c-cdb9a5082fa4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=553506139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.553506139 |
| Directory | /workspace/13.gpio_smoke/latest |
| Test location | /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3018823362 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 72756774 ps |
| CPU time | 0.89 seconds |
| Started | Jul 11 04:30:13 PM PDT 24 |
| Finished | Jul 11 04:30:21 PM PDT 24 |
| Peak memory | 196924 kb |
| Host | smart-19031d21-dd67-4949-af01-77388651cc37 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018823362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3018823362 |
| Directory | /workspace/13.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/13.gpio_stress_all.614642825 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 8123298850 ps |
| CPU time | 101.08 seconds |
| Started | Jul 11 04:29:58 PM PDT 24 |
| Finished | Jul 11 04:31:45 PM PDT 24 |
| Peak memory | 198660 kb |
| Host | smart-f4936ff0-31cb-4743-9b52-8c5aac3a8a39 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614642825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g pio_stress_all.614642825 |
| Directory | /workspace/13.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.1555937968 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 33803346205 ps |
| CPU time | 876.72 seconds |
| Started | Jul 11 04:30:01 PM PDT 24 |
| Finished | Jul 11 04:44:48 PM PDT 24 |
| Peak memory | 198792 kb |
| Host | smart-a3022fac-08db-40e2-941e-856f64c69102 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1555937968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.1555937968 |
| Directory | /workspace/13.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/14.gpio_alert_test.3142824791 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 15381158 ps |
| CPU time | 0.59 seconds |
| Started | Jul 11 04:30:25 PM PDT 24 |
| Finished | Jul 11 04:30:37 PM PDT 24 |
| Peak memory | 194704 kb |
| Host | smart-363fbaa3-dde8-4e74-984c-a8f67a9c2e70 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142824791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3142824791 |
| Directory | /workspace/14.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.196917364 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 35703613 ps |
| CPU time | 0.79 seconds |
| Started | Jul 11 04:30:16 PM PDT 24 |
| Finished | Jul 11 04:30:28 PM PDT 24 |
| Peak memory | 196756 kb |
| Host | smart-78413a1e-4c63-4c77-a2ee-e1d973986ab7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=196917364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.196917364 |
| Directory | /workspace/14.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/14.gpio_filter_stress.3481404843 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1274233763 ps |
| CPU time | 18.22 seconds |
| Started | Jul 11 04:30:19 PM PDT 24 |
| Finished | Jul 11 04:30:50 PM PDT 24 |
| Peak memory | 198540 kb |
| Host | smart-b52f1e51-788e-417c-a5cf-82299086b06f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481404843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre ss.3481404843 |
| Directory | /workspace/14.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/14.gpio_full_random.3652969734 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 295107738 ps |
| CPU time | 0.95 seconds |
| Started | Jul 11 04:31:54 PM PDT 24 |
| Finished | Jul 11 04:32:19 PM PDT 24 |
| Peak memory | 197088 kb |
| Host | smart-eb94788f-3c41-4a8f-9f1a-4443ac98e7c6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652969734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3652969734 |
| Directory | /workspace/14.gpio_full_random/latest |
| Test location | /workspace/coverage/default/14.gpio_intr_rand_pgm.729433468 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 541879523 ps |
| CPU time | 1.12 seconds |
| Started | Jul 11 04:30:20 PM PDT 24 |
| Finished | Jul 11 04:30:34 PM PDT 24 |
| Peak memory | 196612 kb |
| Host | smart-32e755e2-612e-4ff6-a34a-dc2c6c2e706d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729433468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.729433468 |
| Directory | /workspace/14.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1040303478 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 74428984 ps |
| CPU time | 2.84 seconds |
| Started | Jul 11 04:30:23 PM PDT 24 |
| Finished | Jul 11 04:30:39 PM PDT 24 |
| Peak memory | 198536 kb |
| Host | smart-641d8136-d77b-456b-9a1f-4134ca7bcb5b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040303478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1040303478 |
| Directory | /workspace/14.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/14.gpio_rand_intr_trigger.1335007297 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 141027465 ps |
| CPU time | 2.93 seconds |
| Started | Jul 11 04:30:20 PM PDT 24 |
| Finished | Jul 11 04:30:37 PM PDT 24 |
| Peak memory | 196368 kb |
| Host | smart-4af026c8-b79a-47dd-a294-876c16ce6c7c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335007297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger .1335007297 |
| Directory | /workspace/14.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/14.gpio_random_dout_din.1589389677 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 306860704 ps |
| CPU time | 1.34 seconds |
| Started | Jul 11 04:30:11 PM PDT 24 |
| Finished | Jul 11 04:30:20 PM PDT 24 |
| Peak memory | 196396 kb |
| Host | smart-04ede8f2-94e4-4334-8ae0-785b81c5b8ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1589389677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1589389677 |
| Directory | /workspace/14.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2370664778 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 58493591 ps |
| CPU time | 1.17 seconds |
| Started | Jul 11 04:30:04 PM PDT 24 |
| Finished | Jul 11 04:30:14 PM PDT 24 |
| Peak memory | 197352 kb |
| Host | smart-6caba282-69c2-4d18-bcf8-7f466988a4ef |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370664778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu p_pulldown.2370664778 |
| Directory | /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/14.gpio_smoke.3419105943 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 120158927 ps |
| CPU time | 1.16 seconds |
| Started | Jul 11 04:30:15 PM PDT 24 |
| Finished | Jul 11 04:30:26 PM PDT 24 |
| Peak memory | 197420 kb |
| Host | smart-fb552fe1-664c-4076-aca4-e46236aa2f8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3419105943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3419105943 |
| Directory | /workspace/14.gpio_smoke/latest |
| Test location | /workspace/coverage/default/14.gpio_stress_all.3409065605 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 7870760310 ps |
| CPU time | 102.66 seconds |
| Started | Jul 11 04:30:20 PM PDT 24 |
| Finished | Jul 11 04:32:16 PM PDT 24 |
| Peak memory | 198656 kb |
| Host | smart-373453e3-73ae-4a55-92d4-f92cf54753c5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409065605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. gpio_stress_all.3409065605 |
| Directory | /workspace/14.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/15.gpio_alert_test.2613149510 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 12395569 ps |
| CPU time | 0.55 seconds |
| Started | Jul 11 04:30:14 PM PDT 24 |
| Finished | Jul 11 04:30:24 PM PDT 24 |
| Peak memory | 194608 kb |
| Host | smart-5baa5988-a00f-41d0-9ca2-44ba7ef5749a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613149510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2613149510 |
| Directory | /workspace/15.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2910615220 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 38966091 ps |
| CPU time | 0.8 seconds |
| Started | Jul 11 04:30:24 PM PDT 24 |
| Finished | Jul 11 04:30:37 PM PDT 24 |
| Peak memory | 196736 kb |
| Host | smart-c3926da2-1cfb-43de-90b7-ed9af5cad37b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2910615220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2910615220 |
| Directory | /workspace/15.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/15.gpio_filter_stress.2020786714 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 760115743 ps |
| CPU time | 18.42 seconds |
| Started | Jul 11 04:30:50 PM PDT 24 |
| Finished | Jul 11 04:31:12 PM PDT 24 |
| Peak memory | 197256 kb |
| Host | smart-ac6302f8-11d4-4dd0-bab6-9457ea732b55 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020786714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre ss.2020786714 |
| Directory | /workspace/15.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/15.gpio_full_random.2436115013 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 91544784 ps |
| CPU time | 0.74 seconds |
| Started | Jul 11 04:30:15 PM PDT 24 |
| Finished | Jul 11 04:30:26 PM PDT 24 |
| Peak memory | 196344 kb |
| Host | smart-8571bbb8-f0a0-4065-83b0-c7fffe8a6be0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436115013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2436115013 |
| Directory | /workspace/15.gpio_full_random/latest |
| Test location | /workspace/coverage/default/15.gpio_intr_rand_pgm.1316288830 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 499437435 ps |
| CPU time | 1.3 seconds |
| Started | Jul 11 04:30:13 PM PDT 24 |
| Finished | Jul 11 04:30:22 PM PDT 24 |
| Peak memory | 197656 kb |
| Host | smart-903ee826-9dab-4d37-98b0-780d77535eef |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316288830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.1316288830 |
| Directory | /workspace/15.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2288732497 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 354375408 ps |
| CPU time | 1.37 seconds |
| Started | Jul 11 04:30:22 PM PDT 24 |
| Finished | Jul 11 04:30:40 PM PDT 24 |
| Peak memory | 197256 kb |
| Host | smart-ebb2cc0f-d96f-4304-b576-db92db378e45 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288732497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2288732497 |
| Directory | /workspace/15.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/15.gpio_rand_intr_trigger.3024527925 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 66102548 ps |
| CPU time | 1.75 seconds |
| Started | Jul 11 04:30:17 PM PDT 24 |
| Finished | Jul 11 04:30:31 PM PDT 24 |
| Peak memory | 197720 kb |
| Host | smart-f71d9b18-dcd3-4017-8a6d-69de16caf665 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024527925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger .3024527925 |
| Directory | /workspace/15.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/15.gpio_random_dout_din.2372757328 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 21720258 ps |
| CPU time | 0.75 seconds |
| Started | Jul 11 04:30:16 PM PDT 24 |
| Finished | Jul 11 04:30:28 PM PDT 24 |
| Peak memory | 196172 kb |
| Host | smart-f3772190-b417-43fe-967b-55f2975b9a56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2372757328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2372757328 |
| Directory | /workspace/15.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1583062029 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 25436377 ps |
| CPU time | 0.72 seconds |
| Started | Jul 11 04:30:19 PM PDT 24 |
| Finished | Jul 11 04:30:32 PM PDT 24 |
| Peak memory | 195964 kb |
| Host | smart-7414d46b-ffc0-4da2-a9d4-19e0304df7e1 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583062029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu p_pulldown.1583062029 |
| Directory | /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.172701142 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 120057719 ps |
| CPU time | 2.14 seconds |
| Started | Jul 11 04:30:15 PM PDT 24 |
| Finished | Jul 11 04:30:28 PM PDT 24 |
| Peak memory | 198604 kb |
| Host | smart-4a0632ea-c8ed-4bb8-93fc-2410ee827f17 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172701142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran dom_long_reg_writes_reg_reads.172701142 |
| Directory | /workspace/15.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/15.gpio_smoke.1537127164 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 32288956 ps |
| CPU time | 0.96 seconds |
| Started | Jul 11 04:30:09 PM PDT 24 |
| Finished | Jul 11 04:30:16 PM PDT 24 |
| Peak memory | 196436 kb |
| Host | smart-b1fc0606-f294-4159-a717-71c048af6907 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1537127164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1537127164 |
| Directory | /workspace/15.gpio_smoke/latest |
| Test location | /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.78044810 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 129260857 ps |
| CPU time | 0.89 seconds |
| Started | Jul 11 04:30:13 PM PDT 24 |
| Finished | Jul 11 04:30:23 PM PDT 24 |
| Peak memory | 197488 kb |
| Host | smart-735c7621-c399-469f-9b59-c60cf5a67b3b |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78044810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.78044810 |
| Directory | /workspace/15.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/15.gpio_stress_all.3034087911 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 8614748004 ps |
| CPU time | 206.32 seconds |
| Started | Jul 11 04:30:18 PM PDT 24 |
| Finished | Jul 11 04:33:57 PM PDT 24 |
| Peak memory | 198660 kb |
| Host | smart-914f8944-0c12-4569-bb58-028621d3935e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034087911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. gpio_stress_all.3034087911 |
| Directory | /workspace/15.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/16.gpio_alert_test.3949843867 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 75691678 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:30:23 PM PDT 24 |
| Finished | Jul 11 04:30:37 PM PDT 24 |
| Peak memory | 194720 kb |
| Host | smart-1ffe8f36-4241-4504-a4a8-79a3c0d5dcd5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949843867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3949843867 |
| Directory | /workspace/16.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2097262919 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 24712508 ps |
| CPU time | 0.84 seconds |
| Started | Jul 11 04:31:26 PM PDT 24 |
| Finished | Jul 11 04:31:46 PM PDT 24 |
| Peak memory | 195224 kb |
| Host | smart-55adeac3-6f2d-4072-81f9-fdda9bc79162 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2097262919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2097262919 |
| Directory | /workspace/16.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/16.gpio_filter_stress.1648298273 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 646354191 ps |
| CPU time | 17.1 seconds |
| Started | Jul 11 04:30:17 PM PDT 24 |
| Finished | Jul 11 04:30:47 PM PDT 24 |
| Peak memory | 196048 kb |
| Host | smart-7c75197b-aa57-4c9f-8a03-fda417c7cdee |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648298273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre ss.1648298273 |
| Directory | /workspace/16.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/16.gpio_full_random.1474725911 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 76649039 ps |
| CPU time | 0.97 seconds |
| Started | Jul 11 04:30:18 PM PDT 24 |
| Finished | Jul 11 04:30:32 PM PDT 24 |
| Peak memory | 197044 kb |
| Host | smart-47494f01-a58b-40c6-8a6c-bd920a329fe3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474725911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1474725911 |
| Directory | /workspace/16.gpio_full_random/latest |
| Test location | /workspace/coverage/default/16.gpio_intr_rand_pgm.2735055476 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 30887600 ps |
| CPU time | 0.91 seconds |
| Started | Jul 11 04:30:13 PM PDT 24 |
| Finished | Jul 11 04:30:22 PM PDT 24 |
| Peak memory | 196492 kb |
| Host | smart-5e54abde-747a-4720-a5f8-642693552ea7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735055476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2735055476 |
| Directory | /workspace/16.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.201405986 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 89871458 ps |
| CPU time | 3.31 seconds |
| Started | Jul 11 04:30:18 PM PDT 24 |
| Finished | Jul 11 04:30:35 PM PDT 24 |
| Peak memory | 198680 kb |
| Host | smart-f69ab45f-773a-44a8-a5b7-fecbc2d7963d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201405986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 16.gpio_intr_with_filter_rand_intr_event.201405986 |
| Directory | /workspace/16.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/16.gpio_rand_intr_trigger.2728332041 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 78065861 ps |
| CPU time | 2.17 seconds |
| Started | Jul 11 04:30:13 PM PDT 24 |
| Finished | Jul 11 04:30:23 PM PDT 24 |
| Peak memory | 198572 kb |
| Host | smart-009ac74c-e679-4f24-8317-f1840c46146d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728332041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger .2728332041 |
| Directory | /workspace/16.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/16.gpio_random_dout_din.1523151873 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 44247992 ps |
| CPU time | 0.9 seconds |
| Started | Jul 11 04:30:16 PM PDT 24 |
| Finished | Jul 11 04:30:28 PM PDT 24 |
| Peak memory | 197056 kb |
| Host | smart-f2f65a86-641d-4efc-a37a-54d62c5394c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1523151873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1523151873 |
| Directory | /workspace/16.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2835248122 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 66052268 ps |
| CPU time | 0.8 seconds |
| Started | Jul 11 04:30:20 PM PDT 24 |
| Finished | Jul 11 04:30:34 PM PDT 24 |
| Peak memory | 196120 kb |
| Host | smart-8dde1632-1822-4eec-81de-f5141cf88706 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835248122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu p_pulldown.2835248122 |
| Directory | /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.132865025 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 46231101 ps |
| CPU time | 1.93 seconds |
| Started | Jul 11 04:30:14 PM PDT 24 |
| Finished | Jul 11 04:30:25 PM PDT 24 |
| Peak memory | 198452 kb |
| Host | smart-e5872866-23a3-4144-bfed-c608b7061b15 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132865025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran dom_long_reg_writes_reg_reads.132865025 |
| Directory | /workspace/16.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/16.gpio_smoke.2189156311 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 168790122 ps |
| CPU time | 1.32 seconds |
| Started | Jul 11 04:30:20 PM PDT 24 |
| Finished | Jul 11 04:30:35 PM PDT 24 |
| Peak memory | 197336 kb |
| Host | smart-aa6a5931-3f19-4a1c-b76b-c3b171985abf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2189156311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2189156311 |
| Directory | /workspace/16.gpio_smoke/latest |
| Test location | /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2680656264 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 56725950 ps |
| CPU time | 1.25 seconds |
| Started | Jul 11 04:30:19 PM PDT 24 |
| Finished | Jul 11 04:30:33 PM PDT 24 |
| Peak memory | 197252 kb |
| Host | smart-f863bc91-feee-41b3-a06b-ac8934fa0f20 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680656264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2680656264 |
| Directory | /workspace/16.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/16.gpio_stress_all.3004081013 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 2269254188 ps |
| CPU time | 53.91 seconds |
| Started | Jul 11 04:30:21 PM PDT 24 |
| Finished | Jul 11 04:31:28 PM PDT 24 |
| Peak memory | 198412 kb |
| Host | smart-2e76483c-6b52-4e42-ac8d-d7d82384b254 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004081013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16. gpio_stress_all.3004081013 |
| Directory | /workspace/16.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.2852594717 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 184941127606 ps |
| CPU time | 1056.89 seconds |
| Started | Jul 11 04:30:19 PM PDT 24 |
| Finished | Jul 11 04:48:09 PM PDT 24 |
| Peak memory | 198824 kb |
| Host | smart-302401cb-56a8-4ceb-92bb-0f861b28d426 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2852594717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.2852594717 |
| Directory | /workspace/16.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.gpio_alert_test.3235027796 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 21534341 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:30:27 PM PDT 24 |
| Finished | Jul 11 04:30:39 PM PDT 24 |
| Peak memory | 195212 kb |
| Host | smart-d46850a6-d6b6-4ba7-9df5-16b45d6f29ee |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235027796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3235027796 |
| Directory | /workspace/17.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2680262928 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 127592152 ps |
| CPU time | 0.65 seconds |
| Started | Jul 11 04:30:25 PM PDT 24 |
| Finished | Jul 11 04:30:38 PM PDT 24 |
| Peak memory | 195388 kb |
| Host | smart-f3363fdd-633a-4a64-8e84-a85b1885339c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2680262928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2680262928 |
| Directory | /workspace/17.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/17.gpio_filter_stress.382299832 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 401483020 ps |
| CPU time | 13.84 seconds |
| Started | Jul 11 04:30:21 PM PDT 24 |
| Finished | Jul 11 04:30:48 PM PDT 24 |
| Peak memory | 197500 kb |
| Host | smart-4bdd18ae-f7e1-4694-8820-c7e50982e2bf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382299832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres s.382299832 |
| Directory | /workspace/17.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/17.gpio_full_random.4087579811 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 52432843 ps |
| CPU time | 0.81 seconds |
| Started | Jul 11 04:30:13 PM PDT 24 |
| Finished | Jul 11 04:30:23 PM PDT 24 |
| Peak memory | 197216 kb |
| Host | smart-6d3a9b98-2e23-4340-afda-cbbb493f982a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087579811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.4087579811 |
| Directory | /workspace/17.gpio_full_random/latest |
| Test location | /workspace/coverage/default/17.gpio_intr_rand_pgm.3745672571 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 44886764 ps |
| CPU time | 0.78 seconds |
| Started | Jul 11 04:30:20 PM PDT 24 |
| Finished | Jul 11 04:30:34 PM PDT 24 |
| Peak memory | 196836 kb |
| Host | smart-565b5834-9f56-4eb5-80ea-b5737c70cb5f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745672571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3745672571 |
| Directory | /workspace/17.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1324532748 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 44819615 ps |
| CPU time | 1.93 seconds |
| Started | Jul 11 04:31:26 PM PDT 24 |
| Finished | Jul 11 04:31:47 PM PDT 24 |
| Peak memory | 197128 kb |
| Host | smart-37117d21-0623-4a72-abba-0ee55773f33e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324532748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1324532748 |
| Directory | /workspace/17.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/17.gpio_rand_intr_trigger.1307445822 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 35526760 ps |
| CPU time | 1.09 seconds |
| Started | Jul 11 04:30:16 PM PDT 24 |
| Finished | Jul 11 04:30:29 PM PDT 24 |
| Peak memory | 196280 kb |
| Host | smart-577706b5-8c5b-4419-a7ef-c1d2c7aae2aa |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307445822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger .1307445822 |
| Directory | /workspace/17.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/17.gpio_random_dout_din.1434231019 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 61008050 ps |
| CPU time | 0.75 seconds |
| Started | Jul 11 04:30:12 PM PDT 24 |
| Finished | Jul 11 04:30:20 PM PDT 24 |
| Peak memory | 196580 kb |
| Host | smart-cb26f3e8-0a86-4dae-beec-a76478a90c83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1434231019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1434231019 |
| Directory | /workspace/17.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1462326923 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 82630249 ps |
| CPU time | 0.97 seconds |
| Started | Jul 11 04:30:17 PM PDT 24 |
| Finished | Jul 11 04:30:30 PM PDT 24 |
| Peak memory | 196636 kb |
| Host | smart-cf9a8474-b700-47f6-a310-a3ce34b6dad2 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462326923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu p_pulldown.1462326923 |
| Directory | /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2643262760 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 234155898 ps |
| CPU time | 3.67 seconds |
| Started | Jul 11 04:30:15 PM PDT 24 |
| Finished | Jul 11 04:30:29 PM PDT 24 |
| Peak memory | 198632 kb |
| Host | smart-4af00f26-9912-473b-9c10-17cd24f74702 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643262760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra ndom_long_reg_writes_reg_reads.2643262760 |
| Directory | /workspace/17.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/17.gpio_smoke.1139254908 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 549797683 ps |
| CPU time | 0.97 seconds |
| Started | Jul 11 04:30:18 PM PDT 24 |
| Finished | Jul 11 04:30:32 PM PDT 24 |
| Peak memory | 196272 kb |
| Host | smart-a9942462-da97-4efc-85d2-5101e82a7969 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1139254908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1139254908 |
| Directory | /workspace/17.gpio_smoke/latest |
| Test location | /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1260146209 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 74850755 ps |
| CPU time | 0.73 seconds |
| Started | Jul 11 04:30:22 PM PDT 24 |
| Finished | Jul 11 04:30:35 PM PDT 24 |
| Peak memory | 195784 kb |
| Host | smart-ddeb5037-c96a-4c21-829e-d8803a2407bf |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260146209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1260146209 |
| Directory | /workspace/17.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/17.gpio_stress_all.3950432455 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 8487191950 ps |
| CPU time | 86.36 seconds |
| Started | Jul 11 04:30:16 PM PDT 24 |
| Finished | Jul 11 04:31:55 PM PDT 24 |
| Peak memory | 198732 kb |
| Host | smart-e4465ec1-f28d-4461-8374-cbddd95fb1fc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950432455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. gpio_stress_all.3950432455 |
| Directory | /workspace/17.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/18.gpio_alert_test.244342006 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 14550414 ps |
| CPU time | 0.6 seconds |
| Started | Jul 11 04:30:18 PM PDT 24 |
| Finished | Jul 11 04:30:31 PM PDT 24 |
| Peak memory | 195404 kb |
| Host | smart-fb07a2dc-aa31-4932-ae73-51fea1563ab8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244342006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.244342006 |
| Directory | /workspace/18.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.274623419 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 857903468 ps |
| CPU time | 0.9 seconds |
| Started | Jul 11 04:30:21 PM PDT 24 |
| Finished | Jul 11 04:30:35 PM PDT 24 |
| Peak memory | 196936 kb |
| Host | smart-d27aca7a-3606-4c3a-996e-d35536de92b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=274623419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.274623419 |
| Directory | /workspace/18.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/18.gpio_filter_stress.1804638072 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 498210659 ps |
| CPU time | 16.18 seconds |
| Started | Jul 11 04:30:39 PM PDT 24 |
| Finished | Jul 11 04:31:00 PM PDT 24 |
| Peak memory | 198496 kb |
| Host | smart-b09532ca-5c24-4e49-af7f-e862c056b4e9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804638072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre ss.1804638072 |
| Directory | /workspace/18.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/18.gpio_full_random.2629954177 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 94946714 ps |
| CPU time | 0.8 seconds |
| Started | Jul 11 04:30:35 PM PDT 24 |
| Finished | Jul 11 04:30:43 PM PDT 24 |
| Peak memory | 197092 kb |
| Host | smart-35618af3-7fe4-42b8-8b0b-dab641d82338 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629954177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2629954177 |
| Directory | /workspace/18.gpio_full_random/latest |
| Test location | /workspace/coverage/default/18.gpio_intr_rand_pgm.4078138506 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 223390913 ps |
| CPU time | 1 seconds |
| Started | Jul 11 04:30:15 PM PDT 24 |
| Finished | Jul 11 04:30:26 PM PDT 24 |
| Peak memory | 196592 kb |
| Host | smart-48b9efd1-a114-414a-a087-d0885b48519d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078138506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.4078138506 |
| Directory | /workspace/18.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1988033217 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 88558554 ps |
| CPU time | 3.41 seconds |
| Started | Jul 11 04:30:32 PM PDT 24 |
| Finished | Jul 11 04:30:45 PM PDT 24 |
| Peak memory | 198588 kb |
| Host | smart-eaa99299-d4ec-4bfb-be62-9c6f1c85c8b4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988033217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1988033217 |
| Directory | /workspace/18.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/18.gpio_rand_intr_trigger.1167759055 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 31536263 ps |
| CPU time | 0.86 seconds |
| Started | Jul 11 04:30:27 PM PDT 24 |
| Finished | Jul 11 04:30:40 PM PDT 24 |
| Peak memory | 194920 kb |
| Host | smart-4227b32a-b09b-4cb3-9f28-8f18054e93db |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167759055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger .1167759055 |
| Directory | /workspace/18.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/18.gpio_random_dout_din.591673050 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 95159774 ps |
| CPU time | 0.73 seconds |
| Started | Jul 11 04:30:16 PM PDT 24 |
| Finished | Jul 11 04:30:28 PM PDT 24 |
| Peak memory | 195896 kb |
| Host | smart-fbe21322-c34f-4f57-8d98-7881d44c9964 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=591673050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.591673050 |
| Directory | /workspace/18.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3094664821 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 143765002 ps |
| CPU time | 0.85 seconds |
| Started | Jul 11 04:30:28 PM PDT 24 |
| Finished | Jul 11 04:30:40 PM PDT 24 |
| Peak memory | 196972 kb |
| Host | smart-058d3a2b-af51-4101-9941-9a8173690df3 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094664821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu p_pulldown.3094664821 |
| Directory | /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1608714757 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 733517324 ps |
| CPU time | 4.08 seconds |
| Started | Jul 11 04:30:18 PM PDT 24 |
| Finished | Jul 11 04:30:35 PM PDT 24 |
| Peak memory | 198884 kb |
| Host | smart-1ac135d3-1398-4bbf-a343-6c640d2bf6bd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608714757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra ndom_long_reg_writes_reg_reads.1608714757 |
| Directory | /workspace/18.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/18.gpio_smoke.1551754864 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 56582244 ps |
| CPU time | 0.98 seconds |
| Started | Jul 11 04:30:11 PM PDT 24 |
| Finished | Jul 11 04:30:20 PM PDT 24 |
| Peak memory | 196140 kb |
| Host | smart-aa30b5bd-9a56-4d14-80da-ed72a469ee61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1551754864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1551754864 |
| Directory | /workspace/18.gpio_smoke/latest |
| Test location | /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3683276067 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 185347152 ps |
| CPU time | 0.96 seconds |
| Started | Jul 11 04:30:20 PM PDT 24 |
| Finished | Jul 11 04:30:35 PM PDT 24 |
| Peak memory | 196892 kb |
| Host | smart-8ad7c4d1-c8b7-44bd-b502-9199646248eb |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683276067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3683276067 |
| Directory | /workspace/18.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/18.gpio_stress_all.3310463403 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 18337775069 ps |
| CPU time | 262.93 seconds |
| Started | Jul 11 04:30:46 PM PDT 24 |
| Finished | Jul 11 04:35:12 PM PDT 24 |
| Peak memory | 198652 kb |
| Host | smart-1bc8b024-c1bc-4ee1-baca-9cc5a2cb3781 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310463403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. gpio_stress_all.3310463403 |
| Directory | /workspace/18.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.519279189 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 403992563721 ps |
| CPU time | 2143.39 seconds |
| Started | Jul 11 04:30:32 PM PDT 24 |
| Finished | Jul 11 05:06:25 PM PDT 24 |
| Peak memory | 198848 kb |
| Host | smart-67e3782d-cce7-47f4-8677-f1a1c9fc157a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =519279189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.519279189 |
| Directory | /workspace/18.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3760556645 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 50581567 ps |
| CPU time | 0.71 seconds |
| Started | Jul 11 04:30:26 PM PDT 24 |
| Finished | Jul 11 04:30:38 PM PDT 24 |
| Peak memory | 195832 kb |
| Host | smart-e69593ab-3bb5-4f07-90a5-ce49b036d6cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3760556645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3760556645 |
| Directory | /workspace/19.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/19.gpio_filter_stress.3741717473 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 571061270 ps |
| CPU time | 14.39 seconds |
| Started | Jul 11 04:30:22 PM PDT 24 |
| Finished | Jul 11 04:30:50 PM PDT 24 |
| Peak memory | 196188 kb |
| Host | smart-d901cb48-44a0-4ad5-8e30-8b1fee7635d0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741717473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre ss.3741717473 |
| Directory | /workspace/19.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/19.gpio_full_random.4109412542 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 119078709 ps |
| CPU time | 1.01 seconds |
| Started | Jul 11 04:30:19 PM PDT 24 |
| Finished | Jul 11 04:30:33 PM PDT 24 |
| Peak memory | 197120 kb |
| Host | smart-18304a05-6446-4f85-839b-83e074c11119 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109412542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.4109412542 |
| Directory | /workspace/19.gpio_full_random/latest |
| Test location | /workspace/coverage/default/19.gpio_intr_rand_pgm.518344081 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 182867904 ps |
| CPU time | 1.26 seconds |
| Started | Jul 11 04:30:27 PM PDT 24 |
| Finished | Jul 11 04:30:40 PM PDT 24 |
| Peak memory | 196496 kb |
| Host | smart-ff3e72fc-7abc-430b-88cb-92fbeec998b7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518344081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.518344081 |
| Directory | /workspace/19.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3705222993 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 36699782 ps |
| CPU time | 1.45 seconds |
| Started | Jul 11 04:30:24 PM PDT 24 |
| Finished | Jul 11 04:30:38 PM PDT 24 |
| Peak memory | 198584 kb |
| Host | smart-c3f46171-c178-4697-bf27-1bf379b664fa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705222993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3705222993 |
| Directory | /workspace/19.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/19.gpio_rand_intr_trigger.911319337 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 115226782 ps |
| CPU time | 3.06 seconds |
| Started | Jul 11 04:30:26 PM PDT 24 |
| Finished | Jul 11 04:30:42 PM PDT 24 |
| Peak memory | 196484 kb |
| Host | smart-af360bc0-54ef-4fa1-8e81-cd77454c2695 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911319337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger. 911319337 |
| Directory | /workspace/19.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/19.gpio_random_dout_din.3185807550 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 36550604 ps |
| CPU time | 1.24 seconds |
| Started | Jul 11 04:30:16 PM PDT 24 |
| Finished | Jul 11 04:30:29 PM PDT 24 |
| Peak memory | 198700 kb |
| Host | smart-756f37dc-c61f-466b-997c-0189b0e6f389 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3185807550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3185807550 |
| Directory | /workspace/19.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3585145075 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 89100679 ps |
| CPU time | 0.89 seconds |
| Started | Jul 11 04:30:19 PM PDT 24 |
| Finished | Jul 11 04:30:33 PM PDT 24 |
| Peak memory | 197116 kb |
| Host | smart-961be036-0611-4abb-9e68-75c6e832198c |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585145075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu p_pulldown.3585145075 |
| Directory | /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1889996545 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1479712475 ps |
| CPU time | 2.98 seconds |
| Started | Jul 11 04:30:49 PM PDT 24 |
| Finished | Jul 11 04:30:54 PM PDT 24 |
| Peak memory | 198536 kb |
| Host | smart-48eb5a96-9b00-42e2-9ca6-3c82a4b1f97f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889996545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra ndom_long_reg_writes_reg_reads.1889996545 |
| Directory | /workspace/19.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/19.gpio_smoke.544390708 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 52923371 ps |
| CPU time | 0.96 seconds |
| Started | Jul 11 04:30:18 PM PDT 24 |
| Finished | Jul 11 04:30:33 PM PDT 24 |
| Peak memory | 196356 kb |
| Host | smart-35db3ba5-de1e-40d6-804d-20bfc475dff9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=544390708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.544390708 |
| Directory | /workspace/19.gpio_smoke/latest |
| Test location | /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.4023320739 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 44965342 ps |
| CPU time | 0.88 seconds |
| Started | Jul 11 04:31:55 PM PDT 24 |
| Finished | Jul 11 04:32:20 PM PDT 24 |
| Peak memory | 197656 kb |
| Host | smart-9913b133-6668-4f47-9f1c-7a0721d83c67 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023320739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.4023320739 |
| Directory | /workspace/19.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/19.gpio_stress_all.2671284787 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 34190973905 ps |
| CPU time | 113.3 seconds |
| Started | Jul 11 04:30:19 PM PDT 24 |
| Finished | Jul 11 04:32:25 PM PDT 24 |
| Peak memory | 198664 kb |
| Host | smart-45f0da75-3687-4e36-a32f-3561b6f388a0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671284787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. gpio_stress_all.2671284787 |
| Directory | /workspace/19.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.1958779262 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 76479982452 ps |
| CPU time | 2106.45 seconds |
| Started | Jul 11 04:30:18 PM PDT 24 |
| Finished | Jul 11 05:05:37 PM PDT 24 |
| Peak memory | 198788 kb |
| Host | smart-1a4dd4fa-a40e-4962-9036-4e5b1f913a66 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1958779262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.1958779262 |
| Directory | /workspace/19.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.gpio_alert_test.204737352 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 65010430 ps |
| CPU time | 0.57 seconds |
| Started | Jul 11 04:30:03 PM PDT 24 |
| Finished | Jul 11 04:30:12 PM PDT 24 |
| Peak memory | 194548 kb |
| Host | smart-042245cd-eeac-4d9e-a4ae-09ea0f643439 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204737352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.204737352 |
| Directory | /workspace/2.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2107182410 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 132102307 ps |
| CPU time | 0.72 seconds |
| Started | Jul 11 04:29:53 PM PDT 24 |
| Finished | Jul 11 04:29:58 PM PDT 24 |
| Peak memory | 194700 kb |
| Host | smart-ae07a7ec-4d9d-4166-b73e-52332616ed73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2107182410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2107182410 |
| Directory | /workspace/2.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/2.gpio_filter_stress.3462213039 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2623802821 ps |
| CPU time | 7.39 seconds |
| Started | Jul 11 04:29:52 PM PDT 24 |
| Finished | Jul 11 04:30:02 PM PDT 24 |
| Peak memory | 198084 kb |
| Host | smart-e8760489-1686-4c83-9be0-b88307f4dead |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462213039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres s.3462213039 |
| Directory | /workspace/2.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/2.gpio_full_random.259381130 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 302114476 ps |
| CPU time | 0.97 seconds |
| Started | Jul 11 04:29:52 PM PDT 24 |
| Finished | Jul 11 04:29:55 PM PDT 24 |
| Peak memory | 197080 kb |
| Host | smart-9fd19358-41b6-4910-a817-08fca7a06abf |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259381130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.259381130 |
| Directory | /workspace/2.gpio_full_random/latest |
| Test location | /workspace/coverage/default/2.gpio_intr_rand_pgm.3318535006 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 997371442 ps |
| CPU time | 1.01 seconds |
| Started | Jul 11 04:29:47 PM PDT 24 |
| Finished | Jul 11 04:29:51 PM PDT 24 |
| Peak memory | 196604 kb |
| Host | smart-3a88b0c6-3805-4777-aa2f-3b5e0b92729c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318535006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3318535006 |
| Directory | /workspace/2.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3149229261 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 494560059 ps |
| CPU time | 2 seconds |
| Started | Jul 11 04:29:47 PM PDT 24 |
| Finished | Jul 11 04:29:51 PM PDT 24 |
| Peak memory | 198660 kb |
| Host | smart-719d4ac2-c2e2-4c7f-95b2-5b9ffd2984ed |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149229261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3149229261 |
| Directory | /workspace/2.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/2.gpio_rand_intr_trigger.1959463000 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 131350715 ps |
| CPU time | 1.49 seconds |
| Started | Jul 11 04:29:52 PM PDT 24 |
| Finished | Jul 11 04:29:57 PM PDT 24 |
| Peak memory | 196636 kb |
| Host | smart-21891117-7761-42e3-8863-f670a53898a6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959463000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger. 1959463000 |
| Directory | /workspace/2.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/2.gpio_random_dout_din.216792954 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 63587337 ps |
| CPU time | 1.16 seconds |
| Started | Jul 11 04:30:15 PM PDT 24 |
| Finished | Jul 11 04:30:37 PM PDT 24 |
| Peak memory | 196568 kb |
| Host | smart-2340610e-d3fd-4ade-880b-56bfbfb02472 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=216792954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.216792954 |
| Directory | /workspace/2.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1125728243 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 28923054 ps |
| CPU time | 0.76 seconds |
| Started | Jul 11 04:29:55 PM PDT 24 |
| Finished | Jul 11 04:30:00 PM PDT 24 |
| Peak memory | 196064 kb |
| Host | smart-c31799dc-7f19-4e9d-998d-f4419789aab9 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125728243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup _pulldown.1125728243 |
| Directory | /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1520869656 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 233734014 ps |
| CPU time | 2.25 seconds |
| Started | Jul 11 04:29:58 PM PDT 24 |
| Finished | Jul 11 04:30:08 PM PDT 24 |
| Peak memory | 198504 kb |
| Host | smart-2e1e763a-b60a-4990-9b57-7f04d03008c3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520869656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran dom_long_reg_writes_reg_reads.1520869656 |
| Directory | /workspace/2.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/2.gpio_sec_cm.314427992 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 253543072 ps |
| CPU time | 0.97 seconds |
| Started | Jul 11 04:29:54 PM PDT 24 |
| Finished | Jul 11 04:29:59 PM PDT 24 |
| Peak memory | 215400 kb |
| Host | smart-3ddb9abc-7b8c-40c6-94d6-196ab0d8acee |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314427992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.314427992 |
| Directory | /workspace/2.gpio_sec_cm/latest |
| Test location | /workspace/coverage/default/2.gpio_smoke.2845386299 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 455730543 ps |
| CPU time | 1.19 seconds |
| Started | Jul 11 04:29:43 PM PDT 24 |
| Finished | Jul 11 04:29:46 PM PDT 24 |
| Peak memory | 196060 kb |
| Host | smart-481331e9-1717-4d9a-8d61-1b16b325c84e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2845386299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2845386299 |
| Directory | /workspace/2.gpio_smoke/latest |
| Test location | /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2474122811 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 119347487 ps |
| CPU time | 1.16 seconds |
| Started | Jul 11 04:29:49 PM PDT 24 |
| Finished | Jul 11 04:29:52 PM PDT 24 |
| Peak memory | 196936 kb |
| Host | smart-d49dd7f5-3235-405a-b90b-cd72e3bb91ef |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474122811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2474122811 |
| Directory | /workspace/2.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/2.gpio_stress_all.1510821895 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 35296436805 ps |
| CPU time | 102.98 seconds |
| Started | Jul 11 04:30:00 PM PDT 24 |
| Finished | Jul 11 04:31:53 PM PDT 24 |
| Peak memory | 198740 kb |
| Host | smart-2e71610c-ba94-4085-afa4-2af1b3a8dc26 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510821895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g pio_stress_all.1510821895 |
| Directory | /workspace/2.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/20.gpio_alert_test.2438292337 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 28867544 ps |
| CPU time | 0.64 seconds |
| Started | Jul 11 04:31:45 PM PDT 24 |
| Finished | Jul 11 04:32:07 PM PDT 24 |
| Peak memory | 194940 kb |
| Host | smart-1675147f-bb45-44d6-8b67-4476cc53f3a9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438292337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2438292337 |
| Directory | /workspace/20.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3949928030 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 18330208 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:30:18 PM PDT 24 |
| Finished | Jul 11 04:30:31 PM PDT 24 |
| Peak memory | 194372 kb |
| Host | smart-dfc1c155-69d0-4d70-8292-87d6df375386 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3949928030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3949928030 |
| Directory | /workspace/20.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/20.gpio_filter_stress.2976394129 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 315269846 ps |
| CPU time | 6.16 seconds |
| Started | Jul 11 04:30:18 PM PDT 24 |
| Finished | Jul 11 04:30:37 PM PDT 24 |
| Peak memory | 198536 kb |
| Host | smart-554bf779-07ea-4572-8763-a34560eba452 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976394129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre ss.2976394129 |
| Directory | /workspace/20.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/20.gpio_full_random.2064317378 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 25514925 ps |
| CPU time | 0.65 seconds |
| Started | Jul 11 04:30:27 PM PDT 24 |
| Finished | Jul 11 04:30:40 PM PDT 24 |
| Peak memory | 195112 kb |
| Host | smart-f85a24c8-0bdd-4808-9c99-e1b7961891d1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064317378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2064317378 |
| Directory | /workspace/20.gpio_full_random/latest |
| Test location | /workspace/coverage/default/20.gpio_intr_rand_pgm.2976698097 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 51052922 ps |
| CPU time | 1 seconds |
| Started | Jul 11 04:30:17 PM PDT 24 |
| Finished | Jul 11 04:30:30 PM PDT 24 |
| Peak memory | 196584 kb |
| Host | smart-3b7d3368-7280-480b-b31e-13e0708064c7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976698097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2976698097 |
| Directory | /workspace/20.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2441169839 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 173219242 ps |
| CPU time | 1.81 seconds |
| Started | Jul 11 04:30:47 PM PDT 24 |
| Finished | Jul 11 04:30:52 PM PDT 24 |
| Peak memory | 198600 kb |
| Host | smart-3bc3072d-7770-463d-8ba9-cfc4b3c5ab18 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441169839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2441169839 |
| Directory | /workspace/20.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/20.gpio_rand_intr_trigger.1613966385 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 46068890 ps |
| CPU time | 1.39 seconds |
| Started | Jul 11 04:30:48 PM PDT 24 |
| Finished | Jul 11 04:30:51 PM PDT 24 |
| Peak memory | 197216 kb |
| Host | smart-836976ab-342e-4417-8c3f-5f1646d097a1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613966385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger .1613966385 |
| Directory | /workspace/20.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/20.gpio_random_dout_din.2684522460 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 50742808 ps |
| CPU time | 1.25 seconds |
| Started | Jul 11 04:31:56 PM PDT 24 |
| Finished | Jul 11 04:32:23 PM PDT 24 |
| Peak memory | 197364 kb |
| Host | smart-0287bfdb-b6db-43dc-92b7-9258f4129feb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2684522460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2684522460 |
| Directory | /workspace/20.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2617172616 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 44304937 ps |
| CPU time | 1.04 seconds |
| Started | Jul 11 04:30:18 PM PDT 24 |
| Finished | Jul 11 04:30:32 PM PDT 24 |
| Peak memory | 196644 kb |
| Host | smart-95a9a2e2-24e0-4199-b632-32020e856770 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617172616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu p_pulldown.2617172616 |
| Directory | /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1737559297 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 595229152 ps |
| CPU time | 3.85 seconds |
| Started | Jul 11 04:30:17 PM PDT 24 |
| Finished | Jul 11 04:30:34 PM PDT 24 |
| Peak memory | 198552 kb |
| Host | smart-14150aa2-ca49-4282-8884-91140183a9e1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737559297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra ndom_long_reg_writes_reg_reads.1737559297 |
| Directory | /workspace/20.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/20.gpio_smoke.2021811583 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 245464516 ps |
| CPU time | 0.93 seconds |
| Started | Jul 11 04:30:26 PM PDT 24 |
| Finished | Jul 11 04:30:39 PM PDT 24 |
| Peak memory | 196776 kb |
| Host | smart-c8047b96-ceca-40e7-939d-31fa34948c19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2021811583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2021811583 |
| Directory | /workspace/20.gpio_smoke/latest |
| Test location | /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.571445566 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 152018199 ps |
| CPU time | 1.17 seconds |
| Started | Jul 11 04:30:28 PM PDT 24 |
| Finished | Jul 11 04:30:40 PM PDT 24 |
| Peak memory | 197008 kb |
| Host | smart-80ca5a1c-cb6f-45cd-8d84-9177db96228e |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571445566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.571445566 |
| Directory | /workspace/20.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/20.gpio_stress_all.2386040600 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 58756714270 ps |
| CPU time | 102.79 seconds |
| Started | Jul 11 04:30:38 PM PDT 24 |
| Finished | Jul 11 04:32:26 PM PDT 24 |
| Peak memory | 198652 kb |
| Host | smart-977ed67e-395a-4a1c-a4aa-6477f9714513 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386040600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. gpio_stress_all.2386040600 |
| Directory | /workspace/20.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/21.gpio_alert_test.577383145 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 15023220 ps |
| CPU time | 0.57 seconds |
| Started | Jul 11 04:30:53 PM PDT 24 |
| Finished | Jul 11 04:30:59 PM PDT 24 |
| Peak memory | 194580 kb |
| Host | smart-763e23b3-924a-4da6-955b-66c7b9c3b1fa |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577383145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.577383145 |
| Directory | /workspace/21.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2844145150 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 201599603 ps |
| CPU time | 0.86 seconds |
| Started | Jul 11 04:30:22 PM PDT 24 |
| Finished | Jul 11 04:30:35 PM PDT 24 |
| Peak memory | 196676 kb |
| Host | smart-8bfe09ac-4ae3-41d5-b03f-c5ae1443463b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2844145150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2844145150 |
| Directory | /workspace/21.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/21.gpio_filter_stress.729262679 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 663408873 ps |
| CPU time | 21.48 seconds |
| Started | Jul 11 04:30:37 PM PDT 24 |
| Finished | Jul 11 04:31:05 PM PDT 24 |
| Peak memory | 196008 kb |
| Host | smart-21ecb53b-7032-45a1-a132-b5e743d442ee |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729262679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stres s.729262679 |
| Directory | /workspace/21.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/21.gpio_full_random.3260711974 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 298274717 ps |
| CPU time | 1 seconds |
| Started | Jul 11 04:30:52 PM PDT 24 |
| Finished | Jul 11 04:30:58 PM PDT 24 |
| Peak memory | 198412 kb |
| Host | smart-6105c64c-3bf8-4638-a275-c5ef7906fd31 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260711974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3260711974 |
| Directory | /workspace/21.gpio_full_random/latest |
| Test location | /workspace/coverage/default/21.gpio_intr_rand_pgm.638231941 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 117223937 ps |
| CPU time | 0.81 seconds |
| Started | Jul 11 04:30:15 PM PDT 24 |
| Finished | Jul 11 04:30:27 PM PDT 24 |
| Peak memory | 197876 kb |
| Host | smart-dd338a09-509f-46f6-a2fa-4d8ea441f583 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638231941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.638231941 |
| Directory | /workspace/21.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.422214305 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 64220926 ps |
| CPU time | 2.5 seconds |
| Started | Jul 11 04:30:39 PM PDT 24 |
| Finished | Jul 11 04:30:47 PM PDT 24 |
| Peak memory | 198680 kb |
| Host | smart-8f0b2e89-dfbe-4bab-b3c3-2f42628fdada |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422214305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 21.gpio_intr_with_filter_rand_intr_event.422214305 |
| Directory | /workspace/21.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/21.gpio_rand_intr_trigger.607326152 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 427759675 ps |
| CPU time | 2.16 seconds |
| Started | Jul 11 04:30:22 PM PDT 24 |
| Finished | Jul 11 04:30:37 PM PDT 24 |
| Peak memory | 196328 kb |
| Host | smart-f6557cea-012b-4257-9296-6a6a990f8ffe |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607326152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger. 607326152 |
| Directory | /workspace/21.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/21.gpio_random_dout_din.1568793382 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 102405296 ps |
| CPU time | 1.3 seconds |
| Started | Jul 11 04:30:21 PM PDT 24 |
| Finished | Jul 11 04:30:36 PM PDT 24 |
| Peak memory | 198612 kb |
| Host | smart-d2db132e-64b7-47bd-8b99-34f3cef9352e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1568793382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1568793382 |
| Directory | /workspace/21.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2132617658 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 62103427 ps |
| CPU time | 1.23 seconds |
| Started | Jul 11 04:30:22 PM PDT 24 |
| Finished | Jul 11 04:30:37 PM PDT 24 |
| Peak memory | 197140 kb |
| Host | smart-9bacd2f6-7ba8-4f5f-bb23-53bf78c41e64 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132617658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu p_pulldown.2132617658 |
| Directory | /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.604717759 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 192165073 ps |
| CPU time | 2.24 seconds |
| Started | Jul 11 04:30:27 PM PDT 24 |
| Finished | Jul 11 04:30:41 PM PDT 24 |
| Peak memory | 198612 kb |
| Host | smart-7cd5289f-17bc-40da-b9b3-8a186de697f0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604717759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran dom_long_reg_writes_reg_reads.604717759 |
| Directory | /workspace/21.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/21.gpio_smoke.2004981640 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 117230371 ps |
| CPU time | 1.02 seconds |
| Started | Jul 11 04:30:20 PM PDT 24 |
| Finished | Jul 11 04:30:35 PM PDT 24 |
| Peak memory | 197140 kb |
| Host | smart-cc960014-5a87-40d4-8c55-72cef12137b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2004981640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2004981640 |
| Directory | /workspace/21.gpio_smoke/latest |
| Test location | /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2046186997 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 105461723 ps |
| CPU time | 1.13 seconds |
| Started | Jul 11 04:30:51 PM PDT 24 |
| Finished | Jul 11 04:30:57 PM PDT 24 |
| Peak memory | 196216 kb |
| Host | smart-39d93ae9-a0f3-4887-8c4f-e94d770d1a66 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046186997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2046186997 |
| Directory | /workspace/21.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/21.gpio_stress_all.463726194 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 6209039779 ps |
| CPU time | 177.76 seconds |
| Started | Jul 11 04:30:35 PM PDT 24 |
| Finished | Jul 11 04:33:40 PM PDT 24 |
| Peak memory | 199036 kb |
| Host | smart-bf8a4221-137b-490f-a88e-8021700a51c5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463726194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g pio_stress_all.463726194 |
| Directory | /workspace/21.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.557837134 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 213302607964 ps |
| CPU time | 834.49 seconds |
| Started | Jul 11 04:30:43 PM PDT 24 |
| Finished | Jul 11 04:44:41 PM PDT 24 |
| Peak memory | 198780 kb |
| Host | smart-762adc7f-b9e6-43c8-9de8-c01788c77a3c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =557837134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.557837134 |
| Directory | /workspace/21.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.gpio_alert_test.4135152033 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 11571458 ps |
| CPU time | 0.56 seconds |
| Started | Jul 11 04:30:36 PM PDT 24 |
| Finished | Jul 11 04:30:43 PM PDT 24 |
| Peak memory | 195232 kb |
| Host | smart-d0174ca8-3c62-4d5a-bae1-39d3dbe815b8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135152033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.4135152033 |
| Directory | /workspace/22.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1152074506 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 32521430 ps |
| CPU time | 0.84 seconds |
| Started | Jul 11 04:30:52 PM PDT 24 |
| Finished | Jul 11 04:30:58 PM PDT 24 |
| Peak memory | 197592 kb |
| Host | smart-d97c6532-c37c-49ff-9cde-b156462a2db1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1152074506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1152074506 |
| Directory | /workspace/22.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/22.gpio_filter_stress.1448964942 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 939985621 ps |
| CPU time | 24.87 seconds |
| Started | Jul 11 04:30:48 PM PDT 24 |
| Finished | Jul 11 04:31:15 PM PDT 24 |
| Peak memory | 198640 kb |
| Host | smart-67727d5b-916d-4b7e-a39e-96e592fcfa58 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448964942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre ss.1448964942 |
| Directory | /workspace/22.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/22.gpio_full_random.1636891569 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 55388816 ps |
| CPU time | 0.86 seconds |
| Started | Jul 11 04:30:59 PM PDT 24 |
| Finished | Jul 11 04:31:05 PM PDT 24 |
| Peak memory | 197612 kb |
| Host | smart-ebd82e14-5fd2-40ba-96c0-996f41117b9a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636891569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1636891569 |
| Directory | /workspace/22.gpio_full_random/latest |
| Test location | /workspace/coverage/default/22.gpio_intr_rand_pgm.1664089299 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 48772651 ps |
| CPU time | 1.23 seconds |
| Started | Jul 11 04:30:51 PM PDT 24 |
| Finished | Jul 11 04:30:57 PM PDT 24 |
| Peak memory | 198616 kb |
| Host | smart-8212a324-f106-40af-8989-b66b120ddd5a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664089299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1664089299 |
| Directory | /workspace/22.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2039865423 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 323619079 ps |
| CPU time | 3.36 seconds |
| Started | Jul 11 04:30:59 PM PDT 24 |
| Finished | Jul 11 04:31:08 PM PDT 24 |
| Peak memory | 198660 kb |
| Host | smart-3abb2afb-737b-42a7-a579-82cbcf050f3f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039865423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2039865423 |
| Directory | /workspace/22.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/22.gpio_rand_intr_trigger.3772303957 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 245840871 ps |
| CPU time | 2.09 seconds |
| Started | Jul 11 04:30:37 PM PDT 24 |
| Finished | Jul 11 04:30:45 PM PDT 24 |
| Peak memory | 196380 kb |
| Host | smart-ed3637c1-d3fa-4704-bd48-165615102869 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772303957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger .3772303957 |
| Directory | /workspace/22.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/22.gpio_random_dout_din.2894162161 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 405083177 ps |
| CPU time | 1.07 seconds |
| Started | Jul 11 04:30:51 PM PDT 24 |
| Finished | Jul 11 04:30:58 PM PDT 24 |
| Peak memory | 197384 kb |
| Host | smart-3181b3d9-30b3-44f4-8784-e4bdf01f28e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2894162161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2894162161 |
| Directory | /workspace/22.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.4038901280 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 39939297 ps |
| CPU time | 0.85 seconds |
| Started | Jul 11 04:30:30 PM PDT 24 |
| Finished | Jul 11 04:30:42 PM PDT 24 |
| Peak memory | 196420 kb |
| Host | smart-9f4d782d-2af6-4b12-bea1-f1c42303afc8 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038901280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu p_pulldown.4038901280 |
| Directory | /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3467697494 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 33934596 ps |
| CPU time | 1.45 seconds |
| Started | Jul 11 04:30:51 PM PDT 24 |
| Finished | Jul 11 04:30:58 PM PDT 24 |
| Peak memory | 198488 kb |
| Host | smart-e1ebb0ec-c921-468d-9672-b6bde0256b3b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467697494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra ndom_long_reg_writes_reg_reads.3467697494 |
| Directory | /workspace/22.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/22.gpio_smoke.1759760054 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 56715518 ps |
| CPU time | 1.29 seconds |
| Started | Jul 11 04:30:53 PM PDT 24 |
| Finished | Jul 11 04:31:00 PM PDT 24 |
| Peak memory | 197216 kb |
| Host | smart-27e91a1b-483e-4f80-890d-e5879fef350a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1759760054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1759760054 |
| Directory | /workspace/22.gpio_smoke/latest |
| Test location | /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3430689840 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 170197642 ps |
| CPU time | 1.39 seconds |
| Started | Jul 11 04:30:36 PM PDT 24 |
| Finished | Jul 11 04:30:44 PM PDT 24 |
| Peak memory | 196116 kb |
| Host | smart-8752011f-a2ba-416f-a24a-854b52139e78 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430689840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3430689840 |
| Directory | /workspace/22.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/22.gpio_stress_all.2484335950 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 6729927506 ps |
| CPU time | 167.36 seconds |
| Started | Jul 11 04:30:40 PM PDT 24 |
| Finished | Jul 11 04:33:32 PM PDT 24 |
| Peak memory | 198668 kb |
| Host | smart-e830aa2c-3321-4683-bd35-e0b9e56df95c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484335950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. gpio_stress_all.2484335950 |
| Directory | /workspace/22.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/23.gpio_alert_test.2320388282 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 59908417 ps |
| CPU time | 0.6 seconds |
| Started | Jul 11 04:30:47 PM PDT 24 |
| Finished | Jul 11 04:30:50 PM PDT 24 |
| Peak memory | 194592 kb |
| Host | smart-0b1eed2e-68bb-4e39-8cfa-b2a305745c0c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320388282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2320388282 |
| Directory | /workspace/23.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1577174027 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 76219095 ps |
| CPU time | 0.85 seconds |
| Started | Jul 11 04:30:53 PM PDT 24 |
| Finished | Jul 11 04:31:00 PM PDT 24 |
| Peak memory | 196688 kb |
| Host | smart-6f267fbb-c446-4f25-a96a-7240b932c51c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1577174027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1577174027 |
| Directory | /workspace/23.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/23.gpio_filter_stress.4181882742 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2660475934 ps |
| CPU time | 21.5 seconds |
| Started | Jul 11 04:30:35 PM PDT 24 |
| Finished | Jul 11 04:31:04 PM PDT 24 |
| Peak memory | 198932 kb |
| Host | smart-66c8c90b-c86d-46c3-b162-565d990e372e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181882742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre ss.4181882742 |
| Directory | /workspace/23.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/23.gpio_full_random.1047468771 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 166938446 ps |
| CPU time | 0.84 seconds |
| Started | Jul 11 04:30:28 PM PDT 24 |
| Finished | Jul 11 04:30:40 PM PDT 24 |
| Peak memory | 197004 kb |
| Host | smart-03cbc31b-50a5-4129-a5cb-872536f9fc51 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047468771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1047468771 |
| Directory | /workspace/23.gpio_full_random/latest |
| Test location | /workspace/coverage/default/23.gpio_intr_rand_pgm.1003615244 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 1102711303 ps |
| CPU time | 1.23 seconds |
| Started | Jul 11 04:30:49 PM PDT 24 |
| Finished | Jul 11 04:30:52 PM PDT 24 |
| Peak memory | 198624 kb |
| Host | smart-3ff6bd2d-4e61-4f6e-868b-94b6d6cae1cc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003615244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1003615244 |
| Directory | /workspace/23.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1105060070 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 71634264 ps |
| CPU time | 2.76 seconds |
| Started | Jul 11 04:30:48 PM PDT 24 |
| Finished | Jul 11 04:30:53 PM PDT 24 |
| Peak memory | 198532 kb |
| Host | smart-41eaf03a-8c1a-48b7-bdd6-2391ac8fe67c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105060070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1105060070 |
| Directory | /workspace/23.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/23.gpio_rand_intr_trigger.901110562 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 128492497 ps |
| CPU time | 2.57 seconds |
| Started | Jul 11 04:30:49 PM PDT 24 |
| Finished | Jul 11 04:30:54 PM PDT 24 |
| Peak memory | 197044 kb |
| Host | smart-d94907c1-5f8d-49fb-98d7-413c0fc67867 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901110562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger. 901110562 |
| Directory | /workspace/23.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/23.gpio_random_dout_din.1992783183 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 124829677 ps |
| CPU time | 1.19 seconds |
| Started | Jul 11 04:31:02 PM PDT 24 |
| Finished | Jul 11 04:31:10 PM PDT 24 |
| Peak memory | 196356 kb |
| Host | smart-a58051db-40bf-4c8f-ab47-6f0c690d417c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1992783183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1992783183 |
| Directory | /workspace/23.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.4039945644 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 16545236 ps |
| CPU time | 0.73 seconds |
| Started | Jul 11 04:30:39 PM PDT 24 |
| Finished | Jul 11 04:30:45 PM PDT 24 |
| Peak memory | 196580 kb |
| Host | smart-20352f07-169c-4b33-abb3-e23f8dcb8f1e |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039945644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu p_pulldown.4039945644 |
| Directory | /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2531460848 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 80931513 ps |
| CPU time | 1.91 seconds |
| Started | Jul 11 04:30:49 PM PDT 24 |
| Finished | Jul 11 04:30:54 PM PDT 24 |
| Peak memory | 198496 kb |
| Host | smart-9a7bd12f-2594-4c4a-8516-6e3bf744babf |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531460848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra ndom_long_reg_writes_reg_reads.2531460848 |
| Directory | /workspace/23.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/23.gpio_smoke.2185800757 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 246786413 ps |
| CPU time | 1.12 seconds |
| Started | Jul 11 04:30:44 PM PDT 24 |
| Finished | Jul 11 04:30:49 PM PDT 24 |
| Peak memory | 197208 kb |
| Host | smart-0906c540-7130-4abe-86ca-4942274a21de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2185800757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2185800757 |
| Directory | /workspace/23.gpio_smoke/latest |
| Test location | /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2213894070 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 165233580 ps |
| CPU time | 1.17 seconds |
| Started | Jul 11 04:30:42 PM PDT 24 |
| Finished | Jul 11 04:30:46 PM PDT 24 |
| Peak memory | 197052 kb |
| Host | smart-93198f86-6005-4ce3-ac1c-41c3b34cdf49 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213894070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2213894070 |
| Directory | /workspace/23.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/23.gpio_stress_all.2771501140 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 11348820839 ps |
| CPU time | 145.16 seconds |
| Started | Jul 11 04:30:53 PM PDT 24 |
| Finished | Jul 11 04:33:24 PM PDT 24 |
| Peak memory | 198668 kb |
| Host | smart-f47f5c58-7016-4061-b4f3-9578865c01a6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771501140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. gpio_stress_all.2771501140 |
| Directory | /workspace/23.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.2894861441 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 20553697969 ps |
| CPU time | 324.84 seconds |
| Started | Jul 11 04:30:38 PM PDT 24 |
| Finished | Jul 11 04:36:08 PM PDT 24 |
| Peak memory | 198768 kb |
| Host | smart-63fb6dfc-4a8f-4fcd-bc98-acc2ec805ddf |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2894861441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.2894861441 |
| Directory | /workspace/23.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.gpio_alert_test.4048617311 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 37898136 ps |
| CPU time | 0.57 seconds |
| Started | Jul 11 04:30:50 PM PDT 24 |
| Finished | Jul 11 04:30:55 PM PDT 24 |
| Peak memory | 195332 kb |
| Host | smart-7702fc5a-a1d1-4493-b862-f6c81af8f36a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048617311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.4048617311 |
| Directory | /workspace/24.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1671402802 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 33903081 ps |
| CPU time | 0.65 seconds |
| Started | Jul 11 04:30:39 PM PDT 24 |
| Finished | Jul 11 04:30:45 PM PDT 24 |
| Peak memory | 195412 kb |
| Host | smart-2ad23496-2cb3-48f8-9087-9af2a77f8e48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1671402802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1671402802 |
| Directory | /workspace/24.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/24.gpio_filter_stress.4123296749 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1058669230 ps |
| CPU time | 15.84 seconds |
| Started | Jul 11 04:30:57 PM PDT 24 |
| Finished | Jul 11 04:31:19 PM PDT 24 |
| Peak memory | 197140 kb |
| Host | smart-9404312b-fa23-4be8-b324-2a41e0c98519 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123296749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre ss.4123296749 |
| Directory | /workspace/24.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/24.gpio_full_random.280881198 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 42229576 ps |
| CPU time | 0.79 seconds |
| Started | Jul 11 04:30:45 PM PDT 24 |
| Finished | Jul 11 04:30:49 PM PDT 24 |
| Peak memory | 197120 kb |
| Host | smart-325b8712-c29d-47f0-b36e-6842717313df |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280881198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.280881198 |
| Directory | /workspace/24.gpio_full_random/latest |
| Test location | /workspace/coverage/default/24.gpio_intr_rand_pgm.3336574153 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 94691344 ps |
| CPU time | 1.2 seconds |
| Started | Jul 11 04:31:07 PM PDT 24 |
| Finished | Jul 11 04:31:18 PM PDT 24 |
| Peak memory | 197188 kb |
| Host | smart-afd0b1cb-abb7-4827-bb5e-c89676ba562e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336574153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3336574153 |
| Directory | /workspace/24.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1460385589 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 275052878 ps |
| CPU time | 2.91 seconds |
| Started | Jul 11 04:30:33 PM PDT 24 |
| Finished | Jul 11 04:30:45 PM PDT 24 |
| Peak memory | 198608 kb |
| Host | smart-1a6de802-2802-4e7d-a79a-bfcc21331f89 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460385589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1460385589 |
| Directory | /workspace/24.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/24.gpio_rand_intr_trigger.4020596632 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 208280248 ps |
| CPU time | 2.88 seconds |
| Started | Jul 11 04:30:43 PM PDT 24 |
| Finished | Jul 11 04:30:50 PM PDT 24 |
| Peak memory | 197568 kb |
| Host | smart-5fe5c766-2781-4a10-9a69-7b21e448d80b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020596632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger .4020596632 |
| Directory | /workspace/24.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/24.gpio_random_dout_din.3866458623 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 32765921 ps |
| CPU time | 0.75 seconds |
| Started | Jul 11 04:31:10 PM PDT 24 |
| Finished | Jul 11 04:31:25 PM PDT 24 |
| Peak memory | 196000 kb |
| Host | smart-c6c6b036-1eeb-43a0-bf8a-6c094129a8ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3866458623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3866458623 |
| Directory | /workspace/24.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.924614194 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 190445528 ps |
| CPU time | 1.01 seconds |
| Started | Jul 11 04:30:51 PM PDT 24 |
| Finished | Jul 11 04:30:57 PM PDT 24 |
| Peak memory | 196352 kb |
| Host | smart-f61767e3-02f8-48c3-bfb1-29e52bb1b4a2 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924614194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup _pulldown.924614194 |
| Directory | /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3437444591 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 243362325 ps |
| CPU time | 3.81 seconds |
| Started | Jul 11 04:30:58 PM PDT 24 |
| Finished | Jul 11 04:31:07 PM PDT 24 |
| Peak memory | 198608 kb |
| Host | smart-62127a4b-0e51-4e28-ba88-6db055a5605b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437444591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra ndom_long_reg_writes_reg_reads.3437444591 |
| Directory | /workspace/24.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/24.gpio_smoke.683506773 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 89416585 ps |
| CPU time | 1.22 seconds |
| Started | Jul 11 04:30:48 PM PDT 24 |
| Finished | Jul 11 04:30:52 PM PDT 24 |
| Peak memory | 196928 kb |
| Host | smart-aeff8e46-45ac-452a-b3ff-48f82a3ca02d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=683506773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.683506773 |
| Directory | /workspace/24.gpio_smoke/latest |
| Test location | /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3213685428 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 98141001 ps |
| CPU time | 0.71 seconds |
| Started | Jul 11 04:30:51 PM PDT 24 |
| Finished | Jul 11 04:30:56 PM PDT 24 |
| Peak memory | 194784 kb |
| Host | smart-cc832f01-df39-4c54-8740-f8ef1634aaff |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213685428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3213685428 |
| Directory | /workspace/24.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/24.gpio_stress_all.2168022155 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 14316786030 ps |
| CPU time | 93.07 seconds |
| Started | Jul 11 04:30:56 PM PDT 24 |
| Finished | Jul 11 04:32:35 PM PDT 24 |
| Peak memory | 198680 kb |
| Host | smart-610a8582-c5ab-4114-90b3-722c1eab11ab |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168022155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24. gpio_stress_all.2168022155 |
| Directory | /workspace/24.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/25.gpio_alert_test.449342339 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 52679171 ps |
| CPU time | 0.59 seconds |
| Started | Jul 11 04:30:46 PM PDT 24 |
| Finished | Jul 11 04:30:50 PM PDT 24 |
| Peak memory | 194636 kb |
| Host | smart-b1268eab-f2d4-4e5b-90e8-a061c643baa9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449342339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.449342339 |
| Directory | /workspace/25.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1608702766 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 47824477 ps |
| CPU time | 0.88 seconds |
| Started | Jul 11 04:30:42 PM PDT 24 |
| Finished | Jul 11 04:30:47 PM PDT 24 |
| Peak memory | 197784 kb |
| Host | smart-6426f0b5-eef3-434b-bd05-7ec0f6a4492d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608702766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1608702766 |
| Directory | /workspace/25.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/25.gpio_filter_stress.1027816693 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 6544191550 ps |
| CPU time | 14.76 seconds |
| Started | Jul 11 04:30:46 PM PDT 24 |
| Finished | Jul 11 04:31:04 PM PDT 24 |
| Peak memory | 198636 kb |
| Host | smart-7b028ed3-4ac1-4ee6-883c-22ff882c8367 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027816693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre ss.1027816693 |
| Directory | /workspace/25.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/25.gpio_full_random.993439772 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 249256555 ps |
| CPU time | 0.9 seconds |
| Started | Jul 11 04:30:51 PM PDT 24 |
| Finished | Jul 11 04:30:56 PM PDT 24 |
| Peak memory | 196412 kb |
| Host | smart-7269930c-bcc2-4fef-a525-dd34b97b837f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993439772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.993439772 |
| Directory | /workspace/25.gpio_full_random/latest |
| Test location | /workspace/coverage/default/25.gpio_intr_rand_pgm.1059105502 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 43723276 ps |
| CPU time | 1.16 seconds |
| Started | Jul 11 04:30:53 PM PDT 24 |
| Finished | Jul 11 04:30:59 PM PDT 24 |
| Peak memory | 197360 kb |
| Host | smart-2795139c-0a02-4555-befa-89b9faa339d4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059105502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1059105502 |
| Directory | /workspace/25.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1402521866 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 36858964 ps |
| CPU time | 1.37 seconds |
| Started | Jul 11 04:30:47 PM PDT 24 |
| Finished | Jul 11 04:30:51 PM PDT 24 |
| Peak memory | 196812 kb |
| Host | smart-469ec715-d843-4979-b1e2-12dab3a00234 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402521866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1402521866 |
| Directory | /workspace/25.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/25.gpio_rand_intr_trigger.247290258 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 76162599 ps |
| CPU time | 1.47 seconds |
| Started | Jul 11 04:31:03 PM PDT 24 |
| Finished | Jul 11 04:31:13 PM PDT 24 |
| Peak memory | 196752 kb |
| Host | smart-5d5a5761-334d-4cc8-9362-f3a9c1873121 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247290258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger. 247290258 |
| Directory | /workspace/25.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/25.gpio_random_dout_din.704714238 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 102523096 ps |
| CPU time | 1.17 seconds |
| Started | Jul 11 04:30:44 PM PDT 24 |
| Finished | Jul 11 04:30:49 PM PDT 24 |
| Peak memory | 198684 kb |
| Host | smart-c14a92a5-bbd8-43f9-aa53-3bc1bae289d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=704714238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.704714238 |
| Directory | /workspace/25.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3943521925 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 289439849 ps |
| CPU time | 1.29 seconds |
| Started | Jul 11 04:31:07 PM PDT 24 |
| Finished | Jul 11 04:31:19 PM PDT 24 |
| Peak memory | 196356 kb |
| Host | smart-060b71f9-32ee-4f76-a5b5-f8e27432b2aa |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943521925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu p_pulldown.3943521925 |
| Directory | /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2559648341 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 1038721112 ps |
| CPU time | 4.58 seconds |
| Started | Jul 11 04:31:03 PM PDT 24 |
| Finished | Jul 11 04:31:16 PM PDT 24 |
| Peak memory | 198532 kb |
| Host | smart-4cae976f-550d-4989-ac8b-0788b0cbac83 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559648341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra ndom_long_reg_writes_reg_reads.2559648341 |
| Directory | /workspace/25.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/25.gpio_smoke.1356587085 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 95240060 ps |
| CPU time | 0.92 seconds |
| Started | Jul 11 04:30:52 PM PDT 24 |
| Finished | Jul 11 04:30:58 PM PDT 24 |
| Peak memory | 195936 kb |
| Host | smart-7aa11bb0-1dba-4da7-a52b-bc04805799ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1356587085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.1356587085 |
| Directory | /workspace/25.gpio_smoke/latest |
| Test location | /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1374710744 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 173303252 ps |
| CPU time | 1.03 seconds |
| Started | Jul 11 04:30:35 PM PDT 24 |
| Finished | Jul 11 04:30:43 PM PDT 24 |
| Peak memory | 196204 kb |
| Host | smart-3bc26c45-75b3-476f-9980-b6fb5e54b610 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374710744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1374710744 |
| Directory | /workspace/25.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/25.gpio_stress_all.3849704108 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 1614745108 ps |
| CPU time | 41.49 seconds |
| Started | Jul 11 04:30:37 PM PDT 24 |
| Finished | Jul 11 04:31:25 PM PDT 24 |
| Peak memory | 198528 kb |
| Host | smart-9cbe4bf9-155d-496d-b230-bdb109d052dc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849704108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. gpio_stress_all.3849704108 |
| Directory | /workspace/25.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.4259990 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 231982981168 ps |
| CPU time | 1021.96 seconds |
| Started | Jul 11 04:31:02 PM PDT 24 |
| Finished | Jul 11 04:48:11 PM PDT 24 |
| Peak memory | 198924 kb |
| Host | smart-ef8b0988-9f68-4473-b70b-cf10f3d09a81 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =4259990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.4259990 |
| Directory | /workspace/25.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/26.gpio_alert_test.859076950 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 14939337 ps |
| CPU time | 0.56 seconds |
| Started | Jul 11 04:30:29 PM PDT 24 |
| Finished | Jul 11 04:30:40 PM PDT 24 |
| Peak memory | 194516 kb |
| Host | smart-5cfa2f4f-ec9f-4ed4-8205-de9ed4fc5781 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859076950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.859076950 |
| Directory | /workspace/26.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1005051947 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 77943309 ps |
| CPU time | 0.68 seconds |
| Started | Jul 11 04:30:53 PM PDT 24 |
| Finished | Jul 11 04:31:00 PM PDT 24 |
| Peak memory | 194680 kb |
| Host | smart-5cba3f30-164a-4f6c-a329-56127064677b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1005051947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1005051947 |
| Directory | /workspace/26.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/26.gpio_filter_stress.3273272246 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 852638139 ps |
| CPU time | 8.18 seconds |
| Started | Jul 11 04:31:05 PM PDT 24 |
| Finished | Jul 11 04:31:23 PM PDT 24 |
| Peak memory | 198548 kb |
| Host | smart-d07f0f99-342c-453c-a39a-2812dbd8879a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273272246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre ss.3273272246 |
| Directory | /workspace/26.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/26.gpio_full_random.2431691705 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 52254061 ps |
| CPU time | 0.76 seconds |
| Started | Jul 11 04:30:50 PM PDT 24 |
| Finished | Jul 11 04:30:55 PM PDT 24 |
| Peak memory | 196960 kb |
| Host | smart-50317fa1-aa45-459d-bf40-53f04dcb5b20 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431691705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2431691705 |
| Directory | /workspace/26.gpio_full_random/latest |
| Test location | /workspace/coverage/default/26.gpio_intr_rand_pgm.4249951186 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 25457077 ps |
| CPU time | 0.69 seconds |
| Started | Jul 11 04:30:37 PM PDT 24 |
| Finished | Jul 11 04:30:44 PM PDT 24 |
| Peak memory | 195640 kb |
| Host | smart-f69221c4-409d-4c54-9c8c-b8ccde7e89bb |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249951186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.4249951186 |
| Directory | /workspace/26.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3065155135 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 88312607 ps |
| CPU time | 3.34 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:31:28 PM PDT 24 |
| Peak memory | 198508 kb |
| Host | smart-76076bf6-d564-46ee-94d7-0ebae7bed3d0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065155135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3065155135 |
| Directory | /workspace/26.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/26.gpio_rand_intr_trigger.527456886 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 252415323 ps |
| CPU time | 2.6 seconds |
| Started | Jul 11 04:30:57 PM PDT 24 |
| Finished | Jul 11 04:31:05 PM PDT 24 |
| Peak memory | 198692 kb |
| Host | smart-8e785baf-5221-4bc7-aa31-a7b9c0e71409 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527456886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger. 527456886 |
| Directory | /workspace/26.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/26.gpio_random_dout_din.2474508583 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 256368926 ps |
| CPU time | 1.14 seconds |
| Started | Jul 11 04:31:07 PM PDT 24 |
| Finished | Jul 11 04:31:18 PM PDT 24 |
| Peak memory | 197700 kb |
| Host | smart-eff0f870-a68c-4a34-a944-2237ab7f39af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2474508583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2474508583 |
| Directory | /workspace/26.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.862564401 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 75886692 ps |
| CPU time | 0.99 seconds |
| Started | Jul 11 04:30:37 PM PDT 24 |
| Finished | Jul 11 04:30:44 PM PDT 24 |
| Peak memory | 196676 kb |
| Host | smart-46803fc9-1682-4d23-9521-c847effa8c07 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862564401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup _pulldown.862564401 |
| Directory | /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1621849469 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 2086058192 ps |
| CPU time | 1.68 seconds |
| Started | Jul 11 04:31:03 PM PDT 24 |
| Finished | Jul 11 04:31:13 PM PDT 24 |
| Peak memory | 198648 kb |
| Host | smart-676a2cb2-55a8-4535-9bef-68cf4625583f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621849469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra ndom_long_reg_writes_reg_reads.1621849469 |
| Directory | /workspace/26.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/26.gpio_smoke.3535669032 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 141444429 ps |
| CPU time | 1.17 seconds |
| Started | Jul 11 04:30:51 PM PDT 24 |
| Finished | Jul 11 04:30:57 PM PDT 24 |
| Peak memory | 196084 kb |
| Host | smart-b69d73dd-1333-4e2a-94d4-a58b6c137709 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3535669032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3535669032 |
| Directory | /workspace/26.gpio_smoke/latest |
| Test location | /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.536532504 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 36624713 ps |
| CPU time | 1.01 seconds |
| Started | Jul 11 04:30:44 PM PDT 24 |
| Finished | Jul 11 04:30:48 PM PDT 24 |
| Peak memory | 197004 kb |
| Host | smart-21eb2e30-7d3c-4946-97bd-c94efdd83729 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536532504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.536532504 |
| Directory | /workspace/26.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/26.gpio_stress_all.3534301647 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 14640922733 ps |
| CPU time | 103.59 seconds |
| Started | Jul 11 04:30:53 PM PDT 24 |
| Finished | Jul 11 04:32:42 PM PDT 24 |
| Peak memory | 198764 kb |
| Host | smart-b5b512e2-453e-4757-ba32-eb311991581c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534301647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. gpio_stress_all.3534301647 |
| Directory | /workspace/26.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.2385959971 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 40803284501 ps |
| CPU time | 204.08 seconds |
| Started | Jul 11 04:30:37 PM PDT 24 |
| Finished | Jul 11 04:34:07 PM PDT 24 |
| Peak memory | 198776 kb |
| Host | smart-a74d6cae-403a-4ce9-9edf-0dbb1bbfe6d4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2385959971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.2385959971 |
| Directory | /workspace/26.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.gpio_alert_test.886123686 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 15667852 ps |
| CPU time | 0.66 seconds |
| Started | Jul 11 04:30:48 PM PDT 24 |
| Finished | Jul 11 04:30:51 PM PDT 24 |
| Peak memory | 195076 kb |
| Host | smart-98261b8b-f0fe-4e9d-960b-e184808b45df |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886123686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.886123686 |
| Directory | /workspace/27.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.4188881969 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 67303964 ps |
| CPU time | 0.63 seconds |
| Started | Jul 11 04:30:52 PM PDT 24 |
| Finished | Jul 11 04:30:58 PM PDT 24 |
| Peak memory | 194584 kb |
| Host | smart-3d02c53c-e87b-4cf5-8c6e-513ddb53d328 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4188881969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.4188881969 |
| Directory | /workspace/27.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/27.gpio_filter_stress.3017788540 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 3484767381 ps |
| CPU time | 24.21 seconds |
| Started | Jul 11 04:31:05 PM PDT 24 |
| Finished | Jul 11 04:31:38 PM PDT 24 |
| Peak memory | 197404 kb |
| Host | smart-2579c01c-97b7-436b-8feb-55a6006f522d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017788540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre ss.3017788540 |
| Directory | /workspace/27.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/27.gpio_full_random.2829194168 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 70338954 ps |
| CPU time | 0.72 seconds |
| Started | Jul 11 04:31:00 PM PDT 24 |
| Finished | Jul 11 04:31:07 PM PDT 24 |
| Peak memory | 195180 kb |
| Host | smart-3cb86a73-fd8a-4b24-9dee-9237bf9523c5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829194168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2829194168 |
| Directory | /workspace/27.gpio_full_random/latest |
| Test location | /workspace/coverage/default/27.gpio_intr_rand_pgm.3131553957 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 42658192 ps |
| CPU time | 0.68 seconds |
| Started | Jul 11 04:30:58 PM PDT 24 |
| Finished | Jul 11 04:31:05 PM PDT 24 |
| Peak memory | 195936 kb |
| Host | smart-7639d5bb-8c38-4328-9b5e-fb1acb62847b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131553957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3131553957 |
| Directory | /workspace/27.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.4107002377 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 90635967 ps |
| CPU time | 3.33 seconds |
| Started | Jul 11 04:30:54 PM PDT 24 |
| Finished | Jul 11 04:31:03 PM PDT 24 |
| Peak memory | 198548 kb |
| Host | smart-0d2a34e9-266e-4526-a65b-7124a27fec37 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107002377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.gpio_intr_with_filter_rand_intr_event.4107002377 |
| Directory | /workspace/27.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/27.gpio_rand_intr_trigger.493445299 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 151030207 ps |
| CPU time | 1.37 seconds |
| Started | Jul 11 04:30:52 PM PDT 24 |
| Finished | Jul 11 04:30:59 PM PDT 24 |
| Peak memory | 197968 kb |
| Host | smart-580587fd-557b-4697-a94a-32ff5d73770a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493445299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger. 493445299 |
| Directory | /workspace/27.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/27.gpio_random_dout_din.945853005 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 260289903 ps |
| CPU time | 1.3 seconds |
| Started | Jul 11 04:31:02 PM PDT 24 |
| Finished | Jul 11 04:31:10 PM PDT 24 |
| Peak memory | 198608 kb |
| Host | smart-dea08b34-abc7-476c-bb5f-9db534ea9a2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945853005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.945853005 |
| Directory | /workspace/27.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2716319433 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 31825626 ps |
| CPU time | 0.83 seconds |
| Started | Jul 11 04:30:52 PM PDT 24 |
| Finished | Jul 11 04:30:59 PM PDT 24 |
| Peak memory | 196060 kb |
| Host | smart-660bf00c-e307-42e3-aa90-7ee165f44f49 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716319433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu p_pulldown.2716319433 |
| Directory | /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2230490598 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 587454068 ps |
| CPU time | 2.73 seconds |
| Started | Jul 11 04:31:07 PM PDT 24 |
| Finished | Jul 11 04:31:22 PM PDT 24 |
| Peak memory | 198240 kb |
| Host | smart-f15e08de-56bf-4ecc-9ce9-17adaf978403 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230490598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra ndom_long_reg_writes_reg_reads.2230490598 |
| Directory | /workspace/27.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/27.gpio_smoke.666025518 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 68449516 ps |
| CPU time | 1.09 seconds |
| Started | Jul 11 04:31:06 PM PDT 24 |
| Finished | Jul 11 04:31:17 PM PDT 24 |
| Peak memory | 196308 kb |
| Host | smart-7e7f5efb-601c-4536-aa2c-e06b50e408e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=666025518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.666025518 |
| Directory | /workspace/27.gpio_smoke/latest |
| Test location | /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.559817901 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 57873865 ps |
| CPU time | 0.98 seconds |
| Started | Jul 11 04:30:52 PM PDT 24 |
| Finished | Jul 11 04:30:58 PM PDT 24 |
| Peak memory | 197104 kb |
| Host | smart-96d0cc04-192e-45d3-9790-9697eb1984cd |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559817901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.559817901 |
| Directory | /workspace/27.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/27.gpio_stress_all.1350989121 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 18304571367 ps |
| CPU time | 58.25 seconds |
| Started | Jul 11 04:31:06 PM PDT 24 |
| Finished | Jul 11 04:32:14 PM PDT 24 |
| Peak memory | 198668 kb |
| Host | smart-c315a4c5-22b8-476c-95dc-f918b03eeb22 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350989121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. gpio_stress_all.1350989121 |
| Directory | /workspace/27.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/28.gpio_alert_test.3230409222 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 47637073 ps |
| CPU time | 0.6 seconds |
| Started | Jul 11 04:32:05 PM PDT 24 |
| Finished | Jul 11 04:32:34 PM PDT 24 |
| Peak memory | 194408 kb |
| Host | smart-b99cebde-505d-487d-97c9-a3b3b91d31ec |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230409222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3230409222 |
| Directory | /workspace/28.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.995884480 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 86053656 ps |
| CPU time | 0.88 seconds |
| Started | Jul 11 04:31:05 PM PDT 24 |
| Finished | Jul 11 04:31:16 PM PDT 24 |
| Peak memory | 197040 kb |
| Host | smart-2a166d9a-0d63-4e2c-9216-ce7f9cf57aac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=995884480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.995884480 |
| Directory | /workspace/28.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/28.gpio_filter_stress.659569493 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 667789555 ps |
| CPU time | 4.23 seconds |
| Started | Jul 11 04:31:01 PM PDT 24 |
| Finished | Jul 11 04:31:11 PM PDT 24 |
| Peak memory | 196032 kb |
| Host | smart-50179e37-bc0a-480b-9d77-847dd494e902 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659569493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres s.659569493 |
| Directory | /workspace/28.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/28.gpio_full_random.3369829338 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 259853617 ps |
| CPU time | 0.94 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:31:26 PM PDT 24 |
| Peak memory | 196768 kb |
| Host | smart-a6a659e0-5115-4843-b009-0982d47a4929 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369829338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3369829338 |
| Directory | /workspace/28.gpio_full_random/latest |
| Test location | /workspace/coverage/default/28.gpio_intr_rand_pgm.2224920577 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 75559783 ps |
| CPU time | 0.94 seconds |
| Started | Jul 11 04:31:03 PM PDT 24 |
| Finished | Jul 11 04:31:12 PM PDT 24 |
| Peak memory | 196524 kb |
| Host | smart-785f4c37-a48b-460c-a512-f335d76c01a9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224920577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2224920577 |
| Directory | /workspace/28.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.304821621 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 86590785 ps |
| CPU time | 1.06 seconds |
| Started | Jul 11 04:30:49 PM PDT 24 |
| Finished | Jul 11 04:30:52 PM PDT 24 |
| Peak memory | 197264 kb |
| Host | smart-ee1dea5f-c4db-458e-abe1-81188c873852 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304821621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 28.gpio_intr_with_filter_rand_intr_event.304821621 |
| Directory | /workspace/28.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/28.gpio_rand_intr_trigger.4032854627 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 154661847 ps |
| CPU time | 1.79 seconds |
| Started | Jul 11 04:30:49 PM PDT 24 |
| Finished | Jul 11 04:30:53 PM PDT 24 |
| Peak memory | 196412 kb |
| Host | smart-75c34ebd-8475-4aba-b336-7a515961979c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032854627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger .4032854627 |
| Directory | /workspace/28.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/28.gpio_random_dout_din.825470153 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 79186790 ps |
| CPU time | 1.01 seconds |
| Started | Jul 11 04:30:52 PM PDT 24 |
| Finished | Jul 11 04:30:58 PM PDT 24 |
| Peak memory | 196564 kb |
| Host | smart-35e3b864-6b1a-4bcc-9aaf-967cfe2dcaa2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=825470153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.825470153 |
| Directory | /workspace/28.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1941654372 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 60263104 ps |
| CPU time | 0.89 seconds |
| Started | Jul 11 04:30:53 PM PDT 24 |
| Finished | Jul 11 04:30:59 PM PDT 24 |
| Peak memory | 197692 kb |
| Host | smart-f29b3dab-9509-4c99-9315-966c1d38418b |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941654372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu p_pulldown.1941654372 |
| Directory | /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3121361405 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 441048851 ps |
| CPU time | 5.01 seconds |
| Started | Jul 11 04:30:48 PM PDT 24 |
| Finished | Jul 11 04:30:56 PM PDT 24 |
| Peak memory | 198476 kb |
| Host | smart-02e71390-f3f3-4a67-bf93-0a022e1f198e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121361405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra ndom_long_reg_writes_reg_reads.3121361405 |
| Directory | /workspace/28.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/28.gpio_smoke.1658736105 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 161769981 ps |
| CPU time | 1.33 seconds |
| Started | Jul 11 04:30:51 PM PDT 24 |
| Finished | Jul 11 04:30:57 PM PDT 24 |
| Peak memory | 196192 kb |
| Host | smart-7b35e8cc-291c-4712-a304-add72033f800 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658736105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1658736105 |
| Directory | /workspace/28.gpio_smoke/latest |
| Test location | /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2738984124 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 90616671 ps |
| CPU time | 1.02 seconds |
| Started | Jul 11 04:31:03 PM PDT 24 |
| Finished | Jul 11 04:31:11 PM PDT 24 |
| Peak memory | 197084 kb |
| Host | smart-829ad70a-bf8c-4958-8429-67b80a16ed88 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738984124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2738984124 |
| Directory | /workspace/28.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/28.gpio_stress_all.136869505 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 5480930372 ps |
| CPU time | 139.04 seconds |
| Started | Jul 11 04:32:03 PM PDT 24 |
| Finished | Jul 11 04:34:50 PM PDT 24 |
| Peak memory | 198656 kb |
| Host | smart-3cc06ec1-9afa-432b-ba9e-89596be16c17 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136869505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g pio_stress_all.136869505 |
| Directory | /workspace/28.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/29.gpio_alert_test.3441461510 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 54163233 ps |
| CPU time | 0.66 seconds |
| Started | Jul 11 04:30:58 PM PDT 24 |
| Finished | Jul 11 04:31:05 PM PDT 24 |
| Peak memory | 194616 kb |
| Host | smart-cb2426aa-3e87-498d-91be-1e4ea5f1a755 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441461510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3441461510 |
| Directory | /workspace/29.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1969540851 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 39373358 ps |
| CPU time | 0.95 seconds |
| Started | Jul 11 04:30:58 PM PDT 24 |
| Finished | Jul 11 04:31:05 PM PDT 24 |
| Peak memory | 196960 kb |
| Host | smart-5cca6945-77c3-4c27-a9aa-421caca8774c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1969540851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1969540851 |
| Directory | /workspace/29.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/29.gpio_filter_stress.3928101934 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1074891096 ps |
| CPU time | 28.01 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:31:53 PM PDT 24 |
| Peak memory | 197276 kb |
| Host | smart-26487ad8-3f69-4b86-b888-5b0263e78268 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928101934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre ss.3928101934 |
| Directory | /workspace/29.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/29.gpio_full_random.3018803864 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 110266396 ps |
| CPU time | 0.82 seconds |
| Started | Jul 11 04:31:06 PM PDT 24 |
| Finished | Jul 11 04:31:16 PM PDT 24 |
| Peak memory | 196556 kb |
| Host | smart-6ddf10ab-f05c-44ea-8da9-e14527278c9d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018803864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3018803864 |
| Directory | /workspace/29.gpio_full_random/latest |
| Test location | /workspace/coverage/default/29.gpio_intr_rand_pgm.2587110774 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 53060757 ps |
| CPU time | 0.84 seconds |
| Started | Jul 11 04:31:05 PM PDT 24 |
| Finished | Jul 11 04:31:16 PM PDT 24 |
| Peak memory | 195980 kb |
| Host | smart-abd116f5-b6f4-41a8-af83-5f52e31478d6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587110774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2587110774 |
| Directory | /workspace/29.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.659128005 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 21461448 ps |
| CPU time | 0.93 seconds |
| Started | Jul 11 04:32:05 PM PDT 24 |
| Finished | Jul 11 04:32:34 PM PDT 24 |
| Peak memory | 197300 kb |
| Host | smart-118d180c-93a6-4bd7-85d0-0e818ef66594 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659128005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 29.gpio_intr_with_filter_rand_intr_event.659128005 |
| Directory | /workspace/29.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/29.gpio_rand_intr_trigger.3601986134 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 98694941 ps |
| CPU time | 2.83 seconds |
| Started | Jul 11 04:32:05 PM PDT 24 |
| Finished | Jul 11 04:32:36 PM PDT 24 |
| Peak memory | 196052 kb |
| Host | smart-947bac6f-6e0d-4b31-8670-958fc1740056 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601986134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger .3601986134 |
| Directory | /workspace/29.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/29.gpio_random_dout_din.1008155646 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 45280701 ps |
| CPU time | 0.85 seconds |
| Started | Jul 11 04:39:01 PM PDT 24 |
| Finished | Jul 11 04:39:02 PM PDT 24 |
| Peak memory | 196752 kb |
| Host | smart-01871fc6-3b86-4c6f-8633-5c44ba4ce886 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1008155646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1008155646 |
| Directory | /workspace/29.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1949900866 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 181797414 ps |
| CPU time | 0.88 seconds |
| Started | Jul 11 04:30:50 PM PDT 24 |
| Finished | Jul 11 04:30:54 PM PDT 24 |
| Peak memory | 196012 kb |
| Host | smart-470b8512-7afb-4954-b389-3da8be2acebe |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949900866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu p_pulldown.1949900866 |
| Directory | /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3184078773 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 8263333116 ps |
| CPU time | 4.91 seconds |
| Started | Jul 11 04:30:58 PM PDT 24 |
| Finished | Jul 11 04:31:09 PM PDT 24 |
| Peak memory | 198652 kb |
| Host | smart-e349b877-2fff-46a6-8bcb-5d0b5c9eaf18 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184078773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra ndom_long_reg_writes_reg_reads.3184078773 |
| Directory | /workspace/29.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/29.gpio_smoke.2030690754 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 43352294 ps |
| CPU time | 0.91 seconds |
| Started | Jul 11 04:30:56 PM PDT 24 |
| Finished | Jul 11 04:31:03 PM PDT 24 |
| Peak memory | 195964 kb |
| Host | smart-9fef2498-8fc5-4e2b-a100-d57253c255e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2030690754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2030690754 |
| Directory | /workspace/29.gpio_smoke/latest |
| Test location | /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.15471207 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 276781127 ps |
| CPU time | 1.42 seconds |
| Started | Jul 11 04:30:52 PM PDT 24 |
| Finished | Jul 11 04:30:59 PM PDT 24 |
| Peak memory | 196784 kb |
| Host | smart-48a2a4d5-da43-4262-acee-1a257e79b8fb |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15471207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.15471207 |
| Directory | /workspace/29.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/29.gpio_stress_all.1194510726 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 26143228799 ps |
| CPU time | 238.9 seconds |
| Started | Jul 11 04:30:57 PM PDT 24 |
| Finished | Jul 11 04:35:01 PM PDT 24 |
| Peak memory | 198648 kb |
| Host | smart-84438061-d14c-4952-a3b1-e573dbbe82a4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194510726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. gpio_stress_all.1194510726 |
| Directory | /workspace/29.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.3809183047 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 99052288619 ps |
| CPU time | 2265.79 seconds |
| Started | Jul 11 04:31:10 PM PDT 24 |
| Finished | Jul 11 05:09:10 PM PDT 24 |
| Peak memory | 198720 kb |
| Host | smart-f467dea2-82ad-4dfe-be15-d5ce45104e24 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3809183047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.3809183047 |
| Directory | /workspace/29.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.gpio_alert_test.4184338780 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 36972154 ps |
| CPU time | 0.56 seconds |
| Started | Jul 11 04:29:54 PM PDT 24 |
| Finished | Jul 11 04:29:59 PM PDT 24 |
| Peak memory | 195228 kb |
| Host | smart-631d940d-ac1a-4da9-9171-65bd56e2bd9f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184338780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.4184338780 |
| Directory | /workspace/3.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1004921141 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 21943337 ps |
| CPU time | 0.76 seconds |
| Started | Jul 11 04:30:01 PM PDT 24 |
| Finished | Jul 11 04:30:11 PM PDT 24 |
| Peak memory | 195980 kb |
| Host | smart-58cd2896-39f9-4294-91af-c05416c0539a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1004921141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1004921141 |
| Directory | /workspace/3.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/3.gpio_filter_stress.493082550 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 406856242 ps |
| CPU time | 12.13 seconds |
| Started | Jul 11 04:30:02 PM PDT 24 |
| Finished | Jul 11 04:30:23 PM PDT 24 |
| Peak memory | 197412 kb |
| Host | smart-e785a6b0-67f0-4b85-8000-e83bf28dd3ed |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493082550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress .493082550 |
| Directory | /workspace/3.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/3.gpio_full_random.1318051148 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 426733684 ps |
| CPU time | 0.89 seconds |
| Started | Jul 11 04:29:58 PM PDT 24 |
| Finished | Jul 11 04:30:06 PM PDT 24 |
| Peak memory | 197304 kb |
| Host | smart-33e5d035-e1b0-477f-8177-2aef57a5086b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318051148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1318051148 |
| Directory | /workspace/3.gpio_full_random/latest |
| Test location | /workspace/coverage/default/3.gpio_intr_rand_pgm.3595706803 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 343551471 ps |
| CPU time | 1.25 seconds |
| Started | Jul 11 04:29:55 PM PDT 24 |
| Finished | Jul 11 04:30:01 PM PDT 24 |
| Peak memory | 197580 kb |
| Host | smart-bd1dea0d-7dcb-4e20-9d9c-8c8e9f8bc2c7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595706803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3595706803 |
| Directory | /workspace/3.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.528654814 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 162104104 ps |
| CPU time | 1.68 seconds |
| Started | Jul 11 04:29:59 PM PDT 24 |
| Finished | Jul 11 04:30:09 PM PDT 24 |
| Peak memory | 198528 kb |
| Host | smart-53c09a27-6b76-4f82-bd22-f3c702c9a4c4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528654814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 3.gpio_intr_with_filter_rand_intr_event.528654814 |
| Directory | /workspace/3.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/3.gpio_rand_intr_trigger.2261891678 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 48414718 ps |
| CPU time | 0.96 seconds |
| Started | Jul 11 04:29:54 PM PDT 24 |
| Finished | Jul 11 04:29:59 PM PDT 24 |
| Peak memory | 196732 kb |
| Host | smart-28007a3f-d92f-47af-9df4-9be1e694134d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261891678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger. 2261891678 |
| Directory | /workspace/3.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/3.gpio_random_dout_din.830409834 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 28891966 ps |
| CPU time | 0.68 seconds |
| Started | Jul 11 04:29:45 PM PDT 24 |
| Finished | Jul 11 04:29:48 PM PDT 24 |
| Peak memory | 195480 kb |
| Host | smart-30de5124-6579-4b1d-b530-1ae5b803fd2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=830409834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.830409834 |
| Directory | /workspace/3.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2028636464 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 220899059 ps |
| CPU time | 1.12 seconds |
| Started | Jul 11 04:29:55 PM PDT 24 |
| Finished | Jul 11 04:30:01 PM PDT 24 |
| Peak memory | 197084 kb |
| Host | smart-4068b32e-f069-4579-87f8-27f5d6561ee9 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028636464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup _pulldown.2028636464 |
| Directory | /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.874735061 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 202230464 ps |
| CPU time | 4.19 seconds |
| Started | Jul 11 04:29:54 PM PDT 24 |
| Finished | Jul 11 04:30:03 PM PDT 24 |
| Peak memory | 198564 kb |
| Host | smart-18363764-13e3-497f-ba4d-47a205816cb7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874735061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand om_long_reg_writes_reg_reads.874735061 |
| Directory | /workspace/3.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/3.gpio_sec_cm.933057041 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 122655363 ps |
| CPU time | 0.96 seconds |
| Started | Jul 11 04:29:59 PM PDT 24 |
| Finished | Jul 11 04:30:09 PM PDT 24 |
| Peak memory | 215296 kb |
| Host | smart-d9d7c3d7-ba05-4911-8bbd-4e70895bdc5a |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933057041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.933057041 |
| Directory | /workspace/3.gpio_sec_cm/latest |
| Test location | /workspace/coverage/default/3.gpio_smoke.4164579575 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 400232663 ps |
| CPU time | 1.13 seconds |
| Started | Jul 11 04:29:53 PM PDT 24 |
| Finished | Jul 11 04:29:58 PM PDT 24 |
| Peak memory | 196292 kb |
| Host | smart-66b7f6c6-3c0f-4225-9a0a-3369e4e2697e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4164579575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.4164579575 |
| Directory | /workspace/3.gpio_smoke/latest |
| Test location | /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3883488901 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 156443540 ps |
| CPU time | 1.27 seconds |
| Started | Jul 11 04:30:08 PM PDT 24 |
| Finished | Jul 11 04:30:16 PM PDT 24 |
| Peak memory | 197236 kb |
| Host | smart-8dd91ab5-bcb1-4a5d-88da-d7c0ce5ab83b |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883488901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3883488901 |
| Directory | /workspace/3.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/3.gpio_stress_all.3324773101 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 3402798204 ps |
| CPU time | 46.34 seconds |
| Started | Jul 11 04:29:52 PM PDT 24 |
| Finished | Jul 11 04:30:41 PM PDT 24 |
| Peak memory | 198640 kb |
| Host | smart-ab98eaa2-f5aa-4745-9766-3ab9ecbfda06 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324773101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g pio_stress_all.3324773101 |
| Directory | /workspace/3.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/30.gpio_alert_test.3972620664 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 13057441 ps |
| CPU time | 0.56 seconds |
| Started | Jul 11 04:31:00 PM PDT 24 |
| Finished | Jul 11 04:31:06 PM PDT 24 |
| Peak memory | 195228 kb |
| Host | smart-2b83bb5c-521f-44e6-bf58-128ab3477d4b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972620664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3972620664 |
| Directory | /workspace/30.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.891120691 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 78973321 ps |
| CPU time | 0.72 seconds |
| Started | Jul 11 04:31:10 PM PDT 24 |
| Finished | Jul 11 04:31:25 PM PDT 24 |
| Peak memory | 196416 kb |
| Host | smart-40051afc-064b-4e7e-aba8-60fa5f71f3f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=891120691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.891120691 |
| Directory | /workspace/30.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/30.gpio_filter_stress.3722813075 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 981226466 ps |
| CPU time | 7.6 seconds |
| Started | Jul 11 04:31:14 PM PDT 24 |
| Finished | Jul 11 04:31:39 PM PDT 24 |
| Peak memory | 198648 kb |
| Host | smart-a4e66518-3f33-4480-a62f-acf387149a1b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722813075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre ss.3722813075 |
| Directory | /workspace/30.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/30.gpio_full_random.3911563975 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 449394086 ps |
| CPU time | 0.65 seconds |
| Started | Jul 11 04:31:55 PM PDT 24 |
| Finished | Jul 11 04:32:21 PM PDT 24 |
| Peak memory | 194036 kb |
| Host | smart-142be89a-603f-4a92-90d4-dd819626506d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911563975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3911563975 |
| Directory | /workspace/30.gpio_full_random/latest |
| Test location | /workspace/coverage/default/30.gpio_intr_rand_pgm.3927005362 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 194029096 ps |
| CPU time | 1.25 seconds |
| Started | Jul 11 04:32:04 PM PDT 24 |
| Finished | Jul 11 04:32:35 PM PDT 24 |
| Peak memory | 197272 kb |
| Host | smart-c194e347-4f1d-48b9-9f1a-303d8a309d98 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927005362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3927005362 |
| Directory | /workspace/30.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1822753326 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 22149311 ps |
| CPU time | 1.05 seconds |
| Started | Jul 11 04:30:44 PM PDT 24 |
| Finished | Jul 11 04:30:49 PM PDT 24 |
| Peak memory | 196848 kb |
| Host | smart-efbaf216-6619-48f5-8e4e-a405409447df |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822753326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1822753326 |
| Directory | /workspace/30.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/30.gpio_rand_intr_trigger.658996487 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 529568805 ps |
| CPU time | 1.52 seconds |
| Started | Jul 11 04:30:40 PM PDT 24 |
| Finished | Jul 11 04:30:46 PM PDT 24 |
| Peak memory | 197132 kb |
| Host | smart-a9833178-2cf4-431a-8be1-26def4037b63 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658996487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger. 658996487 |
| Directory | /workspace/30.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/30.gpio_random_dout_din.333411929 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 294990221 ps |
| CPU time | 0.89 seconds |
| Started | Jul 11 04:31:00 PM PDT 24 |
| Finished | Jul 11 04:31:07 PM PDT 24 |
| Peak memory | 197192 kb |
| Host | smart-da59363d-bf63-4f1f-8e4b-68a272d8a7f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=333411929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.333411929 |
| Directory | /workspace/30.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1545523841 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 99272235 ps |
| CPU time | 1.1 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:31:26 PM PDT 24 |
| Peak memory | 196832 kb |
| Host | smart-42da77a6-9ff2-4569-b1ed-0ed60128bc45 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545523841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu p_pulldown.1545523841 |
| Directory | /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2202646182 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 736903748 ps |
| CPU time | 2.97 seconds |
| Started | Jul 11 04:30:55 PM PDT 24 |
| Finished | Jul 11 04:31:03 PM PDT 24 |
| Peak memory | 198508 kb |
| Host | smart-4fd52be4-db8e-4a36-b29d-1bf2ee97ffd9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202646182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra ndom_long_reg_writes_reg_reads.2202646182 |
| Directory | /workspace/30.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/30.gpio_smoke.2995231141 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 83266181 ps |
| CPU time | 1.51 seconds |
| Started | Jul 11 04:30:49 PM PDT 24 |
| Finished | Jul 11 04:30:52 PM PDT 24 |
| Peak memory | 197364 kb |
| Host | smart-d1428060-69e9-4c72-86a3-757fabf7adaa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2995231141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2995231141 |
| Directory | /workspace/30.gpio_smoke/latest |
| Test location | /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.638714368 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 52546002 ps |
| CPU time | 1.41 seconds |
| Started | Jul 11 04:30:50 PM PDT 24 |
| Finished | Jul 11 04:30:54 PM PDT 24 |
| Peak memory | 198532 kb |
| Host | smart-4fa3f6cd-0b03-4f5d-9126-173c1fc52863 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638714368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.638714368 |
| Directory | /workspace/30.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/30.gpio_stress_all.973366652 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 3601232149 ps |
| CPU time | 19.97 seconds |
| Started | Jul 11 04:31:02 PM PDT 24 |
| Finished | Jul 11 04:31:29 PM PDT 24 |
| Peak memory | 198636 kb |
| Host | smart-ff047f81-98ee-41c5-a72c-9128ad3ffc8d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973366652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.g pio_stress_all.973366652 |
| Directory | /workspace/30.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.777082714 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 793055738970 ps |
| CPU time | 1840.14 seconds |
| Started | Jul 11 04:31:13 PM PDT 24 |
| Finished | Jul 11 05:02:10 PM PDT 24 |
| Peak memory | 207028 kb |
| Host | smart-65c10d0a-7b53-46a2-bf9c-65d5d18b4eda |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =777082714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.777082714 |
| Directory | /workspace/30.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.gpio_alert_test.2027998918 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 16794984 ps |
| CPU time | 0.59 seconds |
| Started | Jul 11 04:31:05 PM PDT 24 |
| Finished | Jul 11 04:31:14 PM PDT 24 |
| Peak memory | 194852 kb |
| Host | smart-213d4b5b-8d64-4ff8-a825-7c6cbe3ac84f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027998918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2027998918 |
| Directory | /workspace/31.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2254811085 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 22594430 ps |
| CPU time | 0.72 seconds |
| Started | Jul 11 04:30:57 PM PDT 24 |
| Finished | Jul 11 04:31:03 PM PDT 24 |
| Peak memory | 195388 kb |
| Host | smart-6bed6118-5101-45e0-a5e2-9f268218ee2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2254811085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2254811085 |
| Directory | /workspace/31.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/31.gpio_filter_stress.75061408 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 666373454 ps |
| CPU time | 10.31 seconds |
| Started | Jul 11 04:31:07 PM PDT 24 |
| Finished | Jul 11 04:31:30 PM PDT 24 |
| Peak memory | 198372 kb |
| Host | smart-c2686a55-33fc-4db6-86c6-b6522fab47fe |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75061408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_ stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stress .75061408 |
| Directory | /workspace/31.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/31.gpio_full_random.2255624925 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 88900122 ps |
| CPU time | 1 seconds |
| Started | Jul 11 04:31:05 PM PDT 24 |
| Finished | Jul 11 04:31:16 PM PDT 24 |
| Peak memory | 197168 kb |
| Host | smart-1df4e54a-e066-41f1-92ea-c03ed73ce761 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255624925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2255624925 |
| Directory | /workspace/31.gpio_full_random/latest |
| Test location | /workspace/coverage/default/31.gpio_intr_rand_pgm.3447517431 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 387981555 ps |
| CPU time | 1.24 seconds |
| Started | Jul 11 04:31:07 PM PDT 24 |
| Finished | Jul 11 04:31:17 PM PDT 24 |
| Peak memory | 197560 kb |
| Host | smart-7e080523-098c-4104-9eb5-66ba155a1715 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447517431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3447517431 |
| Directory | /workspace/31.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.304591175 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 174026816 ps |
| CPU time | 1.87 seconds |
| Started | Jul 11 04:30:52 PM PDT 24 |
| Finished | Jul 11 04:30:59 PM PDT 24 |
| Peak memory | 198648 kb |
| Host | smart-36f24f6c-061a-462a-94ae-c93068e2629a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304591175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 31.gpio_intr_with_filter_rand_intr_event.304591175 |
| Directory | /workspace/31.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/31.gpio_rand_intr_trigger.1900018044 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 155659089 ps |
| CPU time | 1.74 seconds |
| Started | Jul 11 04:31:07 PM PDT 24 |
| Finished | Jul 11 04:31:20 PM PDT 24 |
| Peak memory | 197504 kb |
| Host | smart-9bf318ab-1777-4685-bf77-6bb69c2c4bd2 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900018044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger .1900018044 |
| Directory | /workspace/31.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/31.gpio_random_dout_din.3349926143 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 76512276 ps |
| CPU time | 0.94 seconds |
| Started | Jul 11 04:30:54 PM PDT 24 |
| Finished | Jul 11 04:31:00 PM PDT 24 |
| Peak memory | 196592 kb |
| Host | smart-60d10067-c1f0-4187-b14c-817c91cc48e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3349926143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3349926143 |
| Directory | /workspace/31.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2559594884 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 70829727 ps |
| CPU time | 0.9 seconds |
| Started | Jul 11 04:30:58 PM PDT 24 |
| Finished | Jul 11 04:31:05 PM PDT 24 |
| Peak memory | 196412 kb |
| Host | smart-9878f112-3e2f-4e03-8bac-eeadcbccf1e2 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559594884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu p_pulldown.2559594884 |
| Directory | /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1813928106 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 101431211 ps |
| CPU time | 4.39 seconds |
| Started | Jul 11 04:31:03 PM PDT 24 |
| Finished | Jul 11 04:31:16 PM PDT 24 |
| Peak memory | 198580 kb |
| Host | smart-59fd2aef-86bf-40a3-a0ac-819f3c278daa |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813928106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra ndom_long_reg_writes_reg_reads.1813928106 |
| Directory | /workspace/31.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/31.gpio_smoke.1389105701 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 813147747 ps |
| CPU time | 1.23 seconds |
| Started | Jul 11 04:30:58 PM PDT 24 |
| Finished | Jul 11 04:31:05 PM PDT 24 |
| Peak memory | 197380 kb |
| Host | smart-ed425011-1d8a-4abc-b117-37755bd09a40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1389105701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1389105701 |
| Directory | /workspace/31.gpio_smoke/latest |
| Test location | /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.504389121 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 97902291 ps |
| CPU time | 0.94 seconds |
| Started | Jul 11 04:31:00 PM PDT 24 |
| Finished | Jul 11 04:31:08 PM PDT 24 |
| Peak memory | 196436 kb |
| Host | smart-15ea7edb-b0bf-4267-a2ca-21d385570ecd |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504389121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.504389121 |
| Directory | /workspace/31.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/31.gpio_stress_all.3645607740 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 14593967411 ps |
| CPU time | 164.45 seconds |
| Started | Jul 11 04:31:08 PM PDT 24 |
| Finished | Jul 11 04:34:05 PM PDT 24 |
| Peak memory | 198768 kb |
| Host | smart-02ce04ae-f59e-4919-90fb-bef58472d13a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645607740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. gpio_stress_all.3645607740 |
| Directory | /workspace/31.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/32.gpio_alert_test.67940958 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 33139251 ps |
| CPU time | 0.56 seconds |
| Started | Jul 11 04:30:53 PM PDT 24 |
| Finished | Jul 11 04:31:00 PM PDT 24 |
| Peak memory | 195216 kb |
| Host | smart-a8e698e5-611e-40b5-8a45-5538a6c82bbb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67940958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.67940958 |
| Directory | /workspace/32.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1300419799 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 42711543 ps |
| CPU time | 0.87 seconds |
| Started | Jul 11 04:31:07 PM PDT 24 |
| Finished | Jul 11 04:31:17 PM PDT 24 |
| Peak memory | 196344 kb |
| Host | smart-ea13c23a-1640-4b23-85ce-6cea90a79618 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1300419799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1300419799 |
| Directory | /workspace/32.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/32.gpio_filter_stress.3153970469 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 389962959 ps |
| CPU time | 17.5 seconds |
| Started | Jul 11 04:31:04 PM PDT 24 |
| Finished | Jul 11 04:31:30 PM PDT 24 |
| Peak memory | 197292 kb |
| Host | smart-220ec4d9-3b6b-4e3e-beea-c849a18011c2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153970469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre ss.3153970469 |
| Directory | /workspace/32.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/32.gpio_full_random.1821824123 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 64749759 ps |
| CPU time | 0.88 seconds |
| Started | Jul 11 04:31:04 PM PDT 24 |
| Finished | Jul 11 04:31:13 PM PDT 24 |
| Peak memory | 196540 kb |
| Host | smart-cfdd7b9f-52af-43c4-b71a-01dbff829653 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821824123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1821824123 |
| Directory | /workspace/32.gpio_full_random/latest |
| Test location | /workspace/coverage/default/32.gpio_intr_rand_pgm.2191845652 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 26147158 ps |
| CPU time | 0.68 seconds |
| Started | Jul 11 04:30:54 PM PDT 24 |
| Finished | Jul 11 04:31:01 PM PDT 24 |
| Peak memory | 195812 kb |
| Host | smart-a67b46ff-b6d1-475e-bbd7-b504a718a73d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191845652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2191845652 |
| Directory | /workspace/32.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2731199240 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 52863901 ps |
| CPU time | 1.14 seconds |
| Started | Jul 11 04:31:15 PM PDT 24 |
| Finished | Jul 11 04:31:33 PM PDT 24 |
| Peak memory | 197016 kb |
| Host | smart-664d124c-9666-4013-a247-57c53ce31760 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731199240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2731199240 |
| Directory | /workspace/32.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/32.gpio_rand_intr_trigger.3706411973 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 249849958 ps |
| CPU time | 3.69 seconds |
| Started | Jul 11 04:30:51 PM PDT 24 |
| Finished | Jul 11 04:31:00 PM PDT 24 |
| Peak memory | 197752 kb |
| Host | smart-934c97b3-4bdd-4a14-9914-c3ea1dbc1a15 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706411973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger .3706411973 |
| Directory | /workspace/32.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/32.gpio_random_dout_din.352500486 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 20535600 ps |
| CPU time | 0.81 seconds |
| Started | Jul 11 04:30:58 PM PDT 24 |
| Finished | Jul 11 04:31:05 PM PDT 24 |
| Peak memory | 196116 kb |
| Host | smart-a6da3468-2073-447d-bced-8bd15599658d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=352500486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.352500486 |
| Directory | /workspace/32.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.666959754 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 34067482 ps |
| CPU time | 0.63 seconds |
| Started | Jul 11 04:30:55 PM PDT 24 |
| Finished | Jul 11 04:31:01 PM PDT 24 |
| Peak memory | 194852 kb |
| Host | smart-4dfedffe-10d1-4b90-9f49-e7cbe9a91ed2 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666959754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup _pulldown.666959754 |
| Directory | /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.886861324 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 941723189 ps |
| CPU time | 3.32 seconds |
| Started | Jul 11 04:31:02 PM PDT 24 |
| Finished | Jul 11 04:31:12 PM PDT 24 |
| Peak memory | 198524 kb |
| Host | smart-5d61d6fb-1619-4a66-a15d-8aef7dc9e689 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886861324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran dom_long_reg_writes_reg_reads.886861324 |
| Directory | /workspace/32.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/32.gpio_smoke.3121108611 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 64732926 ps |
| CPU time | 1.23 seconds |
| Started | Jul 11 04:30:51 PM PDT 24 |
| Finished | Jul 11 04:30:57 PM PDT 24 |
| Peak memory | 197144 kb |
| Host | smart-ccaa1918-502d-4ac8-9905-105a9916868f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3121108611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3121108611 |
| Directory | /workspace/32.gpio_smoke/latest |
| Test location | /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2461229484 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 67739784 ps |
| CPU time | 1.32 seconds |
| Started | Jul 11 04:31:01 PM PDT 24 |
| Finished | Jul 11 04:31:09 PM PDT 24 |
| Peak memory | 197372 kb |
| Host | smart-a361c5e3-018b-453b-b958-d9571ca2fe66 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461229484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2461229484 |
| Directory | /workspace/32.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/32.gpio_stress_all.252425191 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 3111932910 ps |
| CPU time | 17.69 seconds |
| Started | Jul 11 04:30:52 PM PDT 24 |
| Finished | Jul 11 04:31:15 PM PDT 24 |
| Peak memory | 198764 kb |
| Host | smart-db637622-d87a-413f-a6ff-83534fe9d524 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252425191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g pio_stress_all.252425191 |
| Directory | /workspace/32.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/33.gpio_alert_test.2279212071 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 41690942 ps |
| CPU time | 0.61 seconds |
| Started | Jul 11 04:30:57 PM PDT 24 |
| Finished | Jul 11 04:31:03 PM PDT 24 |
| Peak memory | 194804 kb |
| Host | smart-14b473ad-6f1b-431b-a6d6-ff316c5d2a39 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279212071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2279212071 |
| Directory | /workspace/33.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.648215920 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 47934211 ps |
| CPU time | 0.68 seconds |
| Started | Jul 11 04:31:00 PM PDT 24 |
| Finished | Jul 11 04:31:06 PM PDT 24 |
| Peak memory | 194768 kb |
| Host | smart-7e59f379-2106-44de-a83c-b9c6c4e31ddc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=648215920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.648215920 |
| Directory | /workspace/33.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/33.gpio_filter_stress.3516579502 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 679291353 ps |
| CPU time | 23.13 seconds |
| Started | Jul 11 04:30:55 PM PDT 24 |
| Finished | Jul 11 04:31:23 PM PDT 24 |
| Peak memory | 198588 kb |
| Host | smart-aefb7325-9939-46b6-adb5-30ff046f347a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516579502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre ss.3516579502 |
| Directory | /workspace/33.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/33.gpio_full_random.3668471935 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 124754437 ps |
| CPU time | 0.95 seconds |
| Started | Jul 11 04:30:50 PM PDT 24 |
| Finished | Jul 11 04:30:56 PM PDT 24 |
| Peak memory | 197312 kb |
| Host | smart-94842ce4-f3db-4d26-9b6f-41e9426df95d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668471935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3668471935 |
| Directory | /workspace/33.gpio_full_random/latest |
| Test location | /workspace/coverage/default/33.gpio_intr_rand_pgm.2553245635 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 25219606 ps |
| CPU time | 0.81 seconds |
| Started | Jul 11 04:30:55 PM PDT 24 |
| Finished | Jul 11 04:31:01 PM PDT 24 |
| Peak memory | 196108 kb |
| Host | smart-04f7dac8-cfc0-430c-83b5-bc91ae56ec1c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553245635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2553245635 |
| Directory | /workspace/33.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.777868823 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 148881802 ps |
| CPU time | 1.6 seconds |
| Started | Jul 11 04:31:02 PM PDT 24 |
| Finished | Jul 11 04:31:11 PM PDT 24 |
| Peak memory | 197036 kb |
| Host | smart-ca9bc05d-daa9-4a84-a2a6-a09d304399d9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777868823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 33.gpio_intr_with_filter_rand_intr_event.777868823 |
| Directory | /workspace/33.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/33.gpio_rand_intr_trigger.4205389630 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 135604919 ps |
| CPU time | 2.59 seconds |
| Started | Jul 11 04:31:00 PM PDT 24 |
| Finished | Jul 11 04:31:09 PM PDT 24 |
| Peak memory | 197488 kb |
| Host | smart-40e19869-98e0-424a-b08b-03d186b811fe |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205389630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger .4205389630 |
| Directory | /workspace/33.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/33.gpio_random_dout_din.913148953 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 30143247 ps |
| CPU time | 0.78 seconds |
| Started | Jul 11 04:31:05 PM PDT 24 |
| Finished | Jul 11 04:31:16 PM PDT 24 |
| Peak memory | 196160 kb |
| Host | smart-7bd8b8e6-9156-4223-adf8-6efd2cb7910d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=913148953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.913148953 |
| Directory | /workspace/33.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.735689980 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 18205223 ps |
| CPU time | 0.73 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:31:27 PM PDT 24 |
| Peak memory | 196032 kb |
| Host | smart-3a00861d-c00a-488f-9a2a-29d0474e82dc |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735689980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup _pulldown.735689980 |
| Directory | /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3641026359 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 108194626 ps |
| CPU time | 4.24 seconds |
| Started | Jul 11 04:31:00 PM PDT 24 |
| Finished | Jul 11 04:31:11 PM PDT 24 |
| Peak memory | 198508 kb |
| Host | smart-cb3358bd-d6b5-4056-8900-22cf47dc9ff2 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641026359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra ndom_long_reg_writes_reg_reads.3641026359 |
| Directory | /workspace/33.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/33.gpio_smoke.628046230 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 176786934 ps |
| CPU time | 0.83 seconds |
| Started | Jul 11 04:30:52 PM PDT 24 |
| Finished | Jul 11 04:30:58 PM PDT 24 |
| Peak memory | 195828 kb |
| Host | smart-cc40c7f7-3dc6-4df0-b746-6978e800a4e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=628046230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.628046230 |
| Directory | /workspace/33.gpio_smoke/latest |
| Test location | /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3781888045 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 212745451 ps |
| CPU time | 0.94 seconds |
| Started | Jul 11 04:31:06 PM PDT 24 |
| Finished | Jul 11 04:31:17 PM PDT 24 |
| Peak memory | 197080 kb |
| Host | smart-caad6ec8-3ef8-46c4-a386-0b47d4df36ab |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781888045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3781888045 |
| Directory | /workspace/33.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/33.gpio_stress_all.388135270 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 2526476512 ps |
| CPU time | 52.06 seconds |
| Started | Jul 11 04:30:57 PM PDT 24 |
| Finished | Jul 11 04:31:55 PM PDT 24 |
| Peak memory | 198732 kb |
| Host | smart-7bc7d035-e20d-4d14-b79f-f840e1c32b51 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388135270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g pio_stress_all.388135270 |
| Directory | /workspace/33.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/34.gpio_alert_test.482033700 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 31677018 ps |
| CPU time | 0.59 seconds |
| Started | Jul 11 04:31:09 PM PDT 24 |
| Finished | Jul 11 04:31:21 PM PDT 24 |
| Peak memory | 194532 kb |
| Host | smart-d09719b3-fe2b-434d-998b-bf56a6cb7a4c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482033700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.482033700 |
| Directory | /workspace/34.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3101473705 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 17992549 ps |
| CPU time | 0.59 seconds |
| Started | Jul 11 04:31:05 PM PDT 24 |
| Finished | Jul 11 04:31:16 PM PDT 24 |
| Peak memory | 195032 kb |
| Host | smart-e8c8ae43-4769-4362-916c-3352e8c4a856 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3101473705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3101473705 |
| Directory | /workspace/34.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/34.gpio_filter_stress.3116893891 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 293249867 ps |
| CPU time | 5.13 seconds |
| Started | Jul 11 04:30:54 PM PDT 24 |
| Finished | Jul 11 04:31:04 PM PDT 24 |
| Peak memory | 197576 kb |
| Host | smart-d548b95e-cff2-4d05-a3e4-1ef380d4b70a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116893891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre ss.3116893891 |
| Directory | /workspace/34.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/34.gpio_full_random.1667737762 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 380098927 ps |
| CPU time | 1.06 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:31:26 PM PDT 24 |
| Peak memory | 196308 kb |
| Host | smart-b9514295-4eb3-4acf-b357-59c475c4163d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667737762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1667737762 |
| Directory | /workspace/34.gpio_full_random/latest |
| Test location | /workspace/coverage/default/34.gpio_intr_rand_pgm.3302462242 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 76917174 ps |
| CPU time | 1.2 seconds |
| Started | Jul 11 04:31:03 PM PDT 24 |
| Finished | Jul 11 04:31:12 PM PDT 24 |
| Peak memory | 197472 kb |
| Host | smart-df5ab3d9-3e62-40ac-8c15-b9bb41fc8a36 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302462242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3302462242 |
| Directory | /workspace/34.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3386793582 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 77139127 ps |
| CPU time | 2.69 seconds |
| Started | Jul 11 04:31:08 PM PDT 24 |
| Finished | Jul 11 04:31:22 PM PDT 24 |
| Peak memory | 198576 kb |
| Host | smart-f0477745-0499-4f31-b8d0-c3c2779ef7a4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386793582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3386793582 |
| Directory | /workspace/34.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/34.gpio_rand_intr_trigger.1444383341 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 80131808 ps |
| CPU time | 2.28 seconds |
| Started | Jul 11 04:31:02 PM PDT 24 |
| Finished | Jul 11 04:31:11 PM PDT 24 |
| Peak memory | 197672 kb |
| Host | smart-51bba855-1727-499a-8b16-82af8a67a650 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444383341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger .1444383341 |
| Directory | /workspace/34.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/34.gpio_random_dout_din.3542156552 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 25276325 ps |
| CPU time | 0.98 seconds |
| Started | Jul 11 04:31:05 PM PDT 24 |
| Finished | Jul 11 04:31:15 PM PDT 24 |
| Peak memory | 197188 kb |
| Host | smart-c313e9ab-6908-48ac-b6a5-3ab9dc595d9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542156552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3542156552 |
| Directory | /workspace/34.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2875025549 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 60579251 ps |
| CPU time | 1.38 seconds |
| Started | Jul 11 04:30:53 PM PDT 24 |
| Finished | Jul 11 04:31:00 PM PDT 24 |
| Peak memory | 198692 kb |
| Host | smart-0f85e038-4c69-4ffc-b359-9d0afcbcdd70 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875025549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu p_pulldown.2875025549 |
| Directory | /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2321050723 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 74140429 ps |
| CPU time | 3.39 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:31:28 PM PDT 24 |
| Peak memory | 198284 kb |
| Host | smart-ef5e1ec5-78fa-4b62-8c96-963dcf41dd97 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321050723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra ndom_long_reg_writes_reg_reads.2321050723 |
| Directory | /workspace/34.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/34.gpio_smoke.4188975012 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 140552016 ps |
| CPU time | 1.2 seconds |
| Started | Jul 11 04:31:01 PM PDT 24 |
| Finished | Jul 11 04:31:08 PM PDT 24 |
| Peak memory | 197012 kb |
| Host | smart-9597cdd7-f819-4d4e-9a9a-613a269dbdaa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4188975012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.4188975012 |
| Directory | /workspace/34.gpio_smoke/latest |
| Test location | /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3357851912 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 160827059 ps |
| CPU time | 1.43 seconds |
| Started | Jul 11 04:30:59 PM PDT 24 |
| Finished | Jul 11 04:31:07 PM PDT 24 |
| Peak memory | 198572 kb |
| Host | smart-37a43a29-936e-4aac-9359-4575ea94dbba |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357851912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3357851912 |
| Directory | /workspace/34.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/34.gpio_stress_all.1679896897 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 5718810498 ps |
| CPU time | 58.08 seconds |
| Started | Jul 11 04:31:12 PM PDT 24 |
| Finished | Jul 11 04:32:26 PM PDT 24 |
| Peak memory | 198648 kb |
| Host | smart-956a195d-dfb8-496a-bc23-d4503b2d9b24 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679896897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. gpio_stress_all.1679896897 |
| Directory | /workspace/34.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/35.gpio_alert_test.4093103709 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 16558140 ps |
| CPU time | 0.57 seconds |
| Started | Jul 11 04:31:12 PM PDT 24 |
| Finished | Jul 11 04:31:29 PM PDT 24 |
| Peak memory | 194720 kb |
| Host | smart-07ed1aa2-c64f-4f62-bcf7-08792693cb63 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093103709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.4093103709 |
| Directory | /workspace/35.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3922219135 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 24329508 ps |
| CPU time | 0.67 seconds |
| Started | Jul 11 04:31:07 PM PDT 24 |
| Finished | Jul 11 04:31:19 PM PDT 24 |
| Peak memory | 195316 kb |
| Host | smart-0bf4e64d-1c92-4c3a-9e78-17b33ff87564 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3922219135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3922219135 |
| Directory | /workspace/35.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/35.gpio_filter_stress.2841533451 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 949561177 ps |
| CPU time | 6.14 seconds |
| Started | Jul 11 04:31:32 PM PDT 24 |
| Finished | Jul 11 04:31:57 PM PDT 24 |
| Peak memory | 198528 kb |
| Host | smart-e3a283e3-e7fc-45b1-98fb-a9134ec54bf9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841533451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre ss.2841533451 |
| Directory | /workspace/35.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/35.gpio_full_random.1058531523 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 134396486 ps |
| CPU time | 0.96 seconds |
| Started | Jul 11 04:31:04 PM PDT 24 |
| Finished | Jul 11 04:31:12 PM PDT 24 |
| Peak memory | 198372 kb |
| Host | smart-f4498ea6-d25b-4ca6-a44e-6a93733bf419 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058531523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.1058531523 |
| Directory | /workspace/35.gpio_full_random/latest |
| Test location | /workspace/coverage/default/35.gpio_intr_rand_pgm.1235641690 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 205675162 ps |
| CPU time | 0.94 seconds |
| Started | Jul 11 04:31:00 PM PDT 24 |
| Finished | Jul 11 04:31:08 PM PDT 24 |
| Peak memory | 196392 kb |
| Host | smart-2270203b-f6c5-496f-857d-04f669fd3710 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235641690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1235641690 |
| Directory | /workspace/35.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/35.gpio_rand_intr_trigger.2881748175 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 96911359 ps |
| CPU time | 2.78 seconds |
| Started | Jul 11 04:31:07 PM PDT 24 |
| Finished | Jul 11 04:31:21 PM PDT 24 |
| Peak memory | 197668 kb |
| Host | smart-44cbcd18-7920-4b55-bdd5-8dd77b60c6ba |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881748175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger .2881748175 |
| Directory | /workspace/35.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/35.gpio_random_dout_din.254182518 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 129212237 ps |
| CPU time | 0.93 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:31:27 PM PDT 24 |
| Peak memory | 197344 kb |
| Host | smart-b92a7766-a5d6-43f2-b479-3228c3ae03eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=254182518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.254182518 |
| Directory | /workspace/35.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.4009921369 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 31597089 ps |
| CPU time | 1.15 seconds |
| Started | Jul 11 04:31:13 PM PDT 24 |
| Finished | Jul 11 04:31:31 PM PDT 24 |
| Peak memory | 196424 kb |
| Host | smart-fbfeef24-6e42-4412-8add-02f625a88ddb |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009921369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu p_pulldown.4009921369 |
| Directory | /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2172203336 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 5403962214 ps |
| CPU time | 4 seconds |
| Started | Jul 11 04:31:02 PM PDT 24 |
| Finished | Jul 11 04:31:13 PM PDT 24 |
| Peak memory | 198680 kb |
| Host | smart-78975ff0-6274-483b-9283-e3d248c59015 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172203336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra ndom_long_reg_writes_reg_reads.2172203336 |
| Directory | /workspace/35.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/35.gpio_smoke.1412852023 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 104881566 ps |
| CPU time | 0.87 seconds |
| Started | Jul 11 04:31:07 PM PDT 24 |
| Finished | Jul 11 04:31:19 PM PDT 24 |
| Peak memory | 196268 kb |
| Host | smart-e4e70d93-5887-4950-9782-fba144a1155d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1412852023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1412852023 |
| Directory | /workspace/35.gpio_smoke/latest |
| Test location | /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.93453528 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 430006603 ps |
| CPU time | 1.26 seconds |
| Started | Jul 11 04:31:06 PM PDT 24 |
| Finished | Jul 11 04:31:17 PM PDT 24 |
| Peak memory | 198640 kb |
| Host | smart-ed28332c-f84a-4bf6-b5eb-3b42c74f70f3 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93453528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.93453528 |
| Directory | /workspace/35.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/35.gpio_stress_all.1855243243 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 16639403860 ps |
| CPU time | 87.6 seconds |
| Started | Jul 11 04:31:19 PM PDT 24 |
| Finished | Jul 11 04:33:05 PM PDT 24 |
| Peak memory | 198804 kb |
| Host | smart-97d23901-56a1-42b2-9436-9c8c1819bc5b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855243243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35. gpio_stress_all.1855243243 |
| Directory | /workspace/35.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.3694748956 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 166184779192 ps |
| CPU time | 1009.01 seconds |
| Started | Jul 11 04:31:10 PM PDT 24 |
| Finished | Jul 11 04:48:13 PM PDT 24 |
| Peak memory | 206984 kb |
| Host | smart-a0097bda-d59c-4232-af7f-18ff499366e2 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3694748956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.3694748956 |
| Directory | /workspace/35.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.gpio_alert_test.863052968 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 21324825 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:31:16 PM PDT 24 |
| Finished | Jul 11 04:31:35 PM PDT 24 |
| Peak memory | 195196 kb |
| Host | smart-5611db54-18b8-4b72-850e-98740de05347 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863052968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.863052968 |
| Directory | /workspace/36.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.4222767078 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 24212155 ps |
| CPU time | 0.77 seconds |
| Started | Jul 11 04:31:00 PM PDT 24 |
| Finished | Jul 11 04:31:08 PM PDT 24 |
| Peak memory | 196596 kb |
| Host | smart-ede6dc5d-3f76-423b-b627-06952e57e175 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4222767078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.4222767078 |
| Directory | /workspace/36.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/36.gpio_filter_stress.2341566916 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 260680674 ps |
| CPU time | 12.69 seconds |
| Started | Jul 11 04:31:02 PM PDT 24 |
| Finished | Jul 11 04:31:21 PM PDT 24 |
| Peak memory | 196072 kb |
| Host | smart-9ae07c63-3980-4025-ab3f-b10db8232b1b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341566916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre ss.2341566916 |
| Directory | /workspace/36.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/36.gpio_full_random.3189557130 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 50147645 ps |
| CPU time | 0.76 seconds |
| Started | Jul 11 04:31:08 PM PDT 24 |
| Finished | Jul 11 04:31:20 PM PDT 24 |
| Peak memory | 196300 kb |
| Host | smart-66ad428b-1581-431a-896e-3d2294f9f5f9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189557130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3189557130 |
| Directory | /workspace/36.gpio_full_random/latest |
| Test location | /workspace/coverage/default/36.gpio_intr_rand_pgm.1591759336 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 66856867 ps |
| CPU time | 0.69 seconds |
| Started | Jul 11 04:31:07 PM PDT 24 |
| Finished | Jul 11 04:31:19 PM PDT 24 |
| Peak memory | 194852 kb |
| Host | smart-d50b5e59-4717-4142-97a1-8fe73be66f59 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591759336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1591759336 |
| Directory | /workspace/36.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3119124331 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 60633481 ps |
| CPU time | 2.25 seconds |
| Started | Jul 11 04:31:07 PM PDT 24 |
| Finished | Jul 11 04:31:22 PM PDT 24 |
| Peak memory | 196932 kb |
| Host | smart-13fdc48e-7659-43c1-ad51-43f2d7f93383 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119124331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3119124331 |
| Directory | /workspace/36.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/36.gpio_rand_intr_trigger.1070335185 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 195183324 ps |
| CPU time | 2.81 seconds |
| Started | Jul 11 04:32:04 PM PDT 24 |
| Finished | Jul 11 04:32:36 PM PDT 24 |
| Peak memory | 196112 kb |
| Host | smart-bbc0382c-b72a-49a5-bc2c-bbbd246d8ed0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070335185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger .1070335185 |
| Directory | /workspace/36.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/36.gpio_random_dout_din.3910002476 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 23137564 ps |
| CPU time | 0.86 seconds |
| Started | Jul 11 04:31:14 PM PDT 24 |
| Finished | Jul 11 04:31:32 PM PDT 24 |
| Peak memory | 196712 kb |
| Host | smart-6f93e8dc-1c11-45fd-8bec-254f00ff45cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3910002476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3910002476 |
| Directory | /workspace/36.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.3315523086 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 241325233 ps |
| CPU time | 1.26 seconds |
| Started | Jul 11 04:31:04 PM PDT 24 |
| Finished | Jul 11 04:31:12 PM PDT 24 |
| Peak memory | 196532 kb |
| Host | smart-b0d0a05b-0531-441d-9ed7-d853b2ad5053 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315523086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu p_pulldown.3315523086 |
| Directory | /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1102130427 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 362282935 ps |
| CPU time | 3.88 seconds |
| Started | Jul 11 04:31:13 PM PDT 24 |
| Finished | Jul 11 04:31:34 PM PDT 24 |
| Peak memory | 198448 kb |
| Host | smart-328006b5-1292-4390-b88f-190689c0d7da |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102130427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra ndom_long_reg_writes_reg_reads.1102130427 |
| Directory | /workspace/36.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/36.gpio_smoke.3956845970 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 51640000 ps |
| CPU time | 1.04 seconds |
| Started | Jul 11 04:31:07 PM PDT 24 |
| Finished | Jul 11 04:31:20 PM PDT 24 |
| Peak memory | 195660 kb |
| Host | smart-859981ba-2e0d-4327-930d-0ceff5fd181f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3956845970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3956845970 |
| Directory | /workspace/36.gpio_smoke/latest |
| Test location | /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1525245630 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 26285599 ps |
| CPU time | 0.74 seconds |
| Started | Jul 11 04:31:07 PM PDT 24 |
| Finished | Jul 11 04:31:18 PM PDT 24 |
| Peak memory | 195668 kb |
| Host | smart-787bc346-2097-4683-859e-3a2106d67958 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525245630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1525245630 |
| Directory | /workspace/36.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/36.gpio_stress_all.3059315000 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 25990835211 ps |
| CPU time | 144.44 seconds |
| Started | Jul 11 04:31:10 PM PDT 24 |
| Finished | Jul 11 04:33:48 PM PDT 24 |
| Peak memory | 198796 kb |
| Host | smart-c1b0faa6-ec70-4785-bdd8-b07747a754a3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059315000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36. gpio_stress_all.3059315000 |
| Directory | /workspace/36.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/37.gpio_alert_test.1007595770 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 49715627 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:32:05 PM PDT 24 |
| Finished | Jul 11 04:32:34 PM PDT 24 |
| Peak memory | 194476 kb |
| Host | smart-a2edc4eb-b614-4edc-a172-fe391c336ee3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007595770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1007595770 |
| Directory | /workspace/37.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1730436783 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 102119100 ps |
| CPU time | 0.82 seconds |
| Started | Jul 11 04:31:07 PM PDT 24 |
| Finished | Jul 11 04:31:19 PM PDT 24 |
| Peak memory | 197056 kb |
| Host | smart-479bc54c-e2df-472b-baab-29d04fedde6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1730436783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1730436783 |
| Directory | /workspace/37.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/37.gpio_filter_stress.628157919 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1394767972 ps |
| CPU time | 9.73 seconds |
| Started | Jul 11 04:32:06 PM PDT 24 |
| Finished | Jul 11 04:32:43 PM PDT 24 |
| Peak memory | 196692 kb |
| Host | smart-aac32ef8-9e9e-4ae0-8bb0-627f3c373770 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628157919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres s.628157919 |
| Directory | /workspace/37.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/37.gpio_full_random.1724825167 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 38868704 ps |
| CPU time | 0.76 seconds |
| Started | Jul 11 04:31:03 PM PDT 24 |
| Finished | Jul 11 04:31:10 PM PDT 24 |
| Peak memory | 196588 kb |
| Host | smart-b977e4f2-3ddb-418c-ba79-3948059c22fb |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724825167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1724825167 |
| Directory | /workspace/37.gpio_full_random/latest |
| Test location | /workspace/coverage/default/37.gpio_intr_rand_pgm.262146292 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 41903396 ps |
| CPU time | 0.78 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:31:27 PM PDT 24 |
| Peak memory | 196672 kb |
| Host | smart-2b677f6c-7753-46dd-9070-2c6075d4b608 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262146292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.262146292 |
| Directory | /workspace/37.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.4197244497 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 176949761 ps |
| CPU time | 1.75 seconds |
| Started | Jul 11 04:32:07 PM PDT 24 |
| Finished | Jul 11 04:32:39 PM PDT 24 |
| Peak memory | 197764 kb |
| Host | smart-b10f3398-ee95-4e29-826d-d10f2df49356 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197244497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 37.gpio_intr_with_filter_rand_intr_event.4197244497 |
| Directory | /workspace/37.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/37.gpio_rand_intr_trigger.228836662 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 114886886 ps |
| CPU time | 3.08 seconds |
| Started | Jul 11 04:32:27 PM PDT 24 |
| Finished | Jul 11 04:33:01 PM PDT 24 |
| Peak memory | 196116 kb |
| Host | smart-c1296ba5-ded9-44b3-a505-6a6052bb2e51 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228836662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger. 228836662 |
| Directory | /workspace/37.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/37.gpio_random_dout_din.428618148 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 152005015 ps |
| CPU time | 1.07 seconds |
| Started | Jul 11 04:31:16 PM PDT 24 |
| Finished | Jul 11 04:31:35 PM PDT 24 |
| Peak memory | 196356 kb |
| Host | smart-8013cb30-191d-4185-9a5d-c7cae5916a96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=428618148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.428618148 |
| Directory | /workspace/37.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2366214283 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 36835898 ps |
| CPU time | 0.79 seconds |
| Started | Jul 11 04:31:10 PM PDT 24 |
| Finished | Jul 11 04:31:24 PM PDT 24 |
| Peak memory | 196096 kb |
| Host | smart-a0688740-e52a-4f9c-8889-458f940aa832 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366214283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu p_pulldown.2366214283 |
| Directory | /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2108996214 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 602738896 ps |
| CPU time | 1.95 seconds |
| Started | Jul 11 04:32:05 PM PDT 24 |
| Finished | Jul 11 04:32:35 PM PDT 24 |
| Peak memory | 198220 kb |
| Host | smart-d2633767-db5b-48ff-8f5d-5335c8fcbd77 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108996214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra ndom_long_reg_writes_reg_reads.2108996214 |
| Directory | /workspace/37.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/37.gpio_smoke.2895346990 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 96579572 ps |
| CPU time | 1.33 seconds |
| Started | Jul 11 04:31:54 PM PDT 24 |
| Finished | Jul 11 04:32:20 PM PDT 24 |
| Peak memory | 197372 kb |
| Host | smart-7a4e58b4-e923-40b6-9373-2a7b7ed8cc97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2895346990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2895346990 |
| Directory | /workspace/37.gpio_smoke/latest |
| Test location | /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3224516563 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 59481887 ps |
| CPU time | 0.93 seconds |
| Started | Jul 11 04:31:08 PM PDT 24 |
| Finished | Jul 11 04:31:20 PM PDT 24 |
| Peak memory | 196236 kb |
| Host | smart-94417c9a-473f-4be8-a18f-5b96fd823e8b |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224516563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3224516563 |
| Directory | /workspace/37.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/37.gpio_stress_all.4130242355 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 67435164361 ps |
| CPU time | 229.66 seconds |
| Started | Jul 11 04:31:02 PM PDT 24 |
| Finished | Jul 11 04:34:58 PM PDT 24 |
| Peak memory | 198660 kb |
| Host | smart-be136184-31fc-47d3-a945-253213c1abf9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130242355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. gpio_stress_all.4130242355 |
| Directory | /workspace/37.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/38.gpio_alert_test.2485601678 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 13469217 ps |
| CPU time | 0.54 seconds |
| Started | Jul 11 04:32:18 PM PDT 24 |
| Finished | Jul 11 04:32:51 PM PDT 24 |
| Peak memory | 195152 kb |
| Host | smart-b2189320-0657-45cc-984f-a3fc97da4c63 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485601678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2485601678 |
| Directory | /workspace/38.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.249224129 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 25780957 ps |
| CPU time | 0.92 seconds |
| Started | Jul 11 04:31:04 PM PDT 24 |
| Finished | Jul 11 04:31:12 PM PDT 24 |
| Peak memory | 197544 kb |
| Host | smart-ae728ca9-364c-4f98-8a11-ce0b4b1a2ef2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=249224129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.249224129 |
| Directory | /workspace/38.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/38.gpio_filter_stress.1555629485 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 203780107 ps |
| CPU time | 7.09 seconds |
| Started | Jul 11 04:31:13 PM PDT 24 |
| Finished | Jul 11 04:31:37 PM PDT 24 |
| Peak memory | 196812 kb |
| Host | smart-68d9729b-432d-4fc1-a12b-b22db102aadb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555629485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre ss.1555629485 |
| Directory | /workspace/38.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/38.gpio_full_random.660835732 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 368067730 ps |
| CPU time | 1.08 seconds |
| Started | Jul 11 04:31:12 PM PDT 24 |
| Finished | Jul 11 04:31:29 PM PDT 24 |
| Peak memory | 198308 kb |
| Host | smart-aaa69477-a4db-40b3-94c7-171f32d2bd54 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660835732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.660835732 |
| Directory | /workspace/38.gpio_full_random/latest |
| Test location | /workspace/coverage/default/38.gpio_intr_rand_pgm.590851728 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 56393268 ps |
| CPU time | 1.24 seconds |
| Started | Jul 11 04:32:20 PM PDT 24 |
| Finished | Jul 11 04:32:54 PM PDT 24 |
| Peak memory | 197088 kb |
| Host | smart-78788b24-252a-4e08-bb6e-d9375958ffda |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590851728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.590851728 |
| Directory | /workspace/38.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1644117717 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 78514599 ps |
| CPU time | 3.03 seconds |
| Started | Jul 11 04:31:01 PM PDT 24 |
| Finished | Jul 11 04:31:11 PM PDT 24 |
| Peak memory | 198712 kb |
| Host | smart-fb03db66-6553-45bb-b1c1-e8b87cc04aba |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644117717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1644117717 |
| Directory | /workspace/38.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/38.gpio_rand_intr_trigger.133602930 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 627681400 ps |
| CPU time | 2.91 seconds |
| Started | Jul 11 04:32:05 PM PDT 24 |
| Finished | Jul 11 04:32:37 PM PDT 24 |
| Peak memory | 197372 kb |
| Host | smart-24ef62c9-951e-43e1-955e-57dcb78b3363 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133602930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger. 133602930 |
| Directory | /workspace/38.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/38.gpio_random_dout_din.3752878955 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 16241522 ps |
| CPU time | 0.74 seconds |
| Started | Jul 11 04:31:02 PM PDT 24 |
| Finished | Jul 11 04:31:10 PM PDT 24 |
| Peak memory | 196860 kb |
| Host | smart-b26e8a08-fdeb-41e7-a381-902a3445578a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3752878955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3752878955 |
| Directory | /workspace/38.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3366995146 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 34916741 ps |
| CPU time | 0.68 seconds |
| Started | Jul 11 04:31:05 PM PDT 24 |
| Finished | Jul 11 04:31:15 PM PDT 24 |
| Peak memory | 196756 kb |
| Host | smart-6323bd87-82b0-41a1-b560-29312d9e1e14 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366995146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu p_pulldown.3366995146 |
| Directory | /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3508707630 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 306122956 ps |
| CPU time | 4.49 seconds |
| Started | Jul 11 04:31:16 PM PDT 24 |
| Finished | Jul 11 04:31:39 PM PDT 24 |
| Peak memory | 197692 kb |
| Host | smart-ef6832a7-a15a-41d4-8a6a-16c3f2f7de37 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508707630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra ndom_long_reg_writes_reg_reads.3508707630 |
| Directory | /workspace/38.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/38.gpio_smoke.2287504236 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 158306641 ps |
| CPU time | 1.41 seconds |
| Started | Jul 11 04:31:10 PM PDT 24 |
| Finished | Jul 11 04:31:24 PM PDT 24 |
| Peak memory | 198656 kb |
| Host | smart-0a5747df-ee90-479b-b0f5-826a7392372e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2287504236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2287504236 |
| Directory | /workspace/38.gpio_smoke/latest |
| Test location | /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.286520643 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 63714620 ps |
| CPU time | 0.81 seconds |
| Started | Jul 11 04:31:18 PM PDT 24 |
| Finished | Jul 11 04:31:37 PM PDT 24 |
| Peak memory | 195676 kb |
| Host | smart-a88021f3-3f40-4c28-a997-3b348935c754 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286520643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.286520643 |
| Directory | /workspace/38.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/38.gpio_stress_all.741292364 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 12642502774 ps |
| CPU time | 170.58 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:34:17 PM PDT 24 |
| Peak memory | 198600 kb |
| Host | smart-8957b302-c45e-4f95-9d49-231a6d5a61e5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741292364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g pio_stress_all.741292364 |
| Directory | /workspace/38.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1463774840 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 202565311081 ps |
| CPU time | 2280.24 seconds |
| Started | Jul 11 04:31:02 PM PDT 24 |
| Finished | Jul 11 05:09:15 PM PDT 24 |
| Peak memory | 198920 kb |
| Host | smart-663cdab9-ab11-421d-98db-d5056fee6003 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1463774840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.1463774840 |
| Directory | /workspace/38.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.gpio_alert_test.1510944395 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 11915984 ps |
| CPU time | 0.54 seconds |
| Started | Jul 11 04:31:16 PM PDT 24 |
| Finished | Jul 11 04:31:35 PM PDT 24 |
| Peak memory | 194532 kb |
| Host | smart-dc8aaa86-ed1b-443d-9358-241ebdd694a9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510944395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1510944395 |
| Directory | /workspace/39.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3935045182 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 23374394 ps |
| CPU time | 0.76 seconds |
| Started | Jul 11 04:32:20 PM PDT 24 |
| Finished | Jul 11 04:32:53 PM PDT 24 |
| Peak memory | 196368 kb |
| Host | smart-9683c8c6-0e7b-4a8d-833c-101ef9cc4c6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3935045182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3935045182 |
| Directory | /workspace/39.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/39.gpio_filter_stress.2168430411 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1583121178 ps |
| CPU time | 21.36 seconds |
| Started | Jul 11 04:32:27 PM PDT 24 |
| Finished | Jul 11 04:33:20 PM PDT 24 |
| Peak memory | 195796 kb |
| Host | smart-091ab363-7a5f-4fd7-96b0-c7b7c3455efe |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168430411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre ss.2168430411 |
| Directory | /workspace/39.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/39.gpio_full_random.964014528 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 47231569 ps |
| CPU time | 0.68 seconds |
| Started | Jul 11 04:32:22 PM PDT 24 |
| Finished | Jul 11 04:32:55 PM PDT 24 |
| Peak memory | 194940 kb |
| Host | smart-50104574-2f15-4f67-9e71-9c878f5c72c4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964014528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.964014528 |
| Directory | /workspace/39.gpio_full_random/latest |
| Test location | /workspace/coverage/default/39.gpio_intr_rand_pgm.3423484995 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 35945997 ps |
| CPU time | 0.8 seconds |
| Started | Jul 11 04:32:21 PM PDT 24 |
| Finished | Jul 11 04:32:53 PM PDT 24 |
| Peak memory | 196396 kb |
| Host | smart-f16adf4e-aafc-4c96-a32c-b541206198e9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423484995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3423484995 |
| Directory | /workspace/39.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.47171476 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 312499884 ps |
| CPU time | 2.53 seconds |
| Started | Jul 11 04:32:18 PM PDT 24 |
| Finished | Jul 11 04:32:53 PM PDT 24 |
| Peak memory | 198352 kb |
| Host | smart-30d0d379-d278-46b0-ab70-e014eb5d2add |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47171476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 39.gpio_intr_with_filter_rand_intr_event.47171476 |
| Directory | /workspace/39.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/39.gpio_rand_intr_trigger.921660312 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 62223794 ps |
| CPU time | 1.31 seconds |
| Started | Jul 11 04:31:10 PM PDT 24 |
| Finished | Jul 11 04:31:25 PM PDT 24 |
| Peak memory | 196612 kb |
| Host | smart-a2c34b09-e900-410f-a135-eaec2fc139e6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921660312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger. 921660312 |
| Directory | /workspace/39.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/39.gpio_random_dout_din.22886024 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 48726253 ps |
| CPU time | 0.64 seconds |
| Started | Jul 11 04:31:10 PM PDT 24 |
| Finished | Jul 11 04:31:24 PM PDT 24 |
| Peak memory | 194852 kb |
| Host | smart-d504f595-49c0-455c-9bb6-d545630f5e4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=22886024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.22886024 |
| Directory | /workspace/39.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2856144318 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 38169860 ps |
| CPU time | 0.74 seconds |
| Started | Jul 11 04:31:13 PM PDT 24 |
| Finished | Jul 11 04:31:30 PM PDT 24 |
| Peak memory | 195952 kb |
| Host | smart-8edc289e-52fe-4ff1-b2e2-95bb9f6703dc |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856144318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu p_pulldown.2856144318 |
| Directory | /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3441755044 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 445351928 ps |
| CPU time | 3.81 seconds |
| Started | Jul 11 04:31:12 PM PDT 24 |
| Finished | Jul 11 04:31:31 PM PDT 24 |
| Peak memory | 198492 kb |
| Host | smart-6e5488e3-6c81-425d-b4df-34ced9cf8dc1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441755044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra ndom_long_reg_writes_reg_reads.3441755044 |
| Directory | /workspace/39.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/39.gpio_smoke.3244734335 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 80985201 ps |
| CPU time | 1.26 seconds |
| Started | Jul 11 04:32:22 PM PDT 24 |
| Finished | Jul 11 04:32:56 PM PDT 24 |
| Peak memory | 195828 kb |
| Host | smart-a7da46bb-2107-4268-8744-1264c0f6d7e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244734335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.3244734335 |
| Directory | /workspace/39.gpio_smoke/latest |
| Test location | /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3984646931 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 39459374 ps |
| CPU time | 1 seconds |
| Started | Jul 11 04:31:12 PM PDT 24 |
| Finished | Jul 11 04:31:29 PM PDT 24 |
| Peak memory | 196116 kb |
| Host | smart-12f03424-347b-4109-8562-d50864a29e9a |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984646931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3984646931 |
| Directory | /workspace/39.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/39.gpio_stress_all.728604988 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 8121866994 ps |
| CPU time | 102.49 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:33:08 PM PDT 24 |
| Peak memory | 198688 kb |
| Host | smart-1fb16cb8-7053-4190-919f-60164d78524d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728604988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g pio_stress_all.728604988 |
| Directory | /workspace/39.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/4.gpio_alert_test.2591762051 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 38020954 ps |
| CPU time | 0.54 seconds |
| Started | Jul 11 04:29:51 PM PDT 24 |
| Finished | Jul 11 04:29:54 PM PDT 24 |
| Peak memory | 194476 kb |
| Host | smart-af161a81-6d2f-4d8e-a3a1-93aefb234391 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591762051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2591762051 |
| Directory | /workspace/4.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3617584537 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 127856870 ps |
| CPU time | 0.82 seconds |
| Started | Jul 11 04:30:03 PM PDT 24 |
| Finished | Jul 11 04:30:13 PM PDT 24 |
| Peak memory | 195680 kb |
| Host | smart-4403f042-2c25-4aea-8b56-75f1caa407c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3617584537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3617584537 |
| Directory | /workspace/4.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/4.gpio_filter_stress.1387109003 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 821478312 ps |
| CPU time | 21.17 seconds |
| Started | Jul 11 04:29:52 PM PDT 24 |
| Finished | Jul 11 04:30:16 PM PDT 24 |
| Peak memory | 197280 kb |
| Host | smart-f27933fb-ba58-459e-a4a5-059bf6d92bc6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387109003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres s.1387109003 |
| Directory | /workspace/4.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/4.gpio_full_random.1770552626 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 380715584 ps |
| CPU time | 0.92 seconds |
| Started | Jul 11 04:29:53 PM PDT 24 |
| Finished | Jul 11 04:29:58 PM PDT 24 |
| Peak memory | 196656 kb |
| Host | smart-c641d136-f1a7-49eb-852d-927aeed798d9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770552626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1770552626 |
| Directory | /workspace/4.gpio_full_random/latest |
| Test location | /workspace/coverage/default/4.gpio_intr_rand_pgm.1857988931 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 153594765 ps |
| CPU time | 1.18 seconds |
| Started | Jul 11 04:29:56 PM PDT 24 |
| Finished | Jul 11 04:30:02 PM PDT 24 |
| Peak memory | 197304 kb |
| Host | smart-3beed782-5390-46ea-8aaa-49a369ff794f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857988931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1857988931 |
| Directory | /workspace/4.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1612295995 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 50024861 ps |
| CPU time | 1.88 seconds |
| Started | Jul 11 04:29:49 PM PDT 24 |
| Finished | Jul 11 04:29:53 PM PDT 24 |
| Peak memory | 198604 kb |
| Host | smart-42226e7e-8151-497a-9cdb-93006f71da2d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612295995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1612295995 |
| Directory | /workspace/4.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/4.gpio_rand_intr_trigger.2811223050 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 141177826 ps |
| CPU time | 2.07 seconds |
| Started | Jul 11 04:29:55 PM PDT 24 |
| Finished | Jul 11 04:30:02 PM PDT 24 |
| Peak memory | 196380 kb |
| Host | smart-a8d24f7f-5fbe-40fb-93fd-a2c9f6861a73 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811223050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger. 2811223050 |
| Directory | /workspace/4.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/4.gpio_random_dout_din.643075014 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 230381031 ps |
| CPU time | 1.12 seconds |
| Started | Jul 11 04:29:45 PM PDT 24 |
| Finished | Jul 11 04:29:48 PM PDT 24 |
| Peak memory | 196568 kb |
| Host | smart-5a362441-09d3-40eb-a7c3-07659c55fbad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=643075014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.643075014 |
| Directory | /workspace/4.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1495530717 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 98462998 ps |
| CPU time | 1.09 seconds |
| Started | Jul 11 04:29:59 PM PDT 24 |
| Finished | Jul 11 04:30:09 PM PDT 24 |
| Peak memory | 197108 kb |
| Host | smart-ede1b8ea-baa3-4dbf-86b8-4bc0bb9c9030 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495530717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup _pulldown.1495530717 |
| Directory | /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1872333058 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 80433857 ps |
| CPU time | 2.13 seconds |
| Started | Jul 11 04:29:51 PM PDT 24 |
| Finished | Jul 11 04:29:56 PM PDT 24 |
| Peak memory | 198492 kb |
| Host | smart-98a0c550-dd99-486b-8b8d-da863f51d7b1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872333058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran dom_long_reg_writes_reg_reads.1872333058 |
| Directory | /workspace/4.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/4.gpio_sec_cm.1227461706 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 89646960 ps |
| CPU time | 0.89 seconds |
| Started | Jul 11 04:29:55 PM PDT 24 |
| Finished | Jul 11 04:30:00 PM PDT 24 |
| Peak memory | 214120 kb |
| Host | smart-27cd4fe5-353c-4c76-b3b6-f95a24e0c5b9 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227461706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1227461706 |
| Directory | /workspace/4.gpio_sec_cm/latest |
| Test location | /workspace/coverage/default/4.gpio_smoke.2946045071 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 43475248 ps |
| CPU time | 0.72 seconds |
| Started | Jul 11 04:29:50 PM PDT 24 |
| Finished | Jul 11 04:29:53 PM PDT 24 |
| Peak memory | 194712 kb |
| Host | smart-f5ca5a91-cd90-48af-a0fc-feb606c30c82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2946045071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2946045071 |
| Directory | /workspace/4.gpio_smoke/latest |
| Test location | /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.13847112 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 146226450 ps |
| CPU time | 0.89 seconds |
| Started | Jul 11 04:29:52 PM PDT 24 |
| Finished | Jul 11 04:29:57 PM PDT 24 |
| Peak memory | 195728 kb |
| Host | smart-905deb76-4dfa-444b-a8e8-a8df319d8786 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13847112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.13847112 |
| Directory | /workspace/4.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/4.gpio_stress_all.1688198957 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 21145130136 ps |
| CPU time | 211.63 seconds |
| Started | Jul 11 04:29:58 PM PDT 24 |
| Finished | Jul 11 04:33:37 PM PDT 24 |
| Peak memory | 198640 kb |
| Host | smart-92e19cb3-3640-4429-973c-ec953ec4d9a8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688198957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g pio_stress_all.1688198957 |
| Directory | /workspace/4.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.2933865822 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 70379178040 ps |
| CPU time | 582.07 seconds |
| Started | Jul 11 04:29:57 PM PDT 24 |
| Finished | Jul 11 04:39:45 PM PDT 24 |
| Peak memory | 198792 kb |
| Host | smart-b932630a-8b0b-432f-809d-86ce492a8864 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2933865822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.2933865822 |
| Directory | /workspace/4.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.gpio_alert_test.451726895 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 14948440 ps |
| CPU time | 0.55 seconds |
| Started | Jul 11 04:32:15 PM PDT 24 |
| Finished | Jul 11 04:32:49 PM PDT 24 |
| Peak memory | 194936 kb |
| Host | smart-6d8b4447-e528-46c1-81be-5e6430611b31 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451726895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.451726895 |
| Directory | /workspace/40.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.102023563 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 179463449 ps |
| CPU time | 0.88 seconds |
| Started | Jul 11 04:31:09 PM PDT 24 |
| Finished | Jul 11 04:31:22 PM PDT 24 |
| Peak memory | 196480 kb |
| Host | smart-9180d440-a65e-41f1-8204-52c8a099babf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102023563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.102023563 |
| Directory | /workspace/40.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/40.gpio_filter_stress.3014742550 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 642689978 ps |
| CPU time | 8.6 seconds |
| Started | Jul 11 04:31:14 PM PDT 24 |
| Finished | Jul 11 04:31:40 PM PDT 24 |
| Peak memory | 197488 kb |
| Host | smart-4fb06976-0bf4-42c2-8489-6f5dc796d456 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014742550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre ss.3014742550 |
| Directory | /workspace/40.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/40.gpio_full_random.3353798813 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 69471595 ps |
| CPU time | 0.88 seconds |
| Started | Jul 11 04:32:15 PM PDT 24 |
| Finished | Jul 11 04:32:49 PM PDT 24 |
| Peak memory | 198108 kb |
| Host | smart-3c673c86-b40f-4a0d-a284-e33cf498fb31 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353798813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3353798813 |
| Directory | /workspace/40.gpio_full_random/latest |
| Test location | /workspace/coverage/default/40.gpio_intr_rand_pgm.2900392113 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 41090580 ps |
| CPU time | 0.74 seconds |
| Started | Jul 11 04:31:13 PM PDT 24 |
| Finished | Jul 11 04:31:30 PM PDT 24 |
| Peak memory | 195952 kb |
| Host | smart-ff5605bb-a0d3-4dbf-9527-da8d57491469 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900392113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2900392113 |
| Directory | /workspace/40.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.419479830 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 148702405 ps |
| CPU time | 2.94 seconds |
| Started | Jul 11 04:31:05 PM PDT 24 |
| Finished | Jul 11 04:31:17 PM PDT 24 |
| Peak memory | 198668 kb |
| Host | smart-e56defd2-ebe2-45ba-80ff-b2c467d4723b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419479830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 40.gpio_intr_with_filter_rand_intr_event.419479830 |
| Directory | /workspace/40.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/40.gpio_rand_intr_trigger.2447819684 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 118561855 ps |
| CPU time | 1.07 seconds |
| Started | Jul 11 04:31:13 PM PDT 24 |
| Finished | Jul 11 04:31:37 PM PDT 24 |
| Peak memory | 196264 kb |
| Host | smart-32e891cc-58fe-49bc-9f76-f33caeca01fb |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447819684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger .2447819684 |
| Directory | /workspace/40.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/40.gpio_random_dout_din.1225421322 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 281340330 ps |
| CPU time | 1.01 seconds |
| Started | Jul 11 04:31:09 PM PDT 24 |
| Finished | Jul 11 04:31:23 PM PDT 24 |
| Peak memory | 196424 kb |
| Host | smart-765c5894-e3cc-4959-96fd-05f314845bba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1225421322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1225421322 |
| Directory | /workspace/40.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3014316607 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 198505456 ps |
| CPU time | 1.07 seconds |
| Started | Jul 11 04:31:04 PM PDT 24 |
| Finished | Jul 11 04:31:12 PM PDT 24 |
| Peak memory | 196440 kb |
| Host | smart-fca93b47-ea2a-4bfa-b32d-abe1698426f3 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014316607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu p_pulldown.3014316607 |
| Directory | /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3780184981 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 881803327 ps |
| CPU time | 4.95 seconds |
| Started | Jul 11 04:32:15 PM PDT 24 |
| Finished | Jul 11 04:32:53 PM PDT 24 |
| Peak memory | 198228 kb |
| Host | smart-22a057b3-e5b5-48f4-b09d-7dad7950419b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780184981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra ndom_long_reg_writes_reg_reads.3780184981 |
| Directory | /workspace/40.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/40.gpio_smoke.1888559550 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 74709655 ps |
| CPU time | 1.1 seconds |
| Started | Jul 11 04:32:14 PM PDT 24 |
| Finished | Jul 11 04:32:45 PM PDT 24 |
| Peak memory | 196088 kb |
| Host | smart-cf515315-4320-436f-9c04-2d05181492d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1888559550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1888559550 |
| Directory | /workspace/40.gpio_smoke/latest |
| Test location | /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2819141991 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 29954049 ps |
| CPU time | 0.89 seconds |
| Started | Jul 11 04:32:06 PM PDT 24 |
| Finished | Jul 11 04:32:34 PM PDT 24 |
| Peak memory | 196152 kb |
| Host | smart-96463a3f-2d1f-4c16-841a-fc830c166a1e |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819141991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2819141991 |
| Directory | /workspace/40.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/40.gpio_stress_all.24959978 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 8429299848 ps |
| CPU time | 190.63 seconds |
| Started | Jul 11 04:32:15 PM PDT 24 |
| Finished | Jul 11 04:35:59 PM PDT 24 |
| Peak memory | 198396 kb |
| Host | smart-dd933cea-2c51-4d37-a4e2-6928c85225de |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24959978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gp io_stress_all.24959978 |
| Directory | /workspace/40.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.3177560958 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 194179364649 ps |
| CPU time | 1833.67 seconds |
| Started | Jul 11 04:32:15 PM PDT 24 |
| Finished | Jul 11 05:03:21 PM PDT 24 |
| Peak memory | 198524 kb |
| Host | smart-fb658515-9ab9-4740-8516-7b5b4bd3a8a7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3177560958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.3177560958 |
| Directory | /workspace/40.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.gpio_alert_test.2286519075 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 18817178 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:31:12 PM PDT 24 |
| Finished | Jul 11 04:31:29 PM PDT 24 |
| Peak memory | 194736 kb |
| Host | smart-dd3f92f3-19fd-47ed-b364-1cfea655c01d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286519075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2286519075 |
| Directory | /workspace/41.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.4291253561 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 34867296 ps |
| CPU time | 0.84 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:31:26 PM PDT 24 |
| Peak memory | 196036 kb |
| Host | smart-6e8c4560-c328-45ab-8ce1-dd8fe68fe801 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4291253561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.4291253561 |
| Directory | /workspace/41.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/41.gpio_filter_stress.500109861 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 637416971 ps |
| CPU time | 15.88 seconds |
| Started | Jul 11 04:31:35 PM PDT 24 |
| Finished | Jul 11 04:32:09 PM PDT 24 |
| Peak memory | 197352 kb |
| Host | smart-025ec341-90a7-49e6-af1c-59cd0c17b9a8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500109861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres s.500109861 |
| Directory | /workspace/41.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/41.gpio_full_random.893959515 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 158879605 ps |
| CPU time | 0.85 seconds |
| Started | Jul 11 04:31:16 PM PDT 24 |
| Finished | Jul 11 04:31:34 PM PDT 24 |
| Peak memory | 197404 kb |
| Host | smart-eb421c7c-75b5-49d8-987a-cd1081a87b43 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893959515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.893959515 |
| Directory | /workspace/41.gpio_full_random/latest |
| Test location | /workspace/coverage/default/41.gpio_intr_rand_pgm.3834527354 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 37063605 ps |
| CPU time | 0.83 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:31:27 PM PDT 24 |
| Peak memory | 196084 kb |
| Host | smart-acbb105a-efa9-472c-be88-3a78ea4da3a4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834527354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3834527354 |
| Directory | /workspace/41.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.272616201 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 85123913 ps |
| CPU time | 1.69 seconds |
| Started | Jul 11 04:31:14 PM PDT 24 |
| Finished | Jul 11 04:31:33 PM PDT 24 |
| Peak memory | 197760 kb |
| Host | smart-022cfca3-3548-49b1-a79f-4578cafef223 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272616201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 41.gpio_intr_with_filter_rand_intr_event.272616201 |
| Directory | /workspace/41.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/41.gpio_rand_intr_trigger.1372922509 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 300223147 ps |
| CPU time | 2.88 seconds |
| Started | Jul 11 04:31:19 PM PDT 24 |
| Finished | Jul 11 04:31:41 PM PDT 24 |
| Peak memory | 198572 kb |
| Host | smart-43987e8d-e7e6-407c-9e8d-eb680607d07b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372922509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger .1372922509 |
| Directory | /workspace/41.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/41.gpio_random_dout_din.1204532113 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 64341679 ps |
| CPU time | 1.17 seconds |
| Started | Jul 11 04:31:13 PM PDT 24 |
| Finished | Jul 11 04:31:31 PM PDT 24 |
| Peak memory | 198684 kb |
| Host | smart-5ae26623-f9e8-4298-a432-3799939d98c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1204532113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1204532113 |
| Directory | /workspace/41.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1766207073 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 365695868 ps |
| CPU time | 0.81 seconds |
| Started | Jul 11 04:31:05 PM PDT 24 |
| Finished | Jul 11 04:31:16 PM PDT 24 |
| Peak memory | 196500 kb |
| Host | smart-d7242a63-3be2-4a92-bfe5-08f47a07c87e |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766207073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu p_pulldown.1766207073 |
| Directory | /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2468217873 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 532668670 ps |
| CPU time | 3.92 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:31:30 PM PDT 24 |
| Peak memory | 198496 kb |
| Host | smart-68e69a00-bb68-46fb-97fb-c27feaf8afe8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468217873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra ndom_long_reg_writes_reg_reads.2468217873 |
| Directory | /workspace/41.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/41.gpio_smoke.2442410494 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 40053988 ps |
| CPU time | 0.83 seconds |
| Started | Jul 11 04:31:12 PM PDT 24 |
| Finished | Jul 11 04:31:29 PM PDT 24 |
| Peak memory | 196532 kb |
| Host | smart-076f89a3-8d90-4319-90a3-d61e2f8d98cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2442410494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2442410494 |
| Directory | /workspace/41.gpio_smoke/latest |
| Test location | /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1010469265 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 270623833 ps |
| CPU time | 1.48 seconds |
| Started | Jul 11 04:31:09 PM PDT 24 |
| Finished | Jul 11 04:31:23 PM PDT 24 |
| Peak memory | 198676 kb |
| Host | smart-8ca11dab-6a98-4fba-835c-a72e944320e5 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010469265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1010469265 |
| Directory | /workspace/41.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/41.gpio_stress_all.3928980927 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 3295022903 ps |
| CPU time | 42.34 seconds |
| Started | Jul 11 04:31:32 PM PDT 24 |
| Finished | Jul 11 04:32:33 PM PDT 24 |
| Peak memory | 198684 kb |
| Host | smart-7b217516-4200-4a77-b6a9-9486d7ecc387 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928980927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41. gpio_stress_all.3928980927 |
| Directory | /workspace/41.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.2470755287 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 353417516795 ps |
| CPU time | 294.54 seconds |
| Started | Jul 11 04:31:27 PM PDT 24 |
| Finished | Jul 11 04:36:40 PM PDT 24 |
| Peak memory | 207124 kb |
| Host | smart-448cd9b8-bf47-4721-9ef0-7ddf9827f8af |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2470755287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.2470755287 |
| Directory | /workspace/41.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.gpio_alert_test.216965915 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 42894105 ps |
| CPU time | 0.6 seconds |
| Started | Jul 11 04:31:52 PM PDT 24 |
| Finished | Jul 11 04:32:16 PM PDT 24 |
| Peak memory | 194540 kb |
| Host | smart-0ebf7b05-379e-4f78-96f5-699a2c1921cd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216965915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.216965915 |
| Directory | /workspace/42.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3749156236 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 456638591 ps |
| CPU time | 0.76 seconds |
| Started | Jul 11 04:31:28 PM PDT 24 |
| Finished | Jul 11 04:31:48 PM PDT 24 |
| Peak memory | 195796 kb |
| Host | smart-02d010a1-fd05-4d24-8fe4-79714b1d1ffb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3749156236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3749156236 |
| Directory | /workspace/42.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/42.gpio_filter_stress.1685456052 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1255110401 ps |
| CPU time | 15.98 seconds |
| Started | Jul 11 04:31:44 PM PDT 24 |
| Finished | Jul 11 04:32:20 PM PDT 24 |
| Peak memory | 197620 kb |
| Host | smart-1c34645f-d787-40d5-b414-43f16896457c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685456052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre ss.1685456052 |
| Directory | /workspace/42.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/42.gpio_full_random.3119453763 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 71899174 ps |
| CPU time | 0.82 seconds |
| Started | Jul 11 04:31:16 PM PDT 24 |
| Finished | Jul 11 04:31:35 PM PDT 24 |
| Peak memory | 197408 kb |
| Host | smart-39e35209-88d9-4693-9ce9-6224892eed90 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119453763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3119453763 |
| Directory | /workspace/42.gpio_full_random/latest |
| Test location | /workspace/coverage/default/42.gpio_intr_rand_pgm.1817136496 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 150021699 ps |
| CPU time | 0.92 seconds |
| Started | Jul 11 04:31:24 PM PDT 24 |
| Finished | Jul 11 04:31:44 PM PDT 24 |
| Peak memory | 196496 kb |
| Host | smart-5a62b98d-afc7-40fe-bbb4-41005efb4405 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817136496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1817136496 |
| Directory | /workspace/42.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2773163691 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 546379929 ps |
| CPU time | 1.21 seconds |
| Started | Jul 11 04:31:19 PM PDT 24 |
| Finished | Jul 11 04:31:39 PM PDT 24 |
| Peak memory | 197520 kb |
| Host | smart-b4aadf01-4471-41bd-a9ea-5186a7f81686 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773163691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2773163691 |
| Directory | /workspace/42.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/42.gpio_rand_intr_trigger.2065261159 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 502804059 ps |
| CPU time | 1.98 seconds |
| Started | Jul 11 04:31:16 PM PDT 24 |
| Finished | Jul 11 04:31:37 PM PDT 24 |
| Peak memory | 198572 kb |
| Host | smart-1017e879-8791-4bfb-bb43-69fae55df5fa |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065261159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger .2065261159 |
| Directory | /workspace/42.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/42.gpio_random_dout_din.2237673261 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 71401493 ps |
| CPU time | 0.66 seconds |
| Started | Jul 11 04:31:10 PM PDT 24 |
| Finished | Jul 11 04:31:26 PM PDT 24 |
| Peak memory | 195536 kb |
| Host | smart-c76da08d-9658-473c-9c74-927c33fa9f4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2237673261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2237673261 |
| Directory | /workspace/42.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.4187850863 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 103374720 ps |
| CPU time | 0.8 seconds |
| Started | Jul 11 04:31:12 PM PDT 24 |
| Finished | Jul 11 04:31:30 PM PDT 24 |
| Peak memory | 195988 kb |
| Host | smart-3643e699-25b9-4d13-b2b4-ae29f23d2948 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187850863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu p_pulldown.4187850863 |
| Directory | /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1329044662 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 1838228194 ps |
| CPU time | 5.22 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:31:30 PM PDT 24 |
| Peak memory | 198596 kb |
| Host | smart-ebb736ba-3f3e-49de-9a0b-6f56a3d791b1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329044662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra ndom_long_reg_writes_reg_reads.1329044662 |
| Directory | /workspace/42.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/42.gpio_smoke.1576966312 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 93079363 ps |
| CPU time | 1.19 seconds |
| Started | Jul 11 04:31:18 PM PDT 24 |
| Finished | Jul 11 04:31:38 PM PDT 24 |
| Peak memory | 196308 kb |
| Host | smart-81e2060b-e0b0-47c9-b818-87eb863422f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1576966312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1576966312 |
| Directory | /workspace/42.gpio_smoke/latest |
| Test location | /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.409311766 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 226918311 ps |
| CPU time | 0.98 seconds |
| Started | Jul 11 04:31:17 PM PDT 24 |
| Finished | Jul 11 04:31:36 PM PDT 24 |
| Peak memory | 197328 kb |
| Host | smart-77937a33-3f13-4cf3-8e69-d3ab46ec388e |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409311766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.409311766 |
| Directory | /workspace/42.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/42.gpio_stress_all.1514609897 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 4309335617 ps |
| CPU time | 65.53 seconds |
| Started | Jul 11 04:31:39 PM PDT 24 |
| Finished | Jul 11 04:33:02 PM PDT 24 |
| Peak memory | 198676 kb |
| Host | smart-7b385c08-0e6b-4305-8b53-e571e5e52fdd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514609897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. gpio_stress_all.1514609897 |
| Directory | /workspace/42.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/43.gpio_alert_test.3744526552 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 14518084 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:31:27 PM PDT 24 |
| Peak memory | 195196 kb |
| Host | smart-256fb207-5044-4cc7-b710-4908c0310612 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744526552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3744526552 |
| Directory | /workspace/43.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3060146752 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 38405690 ps |
| CPU time | 0.78 seconds |
| Started | Jul 11 04:31:29 PM PDT 24 |
| Finished | Jul 11 04:31:49 PM PDT 24 |
| Peak memory | 196668 kb |
| Host | smart-31fcaafc-95f9-4cc7-91ea-93cdd74549bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3060146752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3060146752 |
| Directory | /workspace/43.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/43.gpio_filter_stress.3774719996 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 203502171 ps |
| CPU time | 6.7 seconds |
| Started | Jul 11 04:31:22 PM PDT 24 |
| Finished | Jul 11 04:31:49 PM PDT 24 |
| Peak memory | 198520 kb |
| Host | smart-24c5b3e3-ed65-4527-9178-d335f7706df9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774719996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre ss.3774719996 |
| Directory | /workspace/43.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/43.gpio_full_random.2880919612 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 33755619 ps |
| CPU time | 0.73 seconds |
| Started | Jul 11 04:31:15 PM PDT 24 |
| Finished | Jul 11 04:31:32 PM PDT 24 |
| Peak memory | 196544 kb |
| Host | smart-349f4fa8-628a-422f-8fb8-5e48fc11de35 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880919612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2880919612 |
| Directory | /workspace/43.gpio_full_random/latest |
| Test location | /workspace/coverage/default/43.gpio_intr_rand_pgm.2371122739 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 224837026 ps |
| CPU time | 0.98 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:31:27 PM PDT 24 |
| Peak memory | 196312 kb |
| Host | smart-05d9f8ee-96d5-4d32-8d87-bd4150b9d596 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371122739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2371122739 |
| Directory | /workspace/43.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2924657865 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 139545718 ps |
| CPU time | 3.52 seconds |
| Started | Jul 11 04:31:35 PM PDT 24 |
| Finished | Jul 11 04:31:56 PM PDT 24 |
| Peak memory | 198464 kb |
| Host | smart-cf35c2c2-2a27-4c24-8158-7d94dd86b2d0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924657865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2924657865 |
| Directory | /workspace/43.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/43.gpio_rand_intr_trigger.863914431 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 157504027 ps |
| CPU time | 1.02 seconds |
| Started | Jul 11 04:31:10 PM PDT 24 |
| Finished | Jul 11 04:31:26 PM PDT 24 |
| Peak memory | 196148 kb |
| Host | smart-4c98f761-3acb-4f59-ad06-41a3696e03a9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863914431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger. 863914431 |
| Directory | /workspace/43.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/43.gpio_random_dout_din.2851260317 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 32259511 ps |
| CPU time | 1.15 seconds |
| Started | Jul 11 04:31:10 PM PDT 24 |
| Finished | Jul 11 04:31:25 PM PDT 24 |
| Peak memory | 197204 kb |
| Host | smart-1b7a8706-2ec0-4e11-8f98-90682a9f6069 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2851260317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2851260317 |
| Directory | /workspace/43.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1635999226 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 50864449 ps |
| CPU time | 0.64 seconds |
| Started | Jul 11 04:31:21 PM PDT 24 |
| Finished | Jul 11 04:31:41 PM PDT 24 |
| Peak memory | 195088 kb |
| Host | smart-999843bf-ef81-43f7-9bdd-b95fcb7cdc56 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635999226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu p_pulldown.1635999226 |
| Directory | /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3393184201 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 50692157 ps |
| CPU time | 2.31 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:31:29 PM PDT 24 |
| Peak memory | 198580 kb |
| Host | smart-7d491eae-3ccb-4b4a-903f-5222014d19d4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393184201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra ndom_long_reg_writes_reg_reads.3393184201 |
| Directory | /workspace/43.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/43.gpio_smoke.1392194742 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 352014220 ps |
| CPU time | 1.42 seconds |
| Started | Jul 11 04:31:18 PM PDT 24 |
| Finished | Jul 11 04:31:38 PM PDT 24 |
| Peak memory | 196152 kb |
| Host | smart-57a8eb4f-48be-49bb-b227-a334bead83f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1392194742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1392194742 |
| Directory | /workspace/43.gpio_smoke/latest |
| Test location | /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1215566083 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 147450540 ps |
| CPU time | 0.84 seconds |
| Started | Jul 11 04:31:13 PM PDT 24 |
| Finished | Jul 11 04:31:31 PM PDT 24 |
| Peak memory | 195908 kb |
| Host | smart-c1865ea1-a127-4048-8d03-ff79fa10d907 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215566083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1215566083 |
| Directory | /workspace/43.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/43.gpio_stress_all.715397353 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 12231709029 ps |
| CPU time | 79.31 seconds |
| Started | Jul 11 04:31:29 PM PDT 24 |
| Finished | Jul 11 04:33:07 PM PDT 24 |
| Peak memory | 198608 kb |
| Host | smart-420ccae5-6cb4-460e-85d4-2358a9740f81 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715397353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g pio_stress_all.715397353 |
| Directory | /workspace/43.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.2572829424 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 68097639328 ps |
| CPU time | 1347.71 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:53:54 PM PDT 24 |
| Peak memory | 198764 kb |
| Host | smart-b9d987d4-08f8-4b89-9416-bd21bf654e2c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2572829424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.2572829424 |
| Directory | /workspace/43.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.gpio_alert_test.1925145617 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 25741312 ps |
| CPU time | 0.61 seconds |
| Started | Jul 11 04:31:17 PM PDT 24 |
| Finished | Jul 11 04:31:37 PM PDT 24 |
| Peak memory | 195060 kb |
| Host | smart-d22f2db7-4e67-4a67-85fc-d86ff0f44693 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925145617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1925145617 |
| Directory | /workspace/44.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1869535073 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 67191191 ps |
| CPU time | 0.68 seconds |
| Started | Jul 11 04:31:14 PM PDT 24 |
| Finished | Jul 11 04:31:32 PM PDT 24 |
| Peak memory | 194600 kb |
| Host | smart-d0caff92-0144-4656-8a1c-111010694cff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1869535073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1869535073 |
| Directory | /workspace/44.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/44.gpio_filter_stress.2509316442 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 5832171159 ps |
| CPU time | 21.18 seconds |
| Started | Jul 11 04:31:41 PM PDT 24 |
| Finished | Jul 11 04:32:22 PM PDT 24 |
| Peak memory | 198588 kb |
| Host | smart-68c3023e-4090-43ab-aa28-3e3249ca71e7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509316442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre ss.2509316442 |
| Directory | /workspace/44.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/44.gpio_full_random.2540377280 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 20218979 ps |
| CPU time | 0.63 seconds |
| Started | Jul 11 04:31:17 PM PDT 24 |
| Finished | Jul 11 04:31:36 PM PDT 24 |
| Peak memory | 195800 kb |
| Host | smart-277e1b9c-644b-437d-804f-6ba81960a527 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540377280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2540377280 |
| Directory | /workspace/44.gpio_full_random/latest |
| Test location | /workspace/coverage/default/44.gpio_intr_rand_pgm.908131631 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 21808953 ps |
| CPU time | 0.75 seconds |
| Started | Jul 11 04:31:32 PM PDT 24 |
| Finished | Jul 11 04:31:51 PM PDT 24 |
| Peak memory | 196064 kb |
| Host | smart-5c2e596e-c022-400c-926c-a5f538b6f2eb |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908131631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.908131631 |
| Directory | /workspace/44.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.4121402211 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 70997174 ps |
| CPU time | 2.54 seconds |
| Started | Jul 11 04:31:13 PM PDT 24 |
| Finished | Jul 11 04:31:32 PM PDT 24 |
| Peak memory | 198540 kb |
| Host | smart-4e0762a7-c3e3-4ed1-a2e6-6b86459008a2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121402211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 44.gpio_intr_with_filter_rand_intr_event.4121402211 |
| Directory | /workspace/44.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/44.gpio_rand_intr_trigger.2173600103 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 303025773 ps |
| CPU time | 1.74 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:31:36 PM PDT 24 |
| Peak memory | 196408 kb |
| Host | smart-175f5c5b-45ba-42ae-b8fc-2ce9048db0a0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173600103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger .2173600103 |
| Directory | /workspace/44.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/44.gpio_random_dout_din.3852958487 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 93615069 ps |
| CPU time | 0.7 seconds |
| Started | Jul 11 04:31:15 PM PDT 24 |
| Finished | Jul 11 04:31:34 PM PDT 24 |
| Peak memory | 195860 kb |
| Host | smart-ada5b259-ee45-4643-8d71-960e96705bec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3852958487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3852958487 |
| Directory | /workspace/44.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3446865025 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 49295343 ps |
| CPU time | 1.11 seconds |
| Started | Jul 11 04:31:27 PM PDT 24 |
| Finished | Jul 11 04:31:47 PM PDT 24 |
| Peak memory | 197216 kb |
| Host | smart-b562ae45-a084-4d71-8f23-027f57083f56 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446865025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu p_pulldown.3446865025 |
| Directory | /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1344926329 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 2108376074 ps |
| CPU time | 4.68 seconds |
| Started | Jul 11 04:31:24 PM PDT 24 |
| Finished | Jul 11 04:31:48 PM PDT 24 |
| Peak memory | 198564 kb |
| Host | smart-7630e2bb-5e8f-45b0-8ed7-4020406bfd1d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344926329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra ndom_long_reg_writes_reg_reads.1344926329 |
| Directory | /workspace/44.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/44.gpio_smoke.2189081825 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 138956991 ps |
| CPU time | 0.92 seconds |
| Started | Jul 11 04:31:11 PM PDT 24 |
| Finished | Jul 11 04:31:27 PM PDT 24 |
| Peak memory | 196828 kb |
| Host | smart-17c8ade7-1c21-476d-92d6-fa9c7c897558 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2189081825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2189081825 |
| Directory | /workspace/44.gpio_smoke/latest |
| Test location | /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3212665467 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 298678399 ps |
| CPU time | 1.39 seconds |
| Started | Jul 11 04:31:10 PM PDT 24 |
| Finished | Jul 11 04:31:25 PM PDT 24 |
| Peak memory | 197384 kb |
| Host | smart-1ae58426-8c4c-4682-bb30-a14f4a8fa7f3 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212665467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3212665467 |
| Directory | /workspace/44.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/44.gpio_stress_all.3193765838 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 2402958317 ps |
| CPU time | 55.59 seconds |
| Started | Jul 11 04:31:35 PM PDT 24 |
| Finished | Jul 11 04:32:49 PM PDT 24 |
| Peak memory | 198564 kb |
| Host | smart-81b958d0-96c3-4652-ae7f-02a0377d639d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193765838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. gpio_stress_all.3193765838 |
| Directory | /workspace/44.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/45.gpio_alert_test.1367691155 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 21192136 ps |
| CPU time | 0.56 seconds |
| Started | Jul 11 04:31:35 PM PDT 24 |
| Finished | Jul 11 04:31:54 PM PDT 24 |
| Peak memory | 194512 kb |
| Host | smart-e8f0d77b-0b0c-4296-b8e6-c7f70ce7919e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367691155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1367691155 |
| Directory | /workspace/45.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3751157538 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 33079028 ps |
| CPU time | 0.74 seconds |
| Started | Jul 11 04:31:23 PM PDT 24 |
| Finished | Jul 11 04:31:43 PM PDT 24 |
| Peak memory | 196452 kb |
| Host | smart-1c26d7fd-41ba-4d14-8f36-30baca50d1d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3751157538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3751157538 |
| Directory | /workspace/45.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/45.gpio_filter_stress.2993839393 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 2301272950 ps |
| CPU time | 5.78 seconds |
| Started | Jul 11 04:31:27 PM PDT 24 |
| Finished | Jul 11 04:31:52 PM PDT 24 |
| Peak memory | 196240 kb |
| Host | smart-81cae45b-5613-416f-8706-5058aea1c51a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993839393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre ss.2993839393 |
| Directory | /workspace/45.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/45.gpio_full_random.397336611 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 63786098 ps |
| CPU time | 0.92 seconds |
| Started | Jul 11 04:31:27 PM PDT 24 |
| Finished | Jul 11 04:31:47 PM PDT 24 |
| Peak memory | 197172 kb |
| Host | smart-0a7b8276-7acc-48d2-9dd2-f76e98b3c4ce |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397336611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.397336611 |
| Directory | /workspace/45.gpio_full_random/latest |
| Test location | /workspace/coverage/default/45.gpio_intr_rand_pgm.1453042726 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 119677063 ps |
| CPU time | 1.02 seconds |
| Started | Jul 11 04:31:22 PM PDT 24 |
| Finished | Jul 11 04:31:43 PM PDT 24 |
| Peak memory | 197372 kb |
| Host | smart-3577d394-76b1-423f-8ac3-54f9b47d567a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453042726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1453042726 |
| Directory | /workspace/45.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1386889652 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 71571877 ps |
| CPU time | 2.69 seconds |
| Started | Jul 11 04:31:35 PM PDT 24 |
| Finished | Jul 11 04:31:56 PM PDT 24 |
| Peak memory | 198444 kb |
| Host | smart-7a8cdc23-6c5c-4a08-a5c7-74692b1a2d9f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386889652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1386889652 |
| Directory | /workspace/45.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/45.gpio_rand_intr_trigger.1890505843 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 135872585 ps |
| CPU time | 1.67 seconds |
| Started | Jul 11 04:31:22 PM PDT 24 |
| Finished | Jul 11 04:31:44 PM PDT 24 |
| Peak memory | 196668 kb |
| Host | smart-2243a494-1817-47e7-aded-f1dcc69e6718 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890505843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger .1890505843 |
| Directory | /workspace/45.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/45.gpio_random_dout_din.2779121682 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 75389624 ps |
| CPU time | 0.63 seconds |
| Started | Jul 11 04:31:21 PM PDT 24 |
| Finished | Jul 11 04:31:41 PM PDT 24 |
| Peak memory | 194904 kb |
| Host | smart-db3a5ef2-9327-4ab4-b745-5f7a6e01d79f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2779121682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2779121682 |
| Directory | /workspace/45.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.111403506 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 91215080 ps |
| CPU time | 0.91 seconds |
| Started | Jul 11 04:31:23 PM PDT 24 |
| Finished | Jul 11 04:31:43 PM PDT 24 |
| Peak memory | 196576 kb |
| Host | smart-ba9bdd48-b998-4c89-8355-f85fb9145778 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111403506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup _pulldown.111403506 |
| Directory | /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1459327936 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 61134293 ps |
| CPU time | 2.69 seconds |
| Started | Jul 11 04:31:30 PM PDT 24 |
| Finished | Jul 11 04:31:51 PM PDT 24 |
| Peak memory | 198500 kb |
| Host | smart-c10609ea-0b24-4607-9c0e-e43995cc340b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459327936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra ndom_long_reg_writes_reg_reads.1459327936 |
| Directory | /workspace/45.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/45.gpio_smoke.2032476965 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 36387957 ps |
| CPU time | 1.21 seconds |
| Started | Jul 11 04:31:23 PM PDT 24 |
| Finished | Jul 11 04:31:43 PM PDT 24 |
| Peak memory | 198644 kb |
| Host | smart-25fa4abf-f96b-45e0-8590-c0f3975ea5fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2032476965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2032476965 |
| Directory | /workspace/45.gpio_smoke/latest |
| Test location | /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1079938377 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 28248045 ps |
| CPU time | 0.87 seconds |
| Started | Jul 11 04:31:27 PM PDT 24 |
| Finished | Jul 11 04:31:47 PM PDT 24 |
| Peak memory | 196840 kb |
| Host | smart-f5a38adb-a30c-47b2-b184-8d9f2e7e2c9f |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079938377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1079938377 |
| Directory | /workspace/45.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/45.gpio_stress_all.1588593385 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 180823632786 ps |
| CPU time | 146.11 seconds |
| Started | Jul 11 04:31:24 PM PDT 24 |
| Finished | Jul 11 04:34:09 PM PDT 24 |
| Peak memory | 198652 kb |
| Host | smart-e9f75375-842c-4d74-90cb-a20683140ffc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588593385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. gpio_stress_all.1588593385 |
| Directory | /workspace/45.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.590774122 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 52006806278 ps |
| CPU time | 746.14 seconds |
| Started | Jul 11 04:31:33 PM PDT 24 |
| Finished | Jul 11 04:44:17 PM PDT 24 |
| Peak memory | 198780 kb |
| Host | smart-298d6c16-eb32-4862-a33f-e4c7b1f65e5e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =590774122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.590774122 |
| Directory | /workspace/45.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.gpio_alert_test.308581541 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 39222357 ps |
| CPU time | 0.55 seconds |
| Started | Jul 11 04:31:25 PM PDT 24 |
| Finished | Jul 11 04:31:45 PM PDT 24 |
| Peak memory | 195524 kb |
| Host | smart-37e53464-1c47-4a3c-bbbe-bae09873fc2f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308581541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.308581541 |
| Directory | /workspace/46.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.783716373 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 62376414 ps |
| CPU time | 0.61 seconds |
| Started | Jul 11 04:31:17 PM PDT 24 |
| Finished | Jul 11 04:31:36 PM PDT 24 |
| Peak memory | 194640 kb |
| Host | smart-ef3d29ce-2af6-4aeb-a3fd-d2eb6581c14d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=783716373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.783716373 |
| Directory | /workspace/46.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/46.gpio_filter_stress.1783247014 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 9933644919 ps |
| CPU time | 23.55 seconds |
| Started | Jul 11 04:31:32 PM PDT 24 |
| Finished | Jul 11 04:32:14 PM PDT 24 |
| Peak memory | 198640 kb |
| Host | smart-006db220-d5c5-4e4f-b76f-6decf33a76f5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783247014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre ss.1783247014 |
| Directory | /workspace/46.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/46.gpio_full_random.3012358240 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 378933993 ps |
| CPU time | 1.03 seconds |
| Started | Jul 11 04:31:34 PM PDT 24 |
| Finished | Jul 11 04:31:53 PM PDT 24 |
| Peak memory | 197164 kb |
| Host | smart-d9ff1515-0f0b-45f6-b351-a2c324100c75 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012358240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3012358240 |
| Directory | /workspace/46.gpio_full_random/latest |
| Test location | /workspace/coverage/default/46.gpio_intr_rand_pgm.4039215990 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 48149431 ps |
| CPU time | 1.21 seconds |
| Started | Jul 11 04:31:18 PM PDT 24 |
| Finished | Jul 11 04:31:39 PM PDT 24 |
| Peak memory | 198024 kb |
| Host | smart-c75f23b9-9dcd-4866-bb1d-df99465e20cc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039215990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.4039215990 |
| Directory | /workspace/46.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.441186203 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 176494163 ps |
| CPU time | 3.14 seconds |
| Started | Jul 11 04:31:17 PM PDT 24 |
| Finished | Jul 11 04:31:39 PM PDT 24 |
| Peak memory | 196960 kb |
| Host | smart-83a043a6-14ce-4509-b554-bf7b0ab7d7bd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441186203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 46.gpio_intr_with_filter_rand_intr_event.441186203 |
| Directory | /workspace/46.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/46.gpio_rand_intr_trigger.3692541136 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 70868820 ps |
| CPU time | 1.08 seconds |
| Started | Jul 11 04:31:17 PM PDT 24 |
| Finished | Jul 11 04:31:37 PM PDT 24 |
| Peak memory | 196264 kb |
| Host | smart-042c1bed-36ac-473a-b628-890bf8b6134f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692541136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger .3692541136 |
| Directory | /workspace/46.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/46.gpio_random_dout_din.2293072201 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 39157008 ps |
| CPU time | 0.96 seconds |
| Started | Jul 11 04:31:35 PM PDT 24 |
| Finished | Jul 11 04:31:54 PM PDT 24 |
| Peak memory | 196992 kb |
| Host | smart-ebdedc79-787e-499f-b426-f2b9510ddd24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2293072201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2293072201 |
| Directory | /workspace/46.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.4016987153 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 59930776 ps |
| CPU time | 1.11 seconds |
| Started | Jul 11 04:31:21 PM PDT 24 |
| Finished | Jul 11 04:31:42 PM PDT 24 |
| Peak memory | 198600 kb |
| Host | smart-88f71dfb-e4fb-419e-b8af-8049327d7be3 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016987153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu p_pulldown.4016987153 |
| Directory | /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2988954422 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 246100130 ps |
| CPU time | 2.55 seconds |
| Started | Jul 11 04:31:28 PM PDT 24 |
| Finished | Jul 11 04:31:50 PM PDT 24 |
| Peak memory | 198652 kb |
| Host | smart-f1767f1e-b11e-4e81-9595-7151c922ac4d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988954422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra ndom_long_reg_writes_reg_reads.2988954422 |
| Directory | /workspace/46.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/46.gpio_smoke.366272033 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 130222555 ps |
| CPU time | 1.27 seconds |
| Started | Jul 11 04:31:55 PM PDT 24 |
| Finished | Jul 11 04:32:20 PM PDT 24 |
| Peak memory | 196364 kb |
| Host | smart-672efbdc-3aca-4af2-8491-dc3743daa117 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=366272033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.366272033 |
| Directory | /workspace/46.gpio_smoke/latest |
| Test location | /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2079923913 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 142646681 ps |
| CPU time | 1.18 seconds |
| Started | Jul 11 04:31:28 PM PDT 24 |
| Finished | Jul 11 04:31:48 PM PDT 24 |
| Peak memory | 197360 kb |
| Host | smart-941598b4-5894-4077-aaa4-f0c966f647d3 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079923913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2079923913 |
| Directory | /workspace/46.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/46.gpio_stress_all.1820235634 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 10827343870 ps |
| CPU time | 69.05 seconds |
| Started | Jul 11 04:31:53 PM PDT 24 |
| Finished | Jul 11 04:33:27 PM PDT 24 |
| Peak memory | 198668 kb |
| Host | smart-8cbcfc27-7708-45b9-a9ef-5d78106edeef |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820235634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. gpio_stress_all.1820235634 |
| Directory | /workspace/46.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/47.gpio_alert_test.979092473 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 16980877 ps |
| CPU time | 0.56 seconds |
| Started | Jul 11 04:31:25 PM PDT 24 |
| Finished | Jul 11 04:31:45 PM PDT 24 |
| Peak memory | 195220 kb |
| Host | smart-662030c9-1b20-4d4f-b601-e18b31b67d5b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979092473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.979092473 |
| Directory | /workspace/47.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.219170743 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 50227552 ps |
| CPU time | 0.67 seconds |
| Started | Jul 11 04:31:49 PM PDT 24 |
| Finished | Jul 11 04:32:13 PM PDT 24 |
| Peak memory | 194552 kb |
| Host | smart-968b3786-d35e-42f3-8398-fb4669cefced |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219170743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.219170743 |
| Directory | /workspace/47.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/47.gpio_filter_stress.2765704121 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1980159948 ps |
| CPU time | 27.82 seconds |
| Started | Jul 11 04:31:45 PM PDT 24 |
| Finished | Jul 11 04:32:34 PM PDT 24 |
| Peak memory | 197496 kb |
| Host | smart-14955974-07da-472b-b174-3db52dc30432 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765704121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre ss.2765704121 |
| Directory | /workspace/47.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/47.gpio_full_random.1031394724 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 63159226 ps |
| CPU time | 0.71 seconds |
| Started | Jul 11 04:32:00 PM PDT 24 |
| Finished | Jul 11 04:32:27 PM PDT 24 |
| Peak memory | 196184 kb |
| Host | smart-2168df30-23d3-49cb-a51e-f233ee24923c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031394724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1031394724 |
| Directory | /workspace/47.gpio_full_random/latest |
| Test location | /workspace/coverage/default/47.gpio_intr_rand_pgm.3499138244 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 93656784 ps |
| CPU time | 1.36 seconds |
| Started | Jul 11 04:31:47 PM PDT 24 |
| Finished | Jul 11 04:32:10 PM PDT 24 |
| Peak memory | 198632 kb |
| Host | smart-31248e71-5b10-4924-8e5f-5b46ccec8962 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499138244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3499138244 |
| Directory | /workspace/47.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.4018864547 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 162862426 ps |
| CPU time | 1.57 seconds |
| Started | Jul 11 04:31:36 PM PDT 24 |
| Finished | Jul 11 04:32:02 PM PDT 24 |
| Peak memory | 197256 kb |
| Host | smart-4adb1bac-d75c-4463-88c9-c47e9e1aff92 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018864547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.gpio_intr_with_filter_rand_intr_event.4018864547 |
| Directory | /workspace/47.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/47.gpio_rand_intr_trigger.3267906625 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 34495350 ps |
| CPU time | 0.86 seconds |
| Started | Jul 11 04:31:36 PM PDT 24 |
| Finished | Jul 11 04:31:54 PM PDT 24 |
| Peak memory | 195984 kb |
| Host | smart-9bc646bd-872e-4758-82d0-2df8f59f098e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267906625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger .3267906625 |
| Directory | /workspace/47.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/47.gpio_random_dout_din.4243385136 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 69405285 ps |
| CPU time | 0.63 seconds |
| Started | Jul 11 04:31:18 PM PDT 24 |
| Finished | Jul 11 04:31:38 PM PDT 24 |
| Peak memory | 194864 kb |
| Host | smart-23610def-f55f-463f-8203-b51dd51b9d90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4243385136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.4243385136 |
| Directory | /workspace/47.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1472553438 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 27261358 ps |
| CPU time | 0.72 seconds |
| Started | Jul 11 04:31:31 PM PDT 24 |
| Finished | Jul 11 04:31:51 PM PDT 24 |
| Peak memory | 196648 kb |
| Host | smart-105a58a9-35d1-49cf-8504-9fd0dd2bb1fb |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472553438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu p_pulldown.1472553438 |
| Directory | /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.317183498 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 127092956 ps |
| CPU time | 4.23 seconds |
| Started | Jul 11 04:31:45 PM PDT 24 |
| Finished | Jul 11 04:32:10 PM PDT 24 |
| Peak memory | 198524 kb |
| Host | smart-f38d73a1-f40a-40e1-823f-fde1a0a903ec |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317183498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran dom_long_reg_writes_reg_reads.317183498 |
| Directory | /workspace/47.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/47.gpio_smoke.708590126 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 185053732 ps |
| CPU time | 1.42 seconds |
| Started | Jul 11 04:31:33 PM PDT 24 |
| Finished | Jul 11 04:31:52 PM PDT 24 |
| Peak memory | 197484 kb |
| Host | smart-e87a4eba-2733-4375-8127-b76594629959 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=708590126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.708590126 |
| Directory | /workspace/47.gpio_smoke/latest |
| Test location | /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.797946982 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 50592360 ps |
| CPU time | 1.22 seconds |
| Started | Jul 11 04:31:34 PM PDT 24 |
| Finished | Jul 11 04:31:53 PM PDT 24 |
| Peak memory | 197244 kb |
| Host | smart-2a751a62-502e-44db-88f6-7d0ac9b95286 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797946982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.797946982 |
| Directory | /workspace/47.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/47.gpio_stress_all.3581368906 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 47216253417 ps |
| CPU time | 180.13 seconds |
| Started | Jul 11 04:31:24 PM PDT 24 |
| Finished | Jul 11 04:34:44 PM PDT 24 |
| Peak memory | 198752 kb |
| Host | smart-8b4fcc9e-a08b-44e1-bc11-42b629b15449 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581368906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. gpio_stress_all.3581368906 |
| Directory | /workspace/47.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.1229079655 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 279495250422 ps |
| CPU time | 809.02 seconds |
| Started | Jul 11 04:31:54 PM PDT 24 |
| Finished | Jul 11 04:45:48 PM PDT 24 |
| Peak memory | 206980 kb |
| Host | smart-87c34053-9297-4a07-8c00-9461a6612f43 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1229079655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.1229079655 |
| Directory | /workspace/47.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.gpio_alert_test.3995055662 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 12064139 ps |
| CPU time | 0.58 seconds |
| Started | Jul 11 04:31:55 PM PDT 24 |
| Finished | Jul 11 04:32:20 PM PDT 24 |
| Peak memory | 194708 kb |
| Host | smart-ef095927-4343-418e-9741-7a7570e2b737 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995055662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3995055662 |
| Directory | /workspace/48.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.820715122 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 156027138 ps |
| CPU time | 0.7 seconds |
| Started | Jul 11 04:31:33 PM PDT 24 |
| Finished | Jul 11 04:31:51 PM PDT 24 |
| Peak memory | 196668 kb |
| Host | smart-3d967ad0-71ad-481a-96c8-e914d9b57481 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=820715122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.820715122 |
| Directory | /workspace/48.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/48.gpio_filter_stress.2900068467 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 1396925072 ps |
| CPU time | 12.8 seconds |
| Started | Jul 11 04:31:31 PM PDT 24 |
| Finished | Jul 11 04:32:03 PM PDT 24 |
| Peak memory | 198608 kb |
| Host | smart-6be5b9e3-1bb9-4a3c-a3c0-9455c3e8ae77 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900068467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre ss.2900068467 |
| Directory | /workspace/48.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/48.gpio_full_random.1057873426 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 82928105 ps |
| CPU time | 0.9 seconds |
| Started | Jul 11 04:31:28 PM PDT 24 |
| Finished | Jul 11 04:31:48 PM PDT 24 |
| Peak memory | 197792 kb |
| Host | smart-0838c6f5-601c-4348-ade6-d35dbf9a963e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057873426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1057873426 |
| Directory | /workspace/48.gpio_full_random/latest |
| Test location | /workspace/coverage/default/48.gpio_intr_rand_pgm.1584319749 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 108462099 ps |
| CPU time | 1.55 seconds |
| Started | Jul 11 04:31:42 PM PDT 24 |
| Finished | Jul 11 04:32:04 PM PDT 24 |
| Peak memory | 197652 kb |
| Host | smart-d0d0afa3-157f-4765-8b20-a8f6cc62a0eb |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584319749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1584319749 |
| Directory | /workspace/48.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2035785054 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 75600033 ps |
| CPU time | 2.89 seconds |
| Started | Jul 11 04:31:27 PM PDT 24 |
| Finished | Jul 11 04:31:54 PM PDT 24 |
| Peak memory | 198616 kb |
| Host | smart-aba83536-e7fd-4bb7-987e-a8ab366b5a62 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035785054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2035785054 |
| Directory | /workspace/48.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/48.gpio_rand_intr_trigger.916134382 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 104058788 ps |
| CPU time | 2.96 seconds |
| Started | Jul 11 04:31:33 PM PDT 24 |
| Finished | Jul 11 04:31:54 PM PDT 24 |
| Peak memory | 197640 kb |
| Host | smart-baa327aa-17f3-4920-b2c6-175cc95a2829 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916134382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger. 916134382 |
| Directory | /workspace/48.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/48.gpio_random_dout_din.1156719182 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 51331716 ps |
| CPU time | 1.16 seconds |
| Started | Jul 11 04:31:28 PM PDT 24 |
| Finished | Jul 11 04:31:48 PM PDT 24 |
| Peak memory | 197664 kb |
| Host | smart-497f80e5-74e8-4c47-a1c3-1057339f9af8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1156719182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1156719182 |
| Directory | /workspace/48.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3241311302 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 303375529 ps |
| CPU time | 1.07 seconds |
| Started | Jul 11 04:31:44 PM PDT 24 |
| Finished | Jul 11 04:32:05 PM PDT 24 |
| Peak memory | 197196 kb |
| Host | smart-4be373d3-24da-4bc6-9783-f81ad7f7ad89 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241311302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu p_pulldown.3241311302 |
| Directory | /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3262831049 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 326475948 ps |
| CPU time | 2.29 seconds |
| Started | Jul 11 04:31:58 PM PDT 24 |
| Finished | Jul 11 04:32:25 PM PDT 24 |
| Peak memory | 198604 kb |
| Host | smart-32a3ee65-0957-472b-a837-3517d29be38c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262831049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra ndom_long_reg_writes_reg_reads.3262831049 |
| Directory | /workspace/48.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/48.gpio_smoke.479516799 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 58152242 ps |
| CPU time | 1.32 seconds |
| Started | Jul 11 04:31:41 PM PDT 24 |
| Finished | Jul 11 04:32:02 PM PDT 24 |
| Peak memory | 196264 kb |
| Host | smart-d729d119-53dd-45e3-bb12-baeb9bdb15a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=479516799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.479516799 |
| Directory | /workspace/48.gpio_smoke/latest |
| Test location | /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.206818555 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 705471283 ps |
| CPU time | 0.98 seconds |
| Started | Jul 11 04:31:34 PM PDT 24 |
| Finished | Jul 11 04:31:53 PM PDT 24 |
| Peak memory | 196272 kb |
| Host | smart-aa93387d-5dea-4cdb-8135-57e95133eeca |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206818555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.206818555 |
| Directory | /workspace/48.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/48.gpio_stress_all.908975891 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 2708131822 ps |
| CPU time | 70.18 seconds |
| Started | Jul 11 04:31:37 PM PDT 24 |
| Finished | Jul 11 04:33:06 PM PDT 24 |
| Peak memory | 198604 kb |
| Host | smart-714d2f0f-e793-40ee-a707-528a20b4ae43 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908975891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g pio_stress_all.908975891 |
| Directory | /workspace/48.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/49.gpio_alert_test.459546169 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 11314047 ps |
| CPU time | 0.56 seconds |
| Started | Jul 11 04:31:33 PM PDT 24 |
| Finished | Jul 11 04:31:52 PM PDT 24 |
| Peak memory | 194612 kb |
| Host | smart-c82a6692-6e77-4c4a-827b-1e190c36170a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459546169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.459546169 |
| Directory | /workspace/49.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1842644696 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 57417748 ps |
| CPU time | 0.71 seconds |
| Started | Jul 11 04:31:45 PM PDT 24 |
| Finished | Jul 11 04:32:07 PM PDT 24 |
| Peak memory | 195812 kb |
| Host | smart-cec1998a-d411-4c50-bf98-3aa1329d764b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1842644696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1842644696 |
| Directory | /workspace/49.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/49.gpio_filter_stress.3555470985 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 2162907315 ps |
| CPU time | 13.49 seconds |
| Started | Jul 11 04:31:50 PM PDT 24 |
| Finished | Jul 11 04:32:27 PM PDT 24 |
| Peak memory | 197612 kb |
| Host | smart-b7a301bb-d3f7-495b-81c1-c806ebd2e339 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555470985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre ss.3555470985 |
| Directory | /workspace/49.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/49.gpio_full_random.1888712285 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 155782068 ps |
| CPU time | 1.02 seconds |
| Started | Jul 11 04:31:39 PM PDT 24 |
| Finished | Jul 11 04:31:59 PM PDT 24 |
| Peak memory | 197260 kb |
| Host | smart-b9bb9477-161f-4ea4-a8b7-3a27fc52cccc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888712285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1888712285 |
| Directory | /workspace/49.gpio_full_random/latest |
| Test location | /workspace/coverage/default/49.gpio_intr_rand_pgm.2649369952 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 191327116 ps |
| CPU time | 1.38 seconds |
| Started | Jul 11 04:31:32 PM PDT 24 |
| Finished | Jul 11 04:31:52 PM PDT 24 |
| Peak memory | 197820 kb |
| Host | smart-4db6a0fb-2f5c-4706-b5c6-53e0550c3456 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649369952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2649369952 |
| Directory | /workspace/49.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3108572600 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 174857535 ps |
| CPU time | 3.29 seconds |
| Started | Jul 11 04:31:49 PM PDT 24 |
| Finished | Jul 11 04:32:16 PM PDT 24 |
| Peak memory | 198584 kb |
| Host | smart-ac2ba5ba-b6f0-424f-98c4-87c3c37dc4bb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108572600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3108572600 |
| Directory | /workspace/49.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/49.gpio_rand_intr_trigger.1972566289 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 354943713 ps |
| CPU time | 2.18 seconds |
| Started | Jul 11 04:31:36 PM PDT 24 |
| Finished | Jul 11 04:31:57 PM PDT 24 |
| Peak memory | 197872 kb |
| Host | smart-eb0d188e-62af-4019-aac3-d498c2cc4817 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972566289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger .1972566289 |
| Directory | /workspace/49.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/49.gpio_random_dout_din.2710480169 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 506998417 ps |
| CPU time | 1.25 seconds |
| Started | Jul 11 04:31:44 PM PDT 24 |
| Finished | Jul 11 04:32:05 PM PDT 24 |
| Peak memory | 198016 kb |
| Host | smart-15c5959a-d46a-4098-b822-91e0593b2da8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2710480169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2710480169 |
| Directory | /workspace/49.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2795762776 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 39210101 ps |
| CPU time | 0.66 seconds |
| Started | Jul 11 04:31:27 PM PDT 24 |
| Finished | Jul 11 04:31:47 PM PDT 24 |
| Peak memory | 194880 kb |
| Host | smart-51f58af3-8be5-4624-a51d-dd0e65dc440a |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795762776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu p_pulldown.2795762776 |
| Directory | /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.357448907 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 55423016 ps |
| CPU time | 1.17 seconds |
| Started | Jul 11 04:31:32 PM PDT 24 |
| Finished | Jul 11 04:31:51 PM PDT 24 |
| Peak memory | 198564 kb |
| Host | smart-2ffad910-29b4-4584-8fba-756450196af4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357448907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran dom_long_reg_writes_reg_reads.357448907 |
| Directory | /workspace/49.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/49.gpio_smoke.811404100 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 191582915 ps |
| CPU time | 0.86 seconds |
| Started | Jul 11 04:31:24 PM PDT 24 |
| Finished | Jul 11 04:31:45 PM PDT 24 |
| Peak memory | 195952 kb |
| Host | smart-39e79296-6f3b-447a-8d3c-c422f96e3ebb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=811404100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.811404100 |
| Directory | /workspace/49.gpio_smoke/latest |
| Test location | /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1256407202 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 90567487 ps |
| CPU time | 0.88 seconds |
| Started | Jul 11 04:31:29 PM PDT 24 |
| Finished | Jul 11 04:31:48 PM PDT 24 |
| Peak memory | 196104 kb |
| Host | smart-fe5900e9-0846-4274-a366-2614ac2c48d5 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256407202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1256407202 |
| Directory | /workspace/49.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/49.gpio_stress_all.1577430672 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 3295090424 ps |
| CPU time | 77.27 seconds |
| Started | Jul 11 04:31:43 PM PDT 24 |
| Finished | Jul 11 04:33:20 PM PDT 24 |
| Peak memory | 198616 kb |
| Host | smart-b70512fc-48b6-42e5-a8b8-fe2987b4f0cd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577430672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. gpio_stress_all.1577430672 |
| Directory | /workspace/49.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.1688289854 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 149732193239 ps |
| CPU time | 1940.14 seconds |
| Started | Jul 11 04:31:25 PM PDT 24 |
| Finished | Jul 11 05:04:05 PM PDT 24 |
| Peak memory | 198744 kb |
| Host | smart-16248856-2dc4-4744-a950-69600eae57f6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1688289854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.1688289854 |
| Directory | /workspace/49.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.gpio_alert_test.1810227554 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 53026796 ps |
| CPU time | 0.57 seconds |
| Started | Jul 11 04:30:12 PM PDT 24 |
| Finished | Jul 11 04:30:20 PM PDT 24 |
| Peak memory | 194696 kb |
| Host | smart-f1aa48ef-28ac-40f2-a282-aa1ae2eb9338 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810227554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1810227554 |
| Directory | /workspace/5.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.329862614 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 33643453 ps |
| CPU time | 0.86 seconds |
| Started | Jul 11 04:29:57 PM PDT 24 |
| Finished | Jul 11 04:30:04 PM PDT 24 |
| Peak memory | 195956 kb |
| Host | smart-5043fb08-4431-4eaf-a58f-a767b23b8d48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=329862614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.329862614 |
| Directory | /workspace/5.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/5.gpio_filter_stress.3430118054 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 481767060 ps |
| CPU time | 6.48 seconds |
| Started | Jul 11 04:29:50 PM PDT 24 |
| Finished | Jul 11 04:29:58 PM PDT 24 |
| Peak memory | 197384 kb |
| Host | smart-02548b50-ecd4-4eab-88ab-d514c7e595e8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430118054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres s.3430118054 |
| Directory | /workspace/5.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/5.gpio_full_random.3581009781 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 71302051 ps |
| CPU time | 0.89 seconds |
| Started | Jul 11 04:30:13 PM PDT 24 |
| Finished | Jul 11 04:30:22 PM PDT 24 |
| Peak memory | 197364 kb |
| Host | smart-2f79f991-4f58-4363-af44-11e0973523d0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581009781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3581009781 |
| Directory | /workspace/5.gpio_full_random/latest |
| Test location | /workspace/coverage/default/5.gpio_intr_rand_pgm.3395163657 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 63512639 ps |
| CPU time | 0.81 seconds |
| Started | Jul 11 04:30:00 PM PDT 24 |
| Finished | Jul 11 04:30:09 PM PDT 24 |
| Peak memory | 196696 kb |
| Host | smart-94c3a1d1-dab0-4a55-a8db-4f44ed87dff4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395163657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3395163657 |
| Directory | /workspace/5.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.649365642 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 129485195 ps |
| CPU time | 2.57 seconds |
| Started | Jul 11 04:30:14 PM PDT 24 |
| Finished | Jul 11 04:30:27 PM PDT 24 |
| Peak memory | 198712 kb |
| Host | smart-c818b3e0-a5a4-4fdc-985d-2f516359aec3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649365642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 5.gpio_intr_with_filter_rand_intr_event.649365642 |
| Directory | /workspace/5.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/5.gpio_rand_intr_trigger.3887682538 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 136806138 ps |
| CPU time | 2.58 seconds |
| Started | Jul 11 04:30:14 PM PDT 24 |
| Finished | Jul 11 04:30:27 PM PDT 24 |
| Peak memory | 197640 kb |
| Host | smart-04ed4417-2e23-41a7-999a-cfff56bb007f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887682538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger. 3887682538 |
| Directory | /workspace/5.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/5.gpio_random_dout_din.2449391875 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 58716627 ps |
| CPU time | 1.05 seconds |
| Started | Jul 11 04:29:57 PM PDT 24 |
| Finished | Jul 11 04:30:04 PM PDT 24 |
| Peak memory | 196356 kb |
| Host | smart-61e4ee19-4267-40f9-a69f-a45a59a6e47b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2449391875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2449391875 |
| Directory | /workspace/5.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2074473655 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 149566523 ps |
| CPU time | 0.93 seconds |
| Started | Jul 11 04:29:52 PM PDT 24 |
| Finished | Jul 11 04:29:55 PM PDT 24 |
| Peak memory | 196584 kb |
| Host | smart-50ea3629-efb2-432e-8f7d-0820a3d96bb1 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074473655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup _pulldown.2074473655 |
| Directory | /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.54703197 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 116518075 ps |
| CPU time | 3.61 seconds |
| Started | Jul 11 04:29:47 PM PDT 24 |
| Finished | Jul 11 04:29:53 PM PDT 24 |
| Peak memory | 198508 kb |
| Host | smart-72f89373-69b7-4a65-8cff-11f00d03befe |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54703197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rando m_long_reg_writes_reg_reads.54703197 |
| Directory | /workspace/5.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/5.gpio_smoke.2616028976 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 159203130 ps |
| CPU time | 1.25 seconds |
| Started | Jul 11 04:29:48 PM PDT 24 |
| Finished | Jul 11 04:29:51 PM PDT 24 |
| Peak memory | 197464 kb |
| Host | smart-5ad6b4d7-03bd-483c-b245-8cc6dcfdddc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2616028976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2616028976 |
| Directory | /workspace/5.gpio_smoke/latest |
| Test location | /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2454331753 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 73552430 ps |
| CPU time | 0.95 seconds |
| Started | Jul 11 04:30:00 PM PDT 24 |
| Finished | Jul 11 04:30:10 PM PDT 24 |
| Peak memory | 196488 kb |
| Host | smart-625798f2-73f8-40d7-b0f7-7d5e00534dfa |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454331753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2454331753 |
| Directory | /workspace/5.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/5.gpio_stress_all.3750284670 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 4355365338 ps |
| CPU time | 115.16 seconds |
| Started | Jul 11 04:30:08 PM PDT 24 |
| Finished | Jul 11 04:32:10 PM PDT 24 |
| Peak memory | 198552 kb |
| Host | smart-35541dce-4258-4d0b-81dd-6e8551d6992b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750284670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g pio_stress_all.3750284670 |
| Directory | /workspace/5.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/6.gpio_alert_test.2971508465 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 52104881 ps |
| CPU time | 0.57 seconds |
| Started | Jul 11 04:30:03 PM PDT 24 |
| Finished | Jul 11 04:30:13 PM PDT 24 |
| Peak memory | 194728 kb |
| Host | smart-68692b9a-9664-4386-94f0-354fa4395946 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971508465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2971508465 |
| Directory | /workspace/6.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2425644990 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 51591862 ps |
| CPU time | 0.62 seconds |
| Started | Jul 11 04:30:09 PM PDT 24 |
| Finished | Jul 11 04:30:17 PM PDT 24 |
| Peak memory | 194572 kb |
| Host | smart-b00182e9-45fc-411a-9766-d71f050461d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2425644990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2425644990 |
| Directory | /workspace/6.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/6.gpio_filter_stress.614246621 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 472486413 ps |
| CPU time | 8.14 seconds |
| Started | Jul 11 04:30:13 PM PDT 24 |
| Finished | Jul 11 04:30:29 PM PDT 24 |
| Peak memory | 198824 kb |
| Host | smart-547ab5d7-1113-4687-bfcd-59ac092f929d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614246621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress .614246621 |
| Directory | /workspace/6.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/6.gpio_full_random.660984099 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 37228256 ps |
| CPU time | 0.79 seconds |
| Started | Jul 11 04:30:00 PM PDT 24 |
| Finished | Jul 11 04:30:09 PM PDT 24 |
| Peak memory | 196500 kb |
| Host | smart-2ff68c54-b91f-4d91-8b7a-aec16f6a6f29 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660984099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.660984099 |
| Directory | /workspace/6.gpio_full_random/latest |
| Test location | /workspace/coverage/default/6.gpio_intr_rand_pgm.3103391697 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 25654659 ps |
| CPU time | 0.81 seconds |
| Started | Jul 11 04:30:01 PM PDT 24 |
| Finished | Jul 11 04:30:12 PM PDT 24 |
| Peak memory | 195868 kb |
| Host | smart-e560fe52-9150-4850-9b35-b0c0226da4a3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103391697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3103391697 |
| Directory | /workspace/6.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2493602154 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 127942679 ps |
| CPU time | 3.28 seconds |
| Started | Jul 11 04:29:55 PM PDT 24 |
| Finished | Jul 11 04:30:11 PM PDT 24 |
| Peak memory | 198584 kb |
| Host | smart-c78cb458-c3de-446b-aa81-6400a7edd6db |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493602154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2493602154 |
| Directory | /workspace/6.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/6.gpio_rand_intr_trigger.3412433978 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 542525033 ps |
| CPU time | 2.99 seconds |
| Started | Jul 11 04:29:56 PM PDT 24 |
| Finished | Jul 11 04:30:05 PM PDT 24 |
| Peak memory | 198632 kb |
| Host | smart-600ea3ea-95b9-46ac-9b32-70fb77f6c11b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412433978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger. 3412433978 |
| Directory | /workspace/6.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/6.gpio_random_dout_din.1799324862 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 167438201 ps |
| CPU time | 0.91 seconds |
| Started | Jul 11 04:30:14 PM PDT 24 |
| Finished | Jul 11 04:30:25 PM PDT 24 |
| Peak memory | 196672 kb |
| Host | smart-28e5b78a-cc07-4cc8-953e-44467f9cdf7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1799324862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1799324862 |
| Directory | /workspace/6.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1058397913 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 92936651 ps |
| CPU time | 0.81 seconds |
| Started | Jul 11 04:29:48 PM PDT 24 |
| Finished | Jul 11 04:29:51 PM PDT 24 |
| Peak memory | 197880 kb |
| Host | smart-3ae73973-5688-441f-8821-1152596275fa |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058397913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup _pulldown.1058397913 |
| Directory | /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2319407801 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 386575630 ps |
| CPU time | 5.99 seconds |
| Started | Jul 11 04:29:56 PM PDT 24 |
| Finished | Jul 11 04:30:07 PM PDT 24 |
| Peak memory | 198588 kb |
| Host | smart-a021596a-c25a-4d95-b77b-090e58dd00cc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319407801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran dom_long_reg_writes_reg_reads.2319407801 |
| Directory | /workspace/6.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/6.gpio_smoke.2791065125 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 69241699 ps |
| CPU time | 0.78 seconds |
| Started | Jul 11 04:29:53 PM PDT 24 |
| Finished | Jul 11 04:29:57 PM PDT 24 |
| Peak memory | 195768 kb |
| Host | smart-3c604a40-448a-4f88-bfc9-862dc2749aa0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2791065125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2791065125 |
| Directory | /workspace/6.gpio_smoke/latest |
| Test location | /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2817157653 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 204099903 ps |
| CPU time | 1.2 seconds |
| Started | Jul 11 04:29:57 PM PDT 24 |
| Finished | Jul 11 04:30:03 PM PDT 24 |
| Peak memory | 196272 kb |
| Host | smart-902f51bd-36e2-4da5-bd2d-634ede9b2169 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817157653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2817157653 |
| Directory | /workspace/6.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/6.gpio_stress_all.3458594563 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 4334481678 ps |
| CPU time | 124.35 seconds |
| Started | Jul 11 04:29:59 PM PDT 24 |
| Finished | Jul 11 04:32:13 PM PDT 24 |
| Peak memory | 198656 kb |
| Host | smart-f63874c7-15e1-489d-af5d-8cc41eb63721 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458594563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g pio_stress_all.3458594563 |
| Directory | /workspace/6.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/7.gpio_alert_test.2511651783 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 12095025 ps |
| CPU time | 0.55 seconds |
| Started | Jul 11 04:29:58 PM PDT 24 |
| Finished | Jul 11 04:30:05 PM PDT 24 |
| Peak memory | 194500 kb |
| Host | smart-852dcb04-c3a9-41a6-8f10-69d5ea6215e0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511651783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2511651783 |
| Directory | /workspace/7.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.954591354 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 274281332 ps |
| CPU time | 0.75 seconds |
| Started | Jul 11 04:30:02 PM PDT 24 |
| Finished | Jul 11 04:30:12 PM PDT 24 |
| Peak memory | 195836 kb |
| Host | smart-06dd0a7b-70a7-4192-bc0e-7d59e34659e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=954591354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.954591354 |
| Directory | /workspace/7.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/7.gpio_filter_stress.3540582868 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 497037808 ps |
| CPU time | 15.88 seconds |
| Started | Jul 11 04:30:15 PM PDT 24 |
| Finished | Jul 11 04:30:50 PM PDT 24 |
| Peak memory | 198048 kb |
| Host | smart-9c6e4189-75da-4160-9ce6-390bc21a05a8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540582868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres s.3540582868 |
| Directory | /workspace/7.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/7.gpio_full_random.4040646607 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 63532260 ps |
| CPU time | 0.92 seconds |
| Started | Jul 11 04:30:04 PM PDT 24 |
| Finished | Jul 11 04:30:14 PM PDT 24 |
| Peak memory | 197216 kb |
| Host | smart-bef2f601-5dd3-4d83-b85c-69df9572a0c3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040646607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.4040646607 |
| Directory | /workspace/7.gpio_full_random/latest |
| Test location | /workspace/coverage/default/7.gpio_intr_rand_pgm.1933075215 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 63518874 ps |
| CPU time | 0.91 seconds |
| Started | Jul 11 04:29:59 PM PDT 24 |
| Finished | Jul 11 04:30:09 PM PDT 24 |
| Peak memory | 197384 kb |
| Host | smart-45d2428e-dc47-43e8-aa2d-a08d1583ad5c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933075215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1933075215 |
| Directory | /workspace/7.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3041016704 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 279269375 ps |
| CPU time | 1.91 seconds |
| Started | Jul 11 04:29:53 PM PDT 24 |
| Finished | Jul 11 04:29:58 PM PDT 24 |
| Peak memory | 198516 kb |
| Host | smart-09a38fb1-c1ff-4486-a2ce-fb948e181ecf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041016704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3041016704 |
| Directory | /workspace/7.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/7.gpio_rand_intr_trigger.2913312605 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 357631887 ps |
| CPU time | 3.04 seconds |
| Started | Jul 11 04:30:00 PM PDT 24 |
| Finished | Jul 11 04:30:12 PM PDT 24 |
| Peak memory | 198652 kb |
| Host | smart-b9881f9d-c8d3-451b-ad45-15d653100e50 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913312605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger. 2913312605 |
| Directory | /workspace/7.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/7.gpio_random_dout_din.1767739102 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 185039268 ps |
| CPU time | 1.17 seconds |
| Started | Jul 11 04:30:13 PM PDT 24 |
| Finished | Jul 11 04:30:22 PM PDT 24 |
| Peak memory | 196668 kb |
| Host | smart-2a49f019-b598-4f32-b4bd-d9e58a3c24b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1767739102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1767739102 |
| Directory | /workspace/7.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2704825630 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 95002604 ps |
| CPU time | 1.17 seconds |
| Started | Jul 11 04:30:02 PM PDT 24 |
| Finished | Jul 11 04:30:12 PM PDT 24 |
| Peak memory | 198476 kb |
| Host | smart-2931fff3-623b-4da6-b830-b3c1b7b74242 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704825630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup _pulldown.2704825630 |
| Directory | /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.344383726 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 698912143 ps |
| CPU time | 4.17 seconds |
| Started | Jul 11 04:30:15 PM PDT 24 |
| Finished | Jul 11 04:30:30 PM PDT 24 |
| Peak memory | 198652 kb |
| Host | smart-1f28b5e3-6b8e-40f4-ad2d-e17e3aaa2a25 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344383726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand om_long_reg_writes_reg_reads.344383726 |
| Directory | /workspace/7.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/7.gpio_smoke.1664999720 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 144970949 ps |
| CPU time | 1.16 seconds |
| Started | Jul 11 04:30:07 PM PDT 24 |
| Finished | Jul 11 04:30:15 PM PDT 24 |
| Peak memory | 196068 kb |
| Host | smart-cc0216ab-ebaf-4ed6-85a6-67062ef475d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1664999720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1664999720 |
| Directory | /workspace/7.gpio_smoke/latest |
| Test location | /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.922844512 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 116442394 ps |
| CPU time | 1.21 seconds |
| Started | Jul 11 04:30:18 PM PDT 24 |
| Finished | Jul 11 04:30:32 PM PDT 24 |
| Peak memory | 197280 kb |
| Host | smart-70fce4b2-12f2-4b6c-9b08-37b663924aac |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922844512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.922844512 |
| Directory | /workspace/7.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/7.gpio_stress_all.3638338884 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 36893039023 ps |
| CPU time | 122.72 seconds |
| Started | Jul 11 04:30:19 PM PDT 24 |
| Finished | Jul 11 04:32:35 PM PDT 24 |
| Peak memory | 198596 kb |
| Host | smart-f98d4dc9-2b26-4d27-8675-1d57713728cf |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638338884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g pio_stress_all.3638338884 |
| Directory | /workspace/7.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/8.gpio_alert_test.2278922135 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 30523576 ps |
| CPU time | 0.54 seconds |
| Started | Jul 11 04:30:32 PM PDT 24 |
| Finished | Jul 11 04:30:42 PM PDT 24 |
| Peak memory | 194520 kb |
| Host | smart-037632d0-6810-41cb-83ea-e83cb3acfa91 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278922135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2278922135 |
| Directory | /workspace/8.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1143098673 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 40309466 ps |
| CPU time | 0.82 seconds |
| Started | Jul 11 04:30:12 PM PDT 24 |
| Finished | Jul 11 04:30:20 PM PDT 24 |
| Peak memory | 196720 kb |
| Host | smart-7fafcf20-fef9-4b90-bd29-036ed223fad5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1143098673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1143098673 |
| Directory | /workspace/8.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/8.gpio_filter_stress.842727032 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 258010013 ps |
| CPU time | 7.65 seconds |
| Started | Jul 11 04:30:24 PM PDT 24 |
| Finished | Jul 11 04:30:44 PM PDT 24 |
| Peak memory | 197824 kb |
| Host | smart-2199b483-4840-49a0-8b16-33d215cee229 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842727032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress .842727032 |
| Directory | /workspace/8.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/8.gpio_full_random.1069060699 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 85185390 ps |
| CPU time | 0.98 seconds |
| Started | Jul 11 04:29:58 PM PDT 24 |
| Finished | Jul 11 04:30:06 PM PDT 24 |
| Peak memory | 198264 kb |
| Host | smart-1ca44d84-446a-4a34-be00-228a05db507f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069060699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1069060699 |
| Directory | /workspace/8.gpio_full_random/latest |
| Test location | /workspace/coverage/default/8.gpio_intr_rand_pgm.1553499201 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 43167819 ps |
| CPU time | 1.18 seconds |
| Started | Jul 11 04:29:57 PM PDT 24 |
| Finished | Jul 11 04:30:03 PM PDT 24 |
| Peak memory | 196764 kb |
| Host | smart-b458dd76-1864-4339-80ab-7497a53afd88 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553499201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1553499201 |
| Directory | /workspace/8.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1194661094 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 127379572 ps |
| CPU time | 1.4 seconds |
| Started | Jul 11 04:29:59 PM PDT 24 |
| Finished | Jul 11 04:30:10 PM PDT 24 |
| Peak memory | 197420 kb |
| Host | smart-e26a952c-e70c-4d8c-a094-1fb9332c87c4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194661094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1194661094 |
| Directory | /workspace/8.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/8.gpio_rand_intr_trigger.2826582138 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 220234724 ps |
| CPU time | 1.83 seconds |
| Started | Jul 11 04:30:16 PM PDT 24 |
| Finished | Jul 11 04:30:29 PM PDT 24 |
| Peak memory | 196700 kb |
| Host | smart-bf86f436-b7bd-4223-9fac-249e8010813e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826582138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger. 2826582138 |
| Directory | /workspace/8.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/8.gpio_random_dout_din.1272666358 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 29894686 ps |
| CPU time | 1.07 seconds |
| Started | Jul 11 04:29:58 PM PDT 24 |
| Finished | Jul 11 04:30:07 PM PDT 24 |
| Peak memory | 197188 kb |
| Host | smart-42aff207-f16a-48f8-ba8a-9c51bee6cc79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1272666358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.1272666358 |
| Directory | /workspace/8.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.766040587 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 25986524 ps |
| CPU time | 0.64 seconds |
| Started | Jul 11 04:30:03 PM PDT 24 |
| Finished | Jul 11 04:30:12 PM PDT 24 |
| Peak memory | 194956 kb |
| Host | smart-ea833e44-b316-484e-a6d5-b03b23cbac73 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766040587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_ pulldown.766040587 |
| Directory | /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1627173071 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 274883144 ps |
| CPU time | 4.66 seconds |
| Started | Jul 11 04:30:42 PM PDT 24 |
| Finished | Jul 11 04:30:50 PM PDT 24 |
| Peak memory | 198484 kb |
| Host | smart-0665875a-cce1-4df2-a257-13ab595777c8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627173071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran dom_long_reg_writes_reg_reads.1627173071 |
| Directory | /workspace/8.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/8.gpio_smoke.3468706407 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 77944885 ps |
| CPU time | 0.83 seconds |
| Started | Jul 11 04:30:12 PM PDT 24 |
| Finished | Jul 11 04:30:20 PM PDT 24 |
| Peak memory | 196472 kb |
| Host | smart-12188c34-201c-46fc-b43d-115b5e3b706a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3468706407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3468706407 |
| Directory | /workspace/8.gpio_smoke/latest |
| Test location | /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1405948604 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 119945143 ps |
| CPU time | 0.96 seconds |
| Started | Jul 11 04:30:11 PM PDT 24 |
| Finished | Jul 11 04:30:18 PM PDT 24 |
| Peak memory | 195980 kb |
| Host | smart-3ebd0f14-3e4b-46c5-99e6-4a9d2a4a94a9 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405948604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1405948604 |
| Directory | /workspace/8.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/8.gpio_stress_all.1000588711 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 11226533727 ps |
| CPU time | 147.36 seconds |
| Started | Jul 11 04:30:03 PM PDT 24 |
| Finished | Jul 11 04:32:40 PM PDT 24 |
| Peak memory | 198652 kb |
| Host | smart-bfe3062d-2588-4520-9853-cee77652cfaa |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000588711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g pio_stress_all.1000588711 |
| Directory | /workspace/8.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/9.gpio_alert_test.2938581875 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 66917548 ps |
| CPU time | 0.56 seconds |
| Started | Jul 11 04:30:43 PM PDT 24 |
| Finished | Jul 11 04:30:47 PM PDT 24 |
| Peak memory | 194700 kb |
| Host | smart-03e1a1a8-48b4-4f29-8f0b-ea24d7da167b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938581875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2938581875 |
| Directory | /workspace/9.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2828494418 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 100004546 ps |
| CPU time | 0.86 seconds |
| Started | Jul 11 04:30:00 PM PDT 24 |
| Finished | Jul 11 04:30:10 PM PDT 24 |
| Peak memory | 196280 kb |
| Host | smart-370dade5-1ded-43b5-91aa-537d8a201aa4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2828494418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2828494418 |
| Directory | /workspace/9.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/9.gpio_filter_stress.3388325275 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 313491845 ps |
| CPU time | 8.33 seconds |
| Started | Jul 11 04:30:44 PM PDT 24 |
| Finished | Jul 11 04:30:56 PM PDT 24 |
| Peak memory | 197344 kb |
| Host | smart-2eedd664-cd12-4333-ad85-5d9146fe7840 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388325275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres s.3388325275 |
| Directory | /workspace/9.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/9.gpio_full_random.2829194332 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 117364421 ps |
| CPU time | 0.72 seconds |
| Started | Jul 11 04:29:59 PM PDT 24 |
| Finished | Jul 11 04:30:09 PM PDT 24 |
| Peak memory | 195316 kb |
| Host | smart-5173c6e2-cd58-4d01-b1db-e522d21d17fe |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829194332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2829194332 |
| Directory | /workspace/9.gpio_full_random/latest |
| Test location | /workspace/coverage/default/9.gpio_intr_rand_pgm.3462143402 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 81959558 ps |
| CPU time | 1.38 seconds |
| Started | Jul 11 04:30:22 PM PDT 24 |
| Finished | Jul 11 04:30:37 PM PDT 24 |
| Peak memory | 196392 kb |
| Host | smart-8e6c469b-69e3-4a72-95fe-f0af530cd630 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462143402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3462143402 |
| Directory | /workspace/9.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1913304253 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 40978864 ps |
| CPU time | 1.66 seconds |
| Started | Jul 11 04:30:14 PM PDT 24 |
| Finished | Jul 11 04:30:25 PM PDT 24 |
| Peak memory | 198552 kb |
| Host | smart-d25f5083-ec1b-4d3b-85a6-102936a3352a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913304253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1913304253 |
| Directory | /workspace/9.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/9.gpio_rand_intr_trigger.826398432 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 43949703 ps |
| CPU time | 1.24 seconds |
| Started | Jul 11 04:29:57 PM PDT 24 |
| Finished | Jul 11 04:30:04 PM PDT 24 |
| Peak memory | 196376 kb |
| Host | smart-a45ab5d3-9c89-4037-9e31-7e49a53913ec |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826398432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.826398432 |
| Directory | /workspace/9.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/9.gpio_random_dout_din.1583987343 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 60882383 ps |
| CPU time | 0.84 seconds |
| Started | Jul 11 04:30:43 PM PDT 24 |
| Finished | Jul 11 04:30:48 PM PDT 24 |
| Peak memory | 197232 kb |
| Host | smart-456a2635-a7c5-4d36-8819-5c42d76d3b54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1583987343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1583987343 |
| Directory | /workspace/9.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3886538104 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 32220475 ps |
| CPU time | 0.76 seconds |
| Started | Jul 11 04:29:59 PM PDT 24 |
| Finished | Jul 11 04:30:07 PM PDT 24 |
| Peak memory | 196184 kb |
| Host | smart-27568502-7e69-4695-8c57-e9a8fe2af105 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886538104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup _pulldown.3886538104 |
| Directory | /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3841000353 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 196621114 ps |
| CPU time | 1.48 seconds |
| Started | Jul 11 04:30:02 PM PDT 24 |
| Finished | Jul 11 04:30:12 PM PDT 24 |
| Peak memory | 198476 kb |
| Host | smart-57677622-2800-4153-a7b9-680c1f9cf0a7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841000353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran dom_long_reg_writes_reg_reads.3841000353 |
| Directory | /workspace/9.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/9.gpio_smoke.3582235907 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 45789443 ps |
| CPU time | 1.28 seconds |
| Started | Jul 11 04:30:08 PM PDT 24 |
| Finished | Jul 11 04:30:17 PM PDT 24 |
| Peak memory | 198592 kb |
| Host | smart-592eeb83-786d-49a2-a52a-cb7a09c2f3cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3582235907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3582235907 |
| Directory | /workspace/9.gpio_smoke/latest |
| Test location | /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2119350317 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 275168857 ps |
| CPU time | 1.12 seconds |
| Started | Jul 11 04:30:59 PM PDT 24 |
| Finished | Jul 11 04:31:06 PM PDT 24 |
| Peak memory | 196380 kb |
| Host | smart-61d6d8b0-e3a7-4d0f-8073-ef3dedb2ec2c |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119350317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2119350317 |
| Directory | /workspace/9.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/9.gpio_stress_all.75414123 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 7062833600 ps |
| CPU time | 99.14 seconds |
| Started | Jul 11 04:30:12 PM PDT 24 |
| Finished | Jul 11 04:31:58 PM PDT 24 |
| Peak memory | 198808 kb |
| Host | smart-f069385b-4461-4488-8f99-a29ceb8b289d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75414123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpi o_stress_all.75414123 |
| Directory | /workspace/9.gpio_stress_all/latest |
| Test location | /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2485447831 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 91063044 ps |
| CPU time | 0.74 seconds |
| Started | Jul 11 04:26:25 PM PDT 24 |
| Finished | Jul 11 04:26:27 PM PDT 24 |
| Peak memory | 195248 kb |
| Host | smart-0f2b6ef3-967f-4119-8a3a-b349439b0af9 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2485447831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2485447831 |
| Directory | /workspace/0.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1303581371 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 41684531 ps |
| CPU time | 0.92 seconds |
| Started | Jul 11 04:27:08 PM PDT 24 |
| Finished | Jul 11 04:27:11 PM PDT 24 |
| Peak memory | 197512 kb |
| Host | smart-71d751d2-990a-4d2d-a096-2511e719b750 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303581371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.1303581371 |
| Directory | /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3704492132 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 37402195 ps |
| CPU time | 0.94 seconds |
| Started | Jul 11 04:27:05 PM PDT 24 |
| Finished | Jul 11 04:27:07 PM PDT 24 |
| Peak memory | 196684 kb |
| Host | smart-f640bdbb-2450-47ef-81a5-f58acaa00933 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3704492132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3704492132 |
| Directory | /workspace/1.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1731477715 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 173962821 ps |
| CPU time | 1.11 seconds |
| Started | Jul 11 04:26:42 PM PDT 24 |
| Finished | Jul 11 04:26:45 PM PDT 24 |
| Peak memory | 196828 kb |
| Host | smart-87440443-22b0-420b-9a2d-16a98f946a6b |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731477715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.1731477715 |
| Directory | /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1289384819 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 81887001 ps |
| CPU time | 1.2 seconds |
| Started | Jul 11 04:26:36 PM PDT 24 |
| Finished | Jul 11 04:26:40 PM PDT 24 |
| Peak memory | 197204 kb |
| Host | smart-1d66a80e-db13-4749-9171-fdb83537eeb5 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1289384819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1289384819 |
| Directory | /workspace/10.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3735137559 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 93181418 ps |
| CPU time | 1.5 seconds |
| Started | Jul 11 04:27:57 PM PDT 24 |
| Finished | Jul 11 04:28:01 PM PDT 24 |
| Peak memory | 196316 kb |
| Host | smart-413c7b0e-d804-4565-80ca-6393657ec6ca |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735137559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3735137559 |
| Directory | /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3238689918 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 128854644 ps |
| CPU time | 1.11 seconds |
| Started | Jul 11 04:26:33 PM PDT 24 |
| Finished | Jul 11 04:26:36 PM PDT 24 |
| Peak memory | 196824 kb |
| Host | smart-2fb2d52e-9121-4b1d-9ac0-ab0432bfad7f |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3238689918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3238689918 |
| Directory | /workspace/11.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3655254119 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 40612110 ps |
| CPU time | 1.03 seconds |
| Started | Jul 11 04:27:08 PM PDT 24 |
| Finished | Jul 11 04:27:11 PM PDT 24 |
| Peak memory | 196776 kb |
| Host | smart-872d511a-486d-4f87-aff5-b9a05a537e9e |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655254119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3655254119 |
| Directory | /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3376144364 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 27226869 ps |
| CPU time | 0.82 seconds |
| Started | Jul 11 04:26:32 PM PDT 24 |
| Finished | Jul 11 04:26:36 PM PDT 24 |
| Peak memory | 194488 kb |
| Host | smart-57e5f81e-9062-453c-ab17-1ce5825ddc4f |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3376144364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3376144364 |
| Directory | /workspace/12.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4218121003 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 157619960 ps |
| CPU time | 1.21 seconds |
| Started | Jul 11 04:26:37 PM PDT 24 |
| Finished | Jul 11 04:26:41 PM PDT 24 |
| Peak memory | 197020 kb |
| Host | smart-8cb5856d-8a1e-4a43-a958-6e4eed27fd04 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218121003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown _en_cdc_prim.4218121003 |
| Directory | /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2859958618 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 49993719 ps |
| CPU time | 1.02 seconds |
| Started | Jul 11 04:26:45 PM PDT 24 |
| Finished | Jul 11 04:26:50 PM PDT 24 |
| Peak memory | 196080 kb |
| Host | smart-59a3e95f-8283-4e92-a9e0-f9df88a0968f |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2859958618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2859958618 |
| Directory | /workspace/13.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2188804075 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 67861800 ps |
| CPU time | 1.32 seconds |
| Started | Jul 11 04:28:21 PM PDT 24 |
| Finished | Jul 11 04:28:24 PM PDT 24 |
| Peak memory | 196248 kb |
| Host | smart-4b2245da-aaab-4406-b916-b15467ba5beb |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188804075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2188804075 |
| Directory | /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1838917631 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 162935753 ps |
| CPU time | 0.93 seconds |
| Started | Jul 11 04:27:31 PM PDT 24 |
| Finished | Jul 11 04:27:33 PM PDT 24 |
| Peak memory | 195860 kb |
| Host | smart-5f1a56bd-84e3-46c6-a71f-6bdb0296debf |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1838917631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1838917631 |
| Directory | /workspace/14.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2688281072 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 31498229 ps |
| CPU time | 0.76 seconds |
| Started | Jul 11 04:28:15 PM PDT 24 |
| Finished | Jul 11 04:28:18 PM PDT 24 |
| Peak memory | 195600 kb |
| Host | smart-d5d5c996-c786-4621-a58a-ca2cde8fc1e9 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688281072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2688281072 |
| Directory | /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.269889991 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 320514832 ps |
| CPU time | 1.42 seconds |
| Started | Jul 11 04:26:48 PM PDT 24 |
| Finished | Jul 11 04:26:53 PM PDT 24 |
| Peak memory | 190492 kb |
| Host | smart-bd9c95d8-f714-4e6f-bde3-a4900ab759dc |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=269889991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.269889991 |
| Directory | /workspace/15.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3294510889 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 329826938 ps |
| CPU time | 1.3 seconds |
| Started | Jul 11 04:26:42 PM PDT 24 |
| Finished | Jul 11 04:26:47 PM PDT 24 |
| Peak memory | 196836 kb |
| Host | smart-0514f76d-64a3-420e-8cba-2115482b92fb |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294510889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3294510889 |
| Directory | /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3801663253 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 276428091 ps |
| CPU time | 0.81 seconds |
| Started | Jul 11 04:27:29 PM PDT 24 |
| Finished | Jul 11 04:27:31 PM PDT 24 |
| Peak memory | 195644 kb |
| Host | smart-96c29bb4-2e18-48e1-bf96-8d9da7e21937 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3801663253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3801663253 |
| Directory | /workspace/16.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.12124148 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 60533653 ps |
| CPU time | 1.34 seconds |
| Started | Jul 11 04:26:48 PM PDT 24 |
| Finished | Jul 11 04:26:53 PM PDT 24 |
| Peak memory | 196220 kb |
| Host | smart-af2ef04b-4cc1-47f8-9cd7-3326b86a9046 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12124148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_e n_cdc_prim.12124148 |
| Directory | /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.16321213 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 78159490 ps |
| CPU time | 1.06 seconds |
| Started | Jul 11 04:26:35 PM PDT 24 |
| Finished | Jul 11 04:26:40 PM PDT 24 |
| Peak memory | 196104 kb |
| Host | smart-ac0c4b84-feff-4511-ac57-6be4caeb63cb |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=16321213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.16321213 |
| Directory | /workspace/17.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2185487127 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 37948007 ps |
| CPU time | 0.86 seconds |
| Started | Jul 11 04:26:42 PM PDT 24 |
| Finished | Jul 11 04:26:46 PM PDT 24 |
| Peak memory | 195700 kb |
| Host | smart-8389f6f5-0749-4842-aa33-dd188af7be34 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185487127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2185487127 |
| Directory | /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1804821283 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 77994815 ps |
| CPU time | 1.35 seconds |
| Started | Jul 11 04:26:42 PM PDT 24 |
| Finished | Jul 11 04:26:47 PM PDT 24 |
| Peak memory | 196820 kb |
| Host | smart-aa35fe03-4299-4575-8d2e-4d373f888907 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1804821283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1804821283 |
| Directory | /workspace/18.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2712456849 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 21953938 ps |
| CPU time | 0.75 seconds |
| Started | Jul 11 04:26:33 PM PDT 24 |
| Finished | Jul 11 04:26:36 PM PDT 24 |
| Peak memory | 196180 kb |
| Host | smart-020390ce-b898-4945-a106-780ee223ad78 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712456849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2712456849 |
| Directory | /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.203382584 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 131976068 ps |
| CPU time | 0.98 seconds |
| Started | Jul 11 04:27:07 PM PDT 24 |
| Finished | Jul 11 04:27:09 PM PDT 24 |
| Peak memory | 196792 kb |
| Host | smart-4bb083de-cd0e-4f51-b17e-6adaea15543c |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=203382584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.203382584 |
| Directory | /workspace/19.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3547193492 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 29968914 ps |
| CPU time | 1.03 seconds |
| Started | Jul 11 04:26:40 PM PDT 24 |
| Finished | Jul 11 04:26:44 PM PDT 24 |
| Peak memory | 196760 kb |
| Host | smart-fd621213-7771-460c-be75-ae39e6c7d910 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547193492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3547193492 |
| Directory | /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2986192995 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 47783953 ps |
| CPU time | 0.94 seconds |
| Started | Jul 11 04:27:34 PM PDT 24 |
| Finished | Jul 11 04:27:39 PM PDT 24 |
| Peak memory | 196832 kb |
| Host | smart-f325a254-f4ad-4612-8e73-63b0ea8ea48e |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2986192995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2986192995 |
| Directory | /workspace/2.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2711026991 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 549215617 ps |
| CPU time | 1.07 seconds |
| Started | Jul 11 04:27:59 PM PDT 24 |
| Finished | Jul 11 04:28:02 PM PDT 24 |
| Peak memory | 196776 kb |
| Host | smart-08a43439-101c-4eb8-9d0c-e23520addf5f |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711026991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.2711026991 |
| Directory | /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3568766343 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 329542876 ps |
| CPU time | 1.41 seconds |
| Started | Jul 11 04:27:32 PM PDT 24 |
| Finished | Jul 11 04:27:37 PM PDT 24 |
| Peak memory | 197028 kb |
| Host | smart-ba945131-ed4c-48d7-8c42-14bcaa7933b7 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3568766343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3568766343 |
| Directory | /workspace/20.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3467251795 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 38630785 ps |
| CPU time | 1.03 seconds |
| Started | Jul 11 04:27:05 PM PDT 24 |
| Finished | Jul 11 04:27:08 PM PDT 24 |
| Peak memory | 195856 kb |
| Host | smart-ff49ef85-8206-4fc1-af96-5d61b8c7272a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467251795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3467251795 |
| Directory | /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1708643566 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 123250167 ps |
| CPU time | 0.84 seconds |
| Started | Jul 11 04:28:21 PM PDT 24 |
| Finished | Jul 11 04:28:24 PM PDT 24 |
| Peak memory | 196412 kb |
| Host | smart-07e653d2-9542-42ea-8a2b-96c6d08811a4 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1708643566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1708643566 |
| Directory | /workspace/21.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.350176435 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 39603660 ps |
| CPU time | 1.18 seconds |
| Started | Jul 11 04:26:48 PM PDT 24 |
| Finished | Jul 11 04:26:53 PM PDT 24 |
| Peak memory | 195236 kb |
| Host | smart-98b45480-6e36-4bc8-8d73-9b8b52199c4a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350176435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.350176435 |
| Directory | /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.699450641 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 484678971 ps |
| CPU time | 1.2 seconds |
| Started | Jul 11 04:28:30 PM PDT 24 |
| Finished | Jul 11 04:28:33 PM PDT 24 |
| Peak memory | 198168 kb |
| Host | smart-ca9319a7-a85e-44a2-8bef-72a46e87d7a5 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=699450641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.699450641 |
| Directory | /workspace/22.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3689223153 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 176935465 ps |
| CPU time | 1.38 seconds |
| Started | Jul 11 04:26:45 PM PDT 24 |
| Finished | Jul 11 04:26:50 PM PDT 24 |
| Peak memory | 197316 kb |
| Host | smart-418631db-269e-4a37-88d9-5f3f7a6fe7af |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689223153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3689223153 |
| Directory | /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3691341003 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 500240894 ps |
| CPU time | 1.28 seconds |
| Started | Jul 11 04:27:55 PM PDT 24 |
| Finished | Jul 11 04:27:57 PM PDT 24 |
| Peak memory | 197148 kb |
| Host | smart-192bd9c7-904f-4ce6-accb-f2b48734e657 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3691341003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3691341003 |
| Directory | /workspace/23.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.56527922 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 61619819 ps |
| CPU time | 0.99 seconds |
| Started | Jul 11 04:26:59 PM PDT 24 |
| Finished | Jul 11 04:27:02 PM PDT 24 |
| Peak memory | 198224 kb |
| Host | smart-759f3e96-4d67-4398-846b-ba37825de816 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56527922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_e n_cdc_prim.56527922 |
| Directory | /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.941812996 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 23573612 ps |
| CPU time | 0.73 seconds |
| Started | Jul 11 04:27:32 PM PDT 24 |
| Finished | Jul 11 04:27:35 PM PDT 24 |
| Peak memory | 194624 kb |
| Host | smart-de554eae-c25b-4308-8d0d-7f389cefd489 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=941812996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.941812996 |
| Directory | /workspace/24.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1244140566 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 34201352 ps |
| CPU time | 0.92 seconds |
| Started | Jul 11 04:27:01 PM PDT 24 |
| Finished | Jul 11 04:27:03 PM PDT 24 |
| Peak memory | 196636 kb |
| Host | smart-1cec675d-02da-4708-b2b8-a3117378d41c |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244140566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1244140566 |
| Directory | /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3428640676 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 126837007 ps |
| CPU time | 1.12 seconds |
| Started | Jul 11 04:27:33 PM PDT 24 |
| Finished | Jul 11 04:27:37 PM PDT 24 |
| Peak memory | 197412 kb |
| Host | smart-11d0462a-6dc4-4d81-9a07-4f5ba5a1d2c1 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3428640676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3428640676 |
| Directory | /workspace/25.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.138535372 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 49667090 ps |
| CPU time | 0.86 seconds |
| Started | Jul 11 04:27:30 PM PDT 24 |
| Finished | Jul 11 04:27:32 PM PDT 24 |
| Peak memory | 196780 kb |
| Host | smart-5fde439e-427c-4efa-80bc-a4bcee35ab59 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138535372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.138535372 |
| Directory | /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2347769401 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 152567761 ps |
| CPU time | 1.35 seconds |
| Started | Jul 11 04:27:07 PM PDT 24 |
| Finished | Jul 11 04:27:11 PM PDT 24 |
| Peak memory | 193316 kb |
| Host | smart-314a3280-61f2-44d0-9876-53fa442b6ce7 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2347769401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2347769401 |
| Directory | /workspace/26.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.792892469 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 65231924 ps |
| CPU time | 1.16 seconds |
| Started | Jul 11 04:26:50 PM PDT 24 |
| Finished | Jul 11 04:26:54 PM PDT 24 |
| Peak memory | 196048 kb |
| Host | smart-3511c12d-d894-4e84-af18-6587899cf66c |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792892469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.792892469 |
| Directory | /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.723056319 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 118052710 ps |
| CPU time | 1.19 seconds |
| Started | Jul 11 04:27:36 PM PDT 24 |
| Finished | Jul 11 04:27:40 PM PDT 24 |
| Peak memory | 196852 kb |
| Host | smart-723b8e64-c051-4320-a910-18baed4eafd6 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=723056319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.723056319 |
| Directory | /workspace/27.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1865038037 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 55889179 ps |
| CPU time | 1.04 seconds |
| Started | Jul 11 04:26:48 PM PDT 24 |
| Finished | Jul 11 04:26:53 PM PDT 24 |
| Peak memory | 195396 kb |
| Host | smart-f9be09e1-01dd-4726-a392-f266c266351c |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865038037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1865038037 |
| Directory | /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.226578795 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 66391064 ps |
| CPU time | 1.01 seconds |
| Started | Jul 11 04:26:54 PM PDT 24 |
| Finished | Jul 11 04:26:56 PM PDT 24 |
| Peak memory | 195920 kb |
| Host | smart-f46bd83f-3d53-4852-b96c-3a92222dbdab |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=226578795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.226578795 |
| Directory | /workspace/28.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2209755022 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 488781846 ps |
| CPU time | 1.11 seconds |
| Started | Jul 11 04:26:54 PM PDT 24 |
| Finished | Jul 11 04:26:57 PM PDT 24 |
| Peak memory | 196840 kb |
| Host | smart-f4ff49a2-0afd-49f7-8fdc-e5f8cec224cb |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209755022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2209755022 |
| Directory | /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2229865680 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 388419512 ps |
| CPU time | 1.01 seconds |
| Started | Jul 11 04:26:50 PM PDT 24 |
| Finished | Jul 11 04:26:54 PM PDT 24 |
| Peak memory | 195520 kb |
| Host | smart-8de9934e-4efb-490c-83d1-61983d6b2a48 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2229865680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2229865680 |
| Directory | /workspace/29.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.845202499 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 54227960 ps |
| CPU time | 0.75 seconds |
| Started | Jul 11 04:26:48 PM PDT 24 |
| Finished | Jul 11 04:26:52 PM PDT 24 |
| Peak memory | 195400 kb |
| Host | smart-6fd686bc-4502-4003-b3f4-23b67d673451 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845202499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.845202499 |
| Directory | /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2327936787 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 105411575 ps |
| CPU time | 1.43 seconds |
| Started | Jul 11 04:26:42 PM PDT 24 |
| Finished | Jul 11 04:26:46 PM PDT 24 |
| Peak memory | 196836 kb |
| Host | smart-fded2204-257d-410e-bca9-c351ae23e19d |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2327936787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2327936787 |
| Directory | /workspace/3.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2388470934 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 41050727 ps |
| CPU time | 1.1 seconds |
| Started | Jul 11 04:28:14 PM PDT 24 |
| Finished | Jul 11 04:28:16 PM PDT 24 |
| Peak memory | 197016 kb |
| Host | smart-a787ccaf-52e6-47fc-927f-764a3e104cf2 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388470934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.2388470934 |
| Directory | /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2839784022 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 304328081 ps |
| CPU time | 1.24 seconds |
| Started | Jul 11 04:27:39 PM PDT 24 |
| Finished | Jul 11 04:27:43 PM PDT 24 |
| Peak memory | 198268 kb |
| Host | smart-101ed7b9-59be-4129-b18a-1e67d733fe6c |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2839784022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2839784022 |
| Directory | /workspace/30.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.984019169 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 159013180 ps |
| CPU time | 1.31 seconds |
| Started | Jul 11 04:27:07 PM PDT 24 |
| Finished | Jul 11 04:27:11 PM PDT 24 |
| Peak memory | 194676 kb |
| Host | smart-d30a7665-6d17-466e-8ee8-4cdf61406f8f |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984019169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.984019169 |
| Directory | /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1210419823 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 158976354 ps |
| CPU time | 1.15 seconds |
| Started | Jul 11 04:26:45 PM PDT 24 |
| Finished | Jul 11 04:26:49 PM PDT 24 |
| Peak memory | 197008 kb |
| Host | smart-cdac97fa-a410-41bc-bdff-c615e0d7fad7 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1210419823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1210419823 |
| Directory | /workspace/31.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1672517114 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 327517188 ps |
| CPU time | 1.4 seconds |
| Started | Jul 11 04:27:07 PM PDT 24 |
| Finished | Jul 11 04:27:11 PM PDT 24 |
| Peak memory | 193656 kb |
| Host | smart-54d644d6-6e73-4122-86c5-44bce18b5eea |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672517114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1672517114 |
| Directory | /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2297441272 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 180288194 ps |
| CPU time | 1.26 seconds |
| Started | Jul 11 04:26:58 PM PDT 24 |
| Finished | Jul 11 04:27:00 PM PDT 24 |
| Peak memory | 196864 kb |
| Host | smart-b705e86c-1f92-4251-ba29-e7082e1b20d0 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2297441272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2297441272 |
| Directory | /workspace/32.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2515259221 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 145609895 ps |
| CPU time | 1.22 seconds |
| Started | Jul 11 04:27:07 PM PDT 24 |
| Finished | Jul 11 04:27:11 PM PDT 24 |
| Peak memory | 194552 kb |
| Host | smart-bae6945c-c562-4ac9-a6e2-530c34e9abeb |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515259221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2515259221 |
| Directory | /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.606157243 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 53084628 ps |
| CPU time | 1.32 seconds |
| Started | Jul 11 04:26:50 PM PDT 24 |
| Finished | Jul 11 04:26:55 PM PDT 24 |
| Peak memory | 197968 kb |
| Host | smart-32414f66-2cc5-4d76-965a-85a39be14850 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=606157243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.606157243 |
| Directory | /workspace/33.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.779394229 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 93209574 ps |
| CPU time | 0.79 seconds |
| Started | Jul 11 04:27:02 PM PDT 24 |
| Finished | Jul 11 04:27:09 PM PDT 24 |
| Peak memory | 195760 kb |
| Host | smart-6da59711-fc6b-4741-af04-4f8bf64a9892 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779394229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.779394229 |
| Directory | /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1166931324 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 37798897 ps |
| CPU time | 1.21 seconds |
| Started | Jul 11 04:26:53 PM PDT 24 |
| Finished | Jul 11 04:26:55 PM PDT 24 |
| Peak memory | 197424 kb |
| Host | smart-d6d8d2dd-19b9-4a79-bbf4-d9af5adbbfac |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1166931324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1166931324 |
| Directory | /workspace/34.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2144195327 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 43982418 ps |
| CPU time | 1.12 seconds |
| Started | Jul 11 04:27:02 PM PDT 24 |
| Finished | Jul 11 04:27:05 PM PDT 24 |
| Peak memory | 198272 kb |
| Host | smart-d6b77643-b05e-464a-8bfb-bf2085355dac |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144195327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2144195327 |
| Directory | /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3883281877 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 40052412 ps |
| CPU time | 1.13 seconds |
| Started | Jul 11 04:26:56 PM PDT 24 |
| Finished | Jul 11 04:26:58 PM PDT 24 |
| Peak memory | 195956 kb |
| Host | smart-a580e90f-2dfa-47e7-b18d-3ec2bb9fea5f |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3883281877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3883281877 |
| Directory | /workspace/35.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3081320816 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 224117282 ps |
| CPU time | 1.39 seconds |
| Started | Jul 11 04:26:59 PM PDT 24 |
| Finished | Jul 11 04:27:02 PM PDT 24 |
| Peak memory | 197076 kb |
| Host | smart-dd93657f-d69a-46a8-bd5b-e5f8f76f6dd6 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081320816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3081320816 |
| Directory | /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1427722454 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 99337680 ps |
| CPU time | 1.42 seconds |
| Started | Jul 11 04:27:07 PM PDT 24 |
| Finished | Jul 11 04:27:11 PM PDT 24 |
| Peak memory | 194620 kb |
| Host | smart-2a5cef9c-dc66-47fd-9b64-1986c29252ad |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1427722454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1427722454 |
| Directory | /workspace/36.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.914818604 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 133108092 ps |
| CPU time | 1.17 seconds |
| Started | Jul 11 04:26:59 PM PDT 24 |
| Finished | Jul 11 04:27:02 PM PDT 24 |
| Peak memory | 196848 kb |
| Host | smart-c0c3928b-823d-46e4-9c15-77b352fb8a8e |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914818604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.914818604 |
| Directory | /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2068468056 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 55464260 ps |
| CPU time | 0.99 seconds |
| Started | Jul 11 04:28:25 PM PDT 24 |
| Finished | Jul 11 04:28:28 PM PDT 24 |
| Peak memory | 196836 kb |
| Host | smart-4844949d-1810-42dd-b633-715058d7e954 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2068468056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2068468056 |
| Directory | /workspace/37.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1630165163 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 74574104 ps |
| CPU time | 1.3 seconds |
| Started | Jul 11 04:28:03 PM PDT 24 |
| Finished | Jul 11 04:28:05 PM PDT 24 |
| Peak memory | 195868 kb |
| Host | smart-58453aec-ebf7-4088-b815-55db962d20b3 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630165163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1630165163 |
| Directory | /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.361652410 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 221430464 ps |
| CPU time | 0.79 seconds |
| Started | Jul 11 04:27:07 PM PDT 24 |
| Finished | Jul 11 04:27:11 PM PDT 24 |
| Peak memory | 192184 kb |
| Host | smart-8ef28cee-6684-4993-874e-7e1f42d0061c |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=361652410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.361652410 |
| Directory | /workspace/38.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1581404631 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 141335778 ps |
| CPU time | 1.11 seconds |
| Started | Jul 11 04:27:34 PM PDT 24 |
| Finished | Jul 11 04:27:39 PM PDT 24 |
| Peak memory | 195928 kb |
| Host | smart-7e8e186f-6bdc-4dbb-a881-061ffb3b77bb |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581404631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1581404631 |
| Directory | /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.420703931 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 80635515 ps |
| CPU time | 1.06 seconds |
| Started | Jul 11 04:27:00 PM PDT 24 |
| Finished | Jul 11 04:27:08 PM PDT 24 |
| Peak memory | 197004 kb |
| Host | smart-d266d8ff-b64b-4633-aa79-75ba298519d2 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=420703931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.420703931 |
| Directory | /workspace/39.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1394434022 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 24598267 ps |
| CPU time | 0.92 seconds |
| Started | Jul 11 04:26:55 PM PDT 24 |
| Finished | Jul 11 04:26:57 PM PDT 24 |
| Peak memory | 197552 kb |
| Host | smart-3feff765-7296-487d-9530-4a9abda1e2d4 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394434022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1394434022 |
| Directory | /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1752525590 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 45902811 ps |
| CPU time | 1.16 seconds |
| Started | Jul 11 04:27:31 PM PDT 24 |
| Finished | Jul 11 04:27:34 PM PDT 24 |
| Peak memory | 196740 kb |
| Host | smart-fc3fa8da-ac6b-4c5f-8e35-fd34614d94ae |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1752525590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1752525590 |
| Directory | /workspace/4.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3658804844 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 37006817 ps |
| CPU time | 1.11 seconds |
| Started | Jul 11 04:28:16 PM PDT 24 |
| Finished | Jul 11 04:28:20 PM PDT 24 |
| Peak memory | 196692 kb |
| Host | smart-6ec5f5b5-16e1-4048-822a-fccc5169078c |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658804844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.3658804844 |
| Directory | /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1987301137 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 147133189 ps |
| CPU time | 1.07 seconds |
| Started | Jul 11 04:27:01 PM PDT 24 |
| Finished | Jul 11 04:27:04 PM PDT 24 |
| Peak memory | 198280 kb |
| Host | smart-4da120f5-e87d-4d6e-9495-9a3b3a46188d |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1987301137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1987301137 |
| Directory | /workspace/40.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3860603432 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 93581967 ps |
| CPU time | 1.3 seconds |
| Started | Jul 11 04:27:03 PM PDT 24 |
| Finished | Jul 11 04:27:06 PM PDT 24 |
| Peak memory | 196984 kb |
| Host | smart-4fca0ee0-b298-4b08-9a21-eb7fec3975ae |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860603432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3860603432 |
| Directory | /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1717127450 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 98697721 ps |
| CPU time | 1.5 seconds |
| Started | Jul 11 04:27:36 PM PDT 24 |
| Finished | Jul 11 04:27:41 PM PDT 24 |
| Peak memory | 196996 kb |
| Host | smart-c6fb61a2-8662-45fd-9942-4963b6c71ddb |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1717127450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1717127450 |
| Directory | /workspace/41.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1236583906 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 54568235 ps |
| CPU time | 1.33 seconds |
| Started | Jul 11 04:26:59 PM PDT 24 |
| Finished | Jul 11 04:27:02 PM PDT 24 |
| Peak memory | 197012 kb |
| Host | smart-8ee9daf7-efee-468a-8bb0-e8fce8545859 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236583906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1236583906 |
| Directory | /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3047599490 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 97227153 ps |
| CPU time | 1.41 seconds |
| Started | Jul 11 04:27:02 PM PDT 24 |
| Finished | Jul 11 04:27:04 PM PDT 24 |
| Peak memory | 196880 kb |
| Host | smart-0a21c080-d2d7-40cb-89f3-dd7908dd67a9 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3047599490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3047599490 |
| Directory | /workspace/42.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4085426172 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 85733514 ps |
| CPU time | 1.11 seconds |
| Started | Jul 11 04:27:05 PM PDT 24 |
| Finished | Jul 11 04:27:08 PM PDT 24 |
| Peak memory | 198236 kb |
| Host | smart-b65b8fc5-9d24-4f3f-8fee-ba4ae45a3890 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085426172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown _en_cdc_prim.4085426172 |
| Directory | /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1022403218 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 813180535 ps |
| CPU time | 1.3 seconds |
| Started | Jul 11 04:27:07 PM PDT 24 |
| Finished | Jul 11 04:27:09 PM PDT 24 |
| Peak memory | 191932 kb |
| Host | smart-086a4e09-5db4-4c17-9db7-6ff9ecab6d66 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1022403218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1022403218 |
| Directory | /workspace/43.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3019265804 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 40135166 ps |
| CPU time | 1.03 seconds |
| Started | Jul 11 04:27:30 PM PDT 24 |
| Finished | Jul 11 04:27:33 PM PDT 24 |
| Peak memory | 197940 kb |
| Host | smart-39ea4f89-d162-432b-a5d6-ade3875b1df3 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019265804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3019265804 |
| Directory | /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2899421053 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 63444193 ps |
| CPU time | 1.1 seconds |
| Started | Jul 11 04:27:02 PM PDT 24 |
| Finished | Jul 11 04:27:05 PM PDT 24 |
| Peak memory | 197744 kb |
| Host | smart-b59e4817-d784-4d15-a5c2-3154a312c055 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2899421053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2899421053 |
| Directory | /workspace/44.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.936657197 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 38228472 ps |
| CPU time | 1.01 seconds |
| Started | Jul 11 04:27:32 PM PDT 24 |
| Finished | Jul 11 04:27:34 PM PDT 24 |
| Peak memory | 198252 kb |
| Host | smart-eff03e71-b711-487e-aa7e-d8a2a0c3f34f |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936657197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.936657197 |
| Directory | /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2476054544 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 122383890 ps |
| CPU time | 1.07 seconds |
| Started | Jul 11 04:27:08 PM PDT 24 |
| Finished | Jul 11 04:27:11 PM PDT 24 |
| Peak memory | 191940 kb |
| Host | smart-6bba04d0-9aa5-46de-a69a-c45409032a37 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2476054544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2476054544 |
| Directory | /workspace/45.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3476475904 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 117989053 ps |
| CPU time | 1.04 seconds |
| Started | Jul 11 04:27:00 PM PDT 24 |
| Finished | Jul 11 04:27:03 PM PDT 24 |
| Peak memory | 196704 kb |
| Host | smart-387a0e18-8cf1-4b09-8030-bc31d278038a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476475904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3476475904 |
| Directory | /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1282977811 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 58559602 ps |
| CPU time | 1.05 seconds |
| Started | Jul 11 04:27:05 PM PDT 24 |
| Finished | Jul 11 04:27:08 PM PDT 24 |
| Peak memory | 195928 kb |
| Host | smart-76df0dec-37fb-4074-bb51-fe6d972471e4 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1282977811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1282977811 |
| Directory | /workspace/46.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.152565245 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 78721839 ps |
| CPU time | 1.09 seconds |
| Started | Jul 11 04:27:02 PM PDT 24 |
| Finished | Jul 11 04:27:04 PM PDT 24 |
| Peak memory | 196788 kb |
| Host | smart-90c0fb66-8421-4aba-9549-99c72ca6b5e8 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152565245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.152565245 |
| Directory | /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.326320682 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 420507788 ps |
| CPU time | 1.21 seconds |
| Started | Jul 11 04:27:00 PM PDT 24 |
| Finished | Jul 11 04:27:03 PM PDT 24 |
| Peak memory | 198264 kb |
| Host | smart-dfc32874-5708-4298-b614-135d5edea7a0 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=326320682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.326320682 |
| Directory | /workspace/47.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2087168041 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 119648509 ps |
| CPU time | 0.98 seconds |
| Started | Jul 11 04:27:03 PM PDT 24 |
| Finished | Jul 11 04:27:06 PM PDT 24 |
| Peak memory | 195816 kb |
| Host | smart-54b75c2e-d835-4385-8b89-c2be99eb5c97 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087168041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2087168041 |
| Directory | /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1845000839 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 76200497 ps |
| CPU time | 0.99 seconds |
| Started | Jul 11 04:27:31 PM PDT 24 |
| Finished | Jul 11 04:27:33 PM PDT 24 |
| Peak memory | 196544 kb |
| Host | smart-b7d1529d-f69d-41ed-a8f0-54eff02d2242 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1845000839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1845000839 |
| Directory | /workspace/48.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.558004054 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 174060388 ps |
| CPU time | 1.28 seconds |
| Started | Jul 11 04:27:32 PM PDT 24 |
| Finished | Jul 11 04:27:36 PM PDT 24 |
| Peak memory | 196856 kb |
| Host | smart-7ecbd1dc-8116-4483-ab95-c4d947ac06e3 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558004054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.558004054 |
| Directory | /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2822986253 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 35273344 ps |
| CPU time | 0.96 seconds |
| Started | Jul 11 04:27:03 PM PDT 24 |
| Finished | Jul 11 04:27:05 PM PDT 24 |
| Peak memory | 196060 kb |
| Host | smart-309cd477-bec2-48bb-a7e7-ee3c7ddae01e |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2822986253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2822986253 |
| Directory | /workspace/49.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4127554425 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 111007688 ps |
| CPU time | 1.13 seconds |
| Started | Jul 11 04:27:03 PM PDT 24 |
| Finished | Jul 11 04:27:06 PM PDT 24 |
| Peak memory | 197468 kb |
| Host | smart-d2dce324-b875-44b9-adbc-ccd4b925f9da |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127554425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown _en_cdc_prim.4127554425 |
| Directory | /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.543763167 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 48835740 ps |
| CPU time | 0.94 seconds |
| Started | Jul 11 04:27:33 PM PDT 24 |
| Finished | Jul 11 04:27:38 PM PDT 24 |
| Peak memory | 197520 kb |
| Host | smart-6c00c2f4-f595-45a6-be73-f30ae52e4701 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=543763167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.543763167 |
| Directory | /workspace/5.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1166294877 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 163718472 ps |
| CPU time | 0.98 seconds |
| Started | Jul 11 04:27:27 PM PDT 24 |
| Finished | Jul 11 04:27:30 PM PDT 24 |
| Peak memory | 196460 kb |
| Host | smart-6662c4d8-801a-4181-a7c7-8ab0ad969615 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166294877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.1166294877 |
| Directory | /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2932273347 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 31512779 ps |
| CPU time | 0.99 seconds |
| Started | Jul 11 04:28:09 PM PDT 24 |
| Finished | Jul 11 04:28:12 PM PDT 24 |
| Peak memory | 197428 kb |
| Host | smart-50292661-0f31-47a0-90ae-f614aaee1d62 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2932273347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2932273347 |
| Directory | /workspace/6.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4021054869 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 29665364 ps |
| CPU time | 1.02 seconds |
| Started | Jul 11 04:26:31 PM PDT 24 |
| Finished | Jul 11 04:26:35 PM PDT 24 |
| Peak memory | 194628 kb |
| Host | smart-987801d1-b690-48b0-b346-f9ad1d06eecc |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021054869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.4021054869 |
| Directory | /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.4151137009 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 240458686 ps |
| CPU time | 1.33 seconds |
| Started | Jul 11 04:26:42 PM PDT 24 |
| Finished | Jul 11 04:26:45 PM PDT 24 |
| Peak memory | 196936 kb |
| Host | smart-b561917e-c3b4-400c-9560-f1ce65f9270b |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4151137009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.4151137009 |
| Directory | /workspace/7.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1471273502 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 48576864 ps |
| CPU time | 1.28 seconds |
| Started | Jul 11 04:28:21 PM PDT 24 |
| Finished | Jul 11 04:28:24 PM PDT 24 |
| Peak memory | 197116 kb |
| Host | smart-871110a3-9d29-4c75-a7e3-15fce0a32c11 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471273502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.1471273502 |
| Directory | /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3890768779 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 89984830 ps |
| CPU time | 1.64 seconds |
| Started | Jul 11 04:26:42 PM PDT 24 |
| Finished | Jul 11 04:26:46 PM PDT 24 |
| Peak memory | 196916 kb |
| Host | smart-e5783621-fd6b-4c50-a4e9-f14fdd900234 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3890768779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3890768779 |
| Directory | /workspace/8.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2128003559 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 44614687 ps |
| CPU time | 1 seconds |
| Started | Jul 11 04:26:48 PM PDT 24 |
| Finished | Jul 11 04:26:53 PM PDT 24 |
| Peak memory | 194096 kb |
| Host | smart-d0e245af-2f4a-4440-8e90-3f51a69e496b |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128003559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.2128003559 |
| Directory | /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2655214649 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 94300365 ps |
| CPU time | 1.11 seconds |
| Started | Jul 11 04:27:28 PM PDT 24 |
| Finished | Jul 11 04:27:30 PM PDT 24 |
| Peak memory | 196788 kb |
| Host | smart-f06e284d-1286-4253-ba77-968378c31bc4 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2655214649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2655214649 |
| Directory | /workspace/9.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2736706034 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 241706720 ps |
| CPU time | 1.13 seconds |
| Started | Jul 11 04:27:37 PM PDT 24 |
| Finished | Jul 11 04:27:41 PM PDT 24 |
| Peak memory | 198248 kb |
| Host | smart-b643f2d9-d319-42dd-995f-58f1410e84f0 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736706034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.2736706034 |
| Directory | /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
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