Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3778682	1			T21	1		T22	1		T23	40740
all_pins[1]	3778682	1			T21	1		T22	1		T23	40740
all_pins[2]	3778682	1			T21	1		T22	1		T23	40740
all_pins[3]	3778682	1			T21	1		T22	1		T23	40740
all_pins[4]	3778682	1			T21	1		T22	1		T23	40740
all_pins[5]	3778682	1			T21	1		T22	1		T23	40740
all_pins[6]	3778682	1			T21	1		T22	1		T23	40740
all_pins[7]	3778682	1			T21	1		T22	1		T23	40740
all_pins[8]	3778682	1			T21	1		T22	1		T23	40740
all_pins[9]	3778682	1			T21	1		T22	1		T23	40740
all_pins[10]	3778682	1			T21	1		T22	1		T23	40740
all_pins[11]	3778682	1			T21	1		T22	1		T23	40740
all_pins[12]	3778682	1			T21	1		T22	1		T23	40740
all_pins[13]	3778682	1			T21	1		T22	1		T23	40740
all_pins[14]	3778682	1			T21	1		T22	1		T23	40740
all_pins[15]	3778682	1			T21	1		T22	1		T23	40740
all_pins[16]	3778682	1			T21	1		T22	1		T23	40740
all_pins[17]	3778682	1			T21	1		T22	1		T23	40740
all_pins[18]	3778682	1			T21	1		T22	1		T23	40740
all_pins[19]	3778682	1			T21	1		T22	1		T23	40740
all_pins[20]	3778682	1			T21	1		T22	1		T23	40740
all_pins[21]	3778682	1			T21	1		T22	1		T23	40740
all_pins[22]	3778682	1			T21	1		T22	1		T23	40740
all_pins[23]	3778682	1			T21	1		T22	1		T23	40740
all_pins[24]	3778682	1			T21	1		T22	1		T23	40740
all_pins[25]	3778682	1			T21	1		T22	1		T23	40740
all_pins[26]	3778682	1			T21	1		T22	1		T23	40740
all_pins[27]	3778682	1			T21	1		T22	1		T23	40740
all_pins[28]	3778682	1			T21	1		T22	1		T23	40740
all_pins[29]	3778682	1			T21	1		T22	1		T23	40740
all_pins[30]	3778682	1			T21	1		T22	1		T23	40740
all_pins[31]	3778682	1			T21	1		T22	1		T23	40740

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	75147533	1			T21	32		T22	32		T23	816965
values[0x1]	45770291	1			T23	486715		T24	154		T26	560953
transitions[0x0=>0x1]	27445504	1			T23	294034		T24	105		T26	335528
transitions[0x1=>0x0]	27445359	1			T23	294033		T24	105		T26	335527

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2348726	1			T21	1		T22	1		T23	25285
all_pins[0]	values[0x1]	1429956	1			T23	15455		T24	12		T26	18034
all_pins[0]	transitions[0x0=>0x1]	884351	1			T23	9289		T24	4		T26	11056
all_pins[0]	transitions[0x1=>0x0]	882639	1			T23	9243		T24	2		T26	10668
all_pins[1]	values[0x0]	2350225	1			T21	1		T22	1		T23	25747
all_pins[1]	values[0x1]	1428457	1			T23	14993		T24	8		T26	17976
all_pins[1]	transitions[0x0=>0x1]	853869	1			T23	9171		T26	10441		T27	15
all_pins[1]	transitions[0x1=>0x0]	855368	1			T23	9633		T24	4		T26	10499
all_pins[2]	values[0x0]	2344074	1			T21	1		T22	1		T23	25443
all_pins[2]	values[0x1]	1434608	1			T23	15297		T24	1		T26	17235
all_pins[2]	transitions[0x0=>0x1]	858363	1			T23	9291		T26	10383		T27	13
all_pins[2]	transitions[0x1=>0x0]	852212	1			T23	8987		T24	7		T26	11124
all_pins[3]	values[0x0]	2342814	1			T21	1		T22	1		T23	25351
all_pins[3]	values[0x1]	1435868	1			T23	15389		T26	17767		T27	30
all_pins[3]	transitions[0x0=>0x1]	858666	1			T23	9317		T26	10668		T27	15
all_pins[3]	transitions[0x1=>0x0]	857406	1			T23	9225		T24	1		T26	10136
all_pins[4]	values[0x0]	2350489	1			T21	1		T22	1		T23	26886
all_pins[4]	values[0x1]	1428193	1			T23	13854		T24	3		T26	17982
all_pins[4]	transitions[0x0=>0x1]	853584	1			T23	8135		T24	3		T26	10621
all_pins[4]	transitions[0x1=>0x0]	861259	1			T23	9670		T26	10406		T27	19
all_pins[5]	values[0x0]	2352348	1			T21	1		T22	1		T23	25655
all_pins[5]	values[0x1]	1426334	1			T23	15085		T24	9		T26	18251
all_pins[5]	transitions[0x0=>0x1]	853807	1			T23	9659		T24	9		T26	10689
all_pins[5]	transitions[0x1=>0x0]	855666	1			T23	8428		T24	3		T26	10420
all_pins[6]	values[0x0]	2349659	1			T21	1		T22	1		T23	26142
all_pins[6]	values[0x1]	1429023	1			T23	14598		T24	1		T26	17850
all_pins[6]	transitions[0x0=>0x1]	855832	1			T23	8988		T24	1		T26	10519
all_pins[6]	transitions[0x1=>0x0]	853143	1			T23	9475		T24	9		T26	10920
all_pins[7]	values[0x0]	2348670	1			T21	1		T22	1		T23	25715
all_pins[7]	values[0x1]	1430012	1			T23	15025		T24	2		T26	17089
all_pins[7]	transitions[0x0=>0x1]	856226	1			T23	9171		T24	2		T26	10072
all_pins[7]	transitions[0x1=>0x0]	855237	1			T23	8744		T24	1		T26	10833
all_pins[8]	values[0x0]	2348476	1			T21	1		T22	1		T23	25331
all_pins[8]	values[0x1]	1430206	1			T23	15409		T24	13		T26	17326
all_pins[8]	transitions[0x0=>0x1]	856560	1			T23	8963		T24	12		T26	10273
all_pins[8]	transitions[0x1=>0x0]	856366	1			T23	8579		T24	1		T26	10036
all_pins[9]	values[0x0]	2348608	1			T21	1		T22	1		T23	25508
all_pins[9]	values[0x1]	1430074	1			T23	15232		T24	1		T26	17795
all_pins[9]	transitions[0x0=>0x1]	856385	1			T23	9331		T26	10357		T27	10
all_pins[9]	transitions[0x1=>0x0]	856517	1			T23	9508		T24	12		T26	9888
all_pins[10]	values[0x0]	2346976	1			T21	1		T22	1		T23	24826
all_pins[10]	values[0x1]	1431706	1			T23	15914		T24	2		T26	17463
all_pins[10]	transitions[0x0=>0x1]	857181	1			T23	9776		T24	2		T26	10206
all_pins[10]	transitions[0x1=>0x0]	855549	1			T23	9094		T24	1		T26	10538
all_pins[11]	values[0x0]	2350376	1			T21	1		T22	1		T23	26339
all_pins[11]	values[0x1]	1428306	1			T23	14401		T26	16975		T27	23
all_pins[11]	transitions[0x0=>0x1]	855300	1			T23	8372		T26	10210		T27	10
all_pins[11]	transitions[0x1=>0x0]	858700	1			T23	9885		T24	2		T26	10698
all_pins[12]	values[0x0]	2350796	1			T21	1		T22	1		T23	25339
all_pins[12]	values[0x1]	1427886	1			T23	15401		T24	2		T26	17673
all_pins[12]	transitions[0x0=>0x1]	857089	1			T23	9505		T24	2		T26	11029
all_pins[12]	transitions[0x1=>0x0]	857509	1			T23	8505		T26	10331		T27	9
all_pins[13]	values[0x0]	2352098	1			T21	1		T22	1		T23	25142
all_pins[13]	values[0x1]	1426584	1			T23	15598		T24	10		T26	18152
all_pins[13]	transitions[0x0=>0x1]	854969	1			T23	9269		T24	8		T26	10706
all_pins[13]	transitions[0x1=>0x0]	856271	1			T23	9072		T26	10227		T27	15
all_pins[14]	values[0x0]	2347396	1			T21	1		T22	1		T23	25267
all_pins[14]	values[0x1]	1431286	1			T23	15473		T24	3		T26	17241
all_pins[14]	transitions[0x0=>0x1]	858931	1			T23	9113		T24	1		T26	10142
all_pins[14]	transitions[0x1=>0x0]	854229	1			T23	9238		T24	8		T26	11053
all_pins[15]	values[0x0]	2346678	1			T21	1		T22	1		T23	25302
all_pins[15]	values[0x1]	1432004	1			T23	15438		T24	5		T26	16991
all_pins[15]	transitions[0x0=>0x1]	856770	1			T23	9220		T24	2		T26	10569
all_pins[15]	transitions[0x1=>0x0]	856052	1			T23	9255		T26	10819		T27	8
all_pins[16]	values[0x0]	2349608	1			T21	1		T22	1		T23	25576
all_pins[16]	values[0x1]	1429074	1			T23	15164		T24	10		T26	17546
all_pins[16]	transitions[0x0=>0x1]	857241	1			T23	9110		T24	5		T26	10776
all_pins[16]	transitions[0x1=>0x0]	860171	1			T23	9384		T26	10221		T27	14
all_pins[17]	values[0x0]	2345166	1			T21	1		T22	1		T23	25211
all_pins[17]	values[0x1]	1433516	1			T23	15529		T24	3		T26	17120
all_pins[17]	transitions[0x0=>0x1]	861970	1			T23	9476		T26	10338		T27	18
all_pins[17]	transitions[0x1=>0x0]	857528	1			T23	9111		T24	7		T26	10764
all_pins[18]	values[0x0]	2344592	1			T21	1		T22	1		T23	25301
all_pins[18]	values[0x1]	1434090	1			T23	15439		T24	3		T26	17547
all_pins[18]	transitions[0x0=>0x1]	860906	1			T23	9150		T24	1		T26	10932
all_pins[18]	transitions[0x1=>0x0]	860332	1			T23	9240		T24	1		T26	10505
all_pins[19]	values[0x0]	2344326	1			T21	1		T22	1		T23	25237
all_pins[19]	values[0x1]	1434356	1			T23	15503		T24	5		T26	17745
all_pins[19]	transitions[0x0=>0x1]	857318	1			T23	9269		T24	3		T26	10562
all_pins[19]	transitions[0x1=>0x0]	857052	1			T23	9205		T24	1		T26	10364
all_pins[20]	values[0x0]	2349027	1			T21	1		T22	1		T23	25414
all_pins[20]	values[0x1]	1429655	1			T23	15326		T24	13		T26	17333
all_pins[20]	transitions[0x0=>0x1]	855902	1			T23	9099		T24	12		T26	9944
all_pins[20]	transitions[0x1=>0x0]	860603	1			T23	9276		T24	4		T26	10356
all_pins[21]	values[0x0]	2352713	1			T21	1		T22	1		T23	25873
all_pins[21]	values[0x1]	1425969	1			T23	14867		T24	1		T26	16830
all_pins[21]	transitions[0x0=>0x1]	854116	1			T23	8777		T26	9899		T27	10
all_pins[21]	transitions[0x1=>0x0]	857802	1			T23	9236		T24	12		T26	10402
all_pins[22]	values[0x0]	2350143	1			T21	1		T22	1		T23	25462
all_pins[22]	values[0x1]	1428539	1			T23	15278		T24	7		T26	17394
all_pins[22]	transitions[0x0=>0x1]	855908	1			T23	9138		T24	7		T26	10542
all_pins[22]	transitions[0x1=>0x0]	853338	1			T23	8727		T24	1		T26	9978
all_pins[23]	values[0x0]	2344233	1			T21	1		T22	1		T23	25646
all_pins[23]	values[0x1]	1434449	1			T23	15094		T24	3		T26	16649
all_pins[23]	transitions[0x0=>0x1]	859601	1			T23	8980		T24	3		T26	10171
all_pins[23]	transitions[0x1=>0x0]	853691	1			T23	9164		T24	7		T26	10916
all_pins[24]	values[0x0]	2347226	1			T21	1		T22	1		T23	25626
all_pins[24]	values[0x1]	1431456	1			T23	15114		T24	2		T26	17886
all_pins[24]	transitions[0x0=>0x1]	855653	1			T23	9084		T24	2		T26	11015
all_pins[24]	transitions[0x1=>0x0]	858646	1			T23	9064		T24	3		T26	9778
all_pins[25]	values[0x0]	2343628	1			T21	1		T22	1		T23	25480
all_pins[25]	values[0x1]	1435054	1			T23	15260		T24	12		T26	17566
all_pins[25]	transitions[0x0=>0x1]	857127	1			T23	9452		T24	10		T26	10438
all_pins[25]	transitions[0x1=>0x0]	853529	1			T23	9306		T26	10758		T27	15
all_pins[26]	values[0x0]	2348107	1			T21	1		T22	1		T23	25584
all_pins[26]	values[0x1]	1430575	1			T23	15156		T24	2		T26	17854
all_pins[26]	transitions[0x0=>0x1]	856608	1			T23	9276		T26	10798		T27	26
all_pins[26]	transitions[0x1=>0x0]	861087	1			T23	9380		T24	10		T26	10510
all_pins[27]	values[0x0]	2349223	1			T21	1		T22	1		T23	25155
all_pins[27]	values[0x1]	1429459	1			T23	15585		T24	2		T26	17220
all_pins[27]	transitions[0x0=>0x1]	857316	1			T23	9527		T26	10048		T27	6
all_pins[27]	transitions[0x1=>0x0]	858432	1			T23	9098		T26	10682		T27	13
all_pins[28]	values[0x0]	2349384	1			T21	1		T22	1		T23	26124
all_pins[28]	values[0x1]	1429298	1			T23	14616		T24	2		T26	17488
all_pins[28]	transitions[0x0=>0x1]	856576	1			T23	8846		T24	1		T26	10435
all_pins[28]	transitions[0x1=>0x0]	856737	1			T23	9815		T24	1		T26	10167
all_pins[29]	values[0x0]	2346969	1			T21	1		T22	1		T23	25221
all_pins[29]	values[0x1]	1431713	1			T23	15519		T24	6		T26	17941
all_pins[29]	transitions[0x0=>0x1]	859738	1			T23	9736		T24	5		T26	10693
all_pins[29]	transitions[0x1=>0x0]	857323	1			T23	8833		T24	1		T26	10240
all_pins[30]	values[0x0]	2354486	1			T21	1		T22	1		T23	25447
all_pins[30]	values[0x1]	1424196	1			T23	15293		T24	1		T26	17387
all_pins[30]	transitions[0x0=>0x1]	853135	1			T23	9252		T24	1		T26	10237
all_pins[30]	transitions[0x1=>0x0]	860652	1			T23	9478		T24	6		T26	10791
all_pins[31]	values[0x0]	2350293	1			T21	1		T22	1		T23	25330
all_pins[31]	values[0x1]	1428389	1			T23	15410		T24	10		T26	17647
all_pins[31]	transitions[0x0=>0x1]	858506	1			T23	9292		T24	9		T26	10759
all_pins[31]	transitions[0x1=>0x0]	854313	1			T23	9175		T26	10499		T27	10