Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[1]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[2]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[3]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[4]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[5]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[6]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[7]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[8]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[9]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[10]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[11]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[12]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[13]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[14]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[15]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[16]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[17]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[18]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[19]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[20]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[21]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[22]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[23]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[24]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[25]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[26]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[27]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[28]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[29]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[30]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[31]	12539864	1			T21	64		T22	191		T23	113830

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238565371

1

T21

1581

T22

4841

T23

120367

auto[1]

162710277

1

T21

467

T22

1271

T23

243888

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

322837273

1

T21

1744

T22

4429

T23

275203

auto[1]

78438375

1

T21

304

T22

1683

T23

890522

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299743189

1

T21

1245

T22

3202

T23

250305

auto[1]

101532459

1

T21

803

T22

2910

T23

113950

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4658962	1			T21	22		T22	60		T23	22361
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3472114	1			T21	12		T22	8		T23	41477
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1235778	1			T21	11		T22	19		T23	14529
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1560700	1			T21	18		T22	64		T23	1262
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	392603	1			T21	1		T22	10		T23	20157
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1219707	1			T22	30		T23	14044		T24	3
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4660629	1			T21	10		T22	51		T23	22403
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3477662	1			T21	10		T22	6		T23	41810
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1235994	1			T21	7		T22	46		T23	14083
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1552177	1			T21	28		T22	44		T23	1322
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	392649	1			T21	5		T22	7		T23	20327
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1220753	1			T21	4		T22	37		T23	13885
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4658727	1			T21	16		T22	62		T23	22326
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3472865	1			T21	9		T22	9		T23	42240
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1233059	1			T21	2		T22	27		T23	14055
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1555554	1			T21	23		T22	55		T23	1266
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	394063	1			T21	6		T22	5		T23	20032
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1225596	1			T21	8		T22	33		T23	13911
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4670722	1			T21	21		T22	90		T23	21945
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3462638	1			T21	3		T22	13		T23	42545
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1228663	1			T22	10		T23	14048		T25	185
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1562204	1			T21	23		T22	64		T23	1412
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	396036	1			T21	6		T22	2		T23	19844
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1219601	1			T21	11		T22	12		T23	14036
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4662991	1			T21	20		T22	79		T23	22149
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3468860	1			T21	6		T22	3		T23	41779
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1233741	1			T21	6		T22	6		T23	13778
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1555632	1			T21	28		T22	70		T23	1422
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	393552	1			T21	4		T22	10		T23	20854
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1225088	1			T22	23		T23	13848		T24	4
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4653544	1			T21	10		T22	107		T23	22413
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3475439	1			T21	11		T22	9		T23	42140
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1236520	1			T21	8		T22	24		T23	14012
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1557433	1			T21	25		T22	48		T23	1263
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	394157	1			T21	3		T22	1		T23	19839
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1222771	1			T21	7		T22	2		T23	14163
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4662403	1			T21	15		T22	56		T23	22336
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3473323	1			T21	5		T22	4		T23	41974
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1234963	1			T21	7		T22	40		T23	13897
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1555058	1			T21	31		T22	56		T23	1300
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	394575	1			T21	6		T22	5		T23	20255
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1219542	1			T22	30		T23	14068		T24	7
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4662924	1			T21	38		T22	78		T23	22292
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3464837	1			T21	3		T22	8		T23	41957
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1236673	1			T21	3		T22	14		T23	14003
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1557221	1			T21	17		T22	74		T23	1421
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	395186	1			T21	3		T22	5		T23	20199
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1223023	1			T22	12		T23	13958		T24	7
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4670668	1			T21	31		T22	77		T23	22068
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3468636	1			T21	13		T22	13		T23	42080
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1233031	1			T21	11		T22	23		T23	13388
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1554103	1			T21	9		T22	44		T23	1387
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	395297	1			T22	6		T23	20791		T24	14
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1218129	1			T22	28		T23	14116		T24	2
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4655374	1			T21	20		T22	72		T23	22242
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3471715	1			T21	7		T22	5		T23	42045
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1231798	1			T22	12		T23	14161		T25	160
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1559953	1			T21	28		T22	72		T23	1384
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	394452	1			T21	6		T22	6		T23	20315
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1226572	1			T21	3		T22	24		T23	13683
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4664811	1			T21	29		T22	72		T23	22267
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3466672	1			T21	11		T22	9		T23	42326
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1236044	1			T21	3		T22	41		T23	13856
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1553661	1			T21	13		T22	48		T23	1304
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	393098	1			T22	3		T23	20422		T24	4
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1225578	1			T21	8		T22	18		T23	13655
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4676630	1			T21	33		T22	55		T23	22222
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3460226	1			T21	11		T22	4		T23	41807
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1235904	1			T21	11		T22	27		T23	14238
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1555001	1			T21	8		T22	65		T23	1353
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	391809	1			T21	1		T22	9		T23	20422
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1220294	1			T22	31		T23	13788		T24	3
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4668811	1			T21	19		T22	68		T23	22404
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3473555	1			T21	9		T22	6		T23	42023
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1232525	1			T21	12		T22	29		T23	13874
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1554453	1			T21	12		T22	62		T23	1332
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	392663	1			T21	3		T22	10		T23	20461
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1217857	1			T21	9		T22	16		T23	13736
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4663683	1			T21	35		T22	71		T23	22459
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3473272	1			T21	5		T22	8		T23	42285
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1229659	1			T21	13		T22	34		T23	13782
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1554251	1			T21	11		T22	48		T23	1261
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	393248	1			T22	3		T23	20130		T24	8
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1225751	1			T22	27		T23	13913		T24	12
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4667806	1			T21	34		T22	40		T23	22164
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3461685	1			T21	3		T22	4		T23	42091
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1232712	1			T21	15		T22	12		T23	13906
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1553665	1			T21	7		T22	99		T23	1303
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	393883	1			T21	1		T22	10		T23	20451
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1230113	1			T21	4		T22	26		T23	13915
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4667528	1			T21	27		T22	64		T23	22328
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3468832	1			T21	6		T22	5		T23	41759
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1234277	1			T21	4		T22	32		T23	14157
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1550984	1			T21	21		T22	50		T23	1310
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	393193	1			T21	2		T22	7		T23	20499
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1225050	1			T21	4		T22	33		T23	13777
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4673784	1			T21	29		T22	39		T23	22329
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3466005	1			T21	7		T22	8		T23	41796
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1221749	1			T22	22		T23	13948		T24	1
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1563881	1			T21	24		T22	69		T23	1414
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	398085	1			T22	7		T23	20683		T26	1582
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1216360	1			T21	4		T22	46		T23	13660
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4671707	1			T21	43		T22	57		T23	22408
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3468057	1			T21	13		T22	5		T23	41665
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1226046	1			T21	8		T22	23		T23	13974
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1566050	1			T22	57		T23	1413		T24	6
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	394043	1			T22	11		T23	20874		T24	7
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1213961	1			T22	38		T23	13496		T24	2
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4673082	1			T21	32		T22	66		T23	22330
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3469985	1			T21	7		T22	1		T23	41557
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1229703	1			T21	8		T22	22		T23	13993
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1561011	1			T21	13		T22	79		T23	1380
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	394071	1			T22	5		T23	20844		T24	6
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1212012	1			T21	4		T22	18		T23	13726
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4671281	1			T21	34		T22	76		T23	22456
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3465478	1			T21	6		T22	9		T23	41803
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1224983	1			T22	4		T23	13623		T24	15
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1559525	1			T21	23		T22	59		T23	1406
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	395148	1			T21	1		T22	4		T23	20528
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1223449	1			T22	39		T23	14014		T24	9
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4664065	1			T21	26		T22	42		T23	22210
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3475828	1			T21	8		T22	9		T23	42651
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1232803	1			T21	2		T22	27		T23	14055
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1554677	1			T21	18		T22	73		T23	1373
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	394210	1			T22	8		T23	20049		T24	13
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1218281	1			T21	10		T22	32		T23	13492
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4666065	1			T21	24		T22	58		T23	22215
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3471182	1			T21	8		T22	4		T23	42383
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1226254	1			T21	12		T22	32		T23	13402
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1559959	1			T21	17		T22	60		T23	1304
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	396125	1			T21	2		T22	5		T23	20496
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1220279	1			T21	1		T22	32		T23	14030
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4667668	1			T21	19		T22	60		T23	22269
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3475909	1			T21	3		T22	19		T23	42023
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1223806	1			T21	1		T22	26		T23	14000
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1561835	1			T21	26		T22	62		T23	1296
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	391669	1			T21	2		T22	1		T23	20167
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1218977	1			T21	13		T22	23		T23	14075
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4667654	1			T21	44		T22	95		T23	22273
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3470593	1			T21	12		T22	10		T23	41405
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1225909	1			T22	26		T23	13737		T25	175
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1556831	1			T21	8		T22	53		T23	1349
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	395970	1			T22	3		T23	21113		T24	7
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1222907	1			T22	4		T23	13953		T25	154
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4669366	1			T21	19		T22	66		T23	22339
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3473993	1			T21	6		T22	11		T23	42077
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1232476	1			T21	2		T22	49		T23	14101
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1558382	1			T21	25		T22	48		T23	1380
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	394056	1			T21	6		T22	7		T23	20289
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1211591	1			T21	6		T22	10		T23	13644
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4665115	1			T21	19		T22	67		T23	22165
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3470505	1			T21	5		T22	9		T23	42152
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1231008	1			T21	6		T22	23		T23	14135
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1558640	1			T21	21		T22	54		T23	1317
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	394304	1			T21	6		T22	4		T23	20324
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1220292	1			T21	7		T22	34		T23	13737
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4673271	1			T21	25		T22	107		T23	22182
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3462245	1			T21	10		T22	7		T23	42025
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1224459	1			T22	21		T23	14032		T24	2
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1565304	1			T21	21		T22	44		T23	1394
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	396613	1			T21	3		T22	4		T23	20150
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1217972	1			T21	5		T22	8		T23	14047
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4668963	1			T21	19		T22	44		T23	22202
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3473417	1			T21	11		T22	4		T23	41419
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1226036	1			T21	5		T22	14		T23	14373
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1561729	1			T21	26		T22	66		T23	1393
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	395348	1			T21	3		T22	8		T23	21011
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1214371	1			T22	55		T23	13432		T24	2
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4670885	1			T21	16		T22	57		T23	22367
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3469021	1			T21	8		T22	9		T23	41856
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1227458	1			T21	2		T22	36		T23	13725
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1556963	1			T21	27		T22	46		T23	1361
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	394535	1			T21	1		T22	2		T23	20614
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1221002	1			T21	10		T22	41		T23	13907
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4665735	1			T21	15		T22	57		T23	22235
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3468863	1			T21	6		T22	7		T23	41531
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1231502	1			T21	6		T22	21		T23	13953
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1557657	1			T21	25		T22	52		T23	1359
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	393967	1			T21	4		T22	6		T23	20920
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1222140	1			T21	8		T22	48		T23	13832
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4660497	1			T21	50		T22	81		T23	22356
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3473424	1			T21	13		T22	8		T23	41913
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1229261	1			T22	42		T23	14484		T25	152
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1563030	1			T21	1		T22	41		T23	1366
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	395019	1			T22	2		T23	19797		T24	28
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1218633	1			T22	17		T23	13914		T24	2
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4666463	1			T21	21		T22	57		T23	22429
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3470521	1			T21	12		T22	3		T23	41873
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1229224	1			T21	6		T22	50		T23	14140
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1562015	1			T21	18		T22	50		T23	1281
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	394936	1			T22	9		T23	20482		T24	10
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1216705	1			T21	7		T22	22		T23	13625

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal