Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[1]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[2]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[3]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[4]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[5]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[6]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[7]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[8]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[9]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[10]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[11]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[12]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[13]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[14]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[15]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[16]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[17]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[18]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[19]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[20]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[21]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[22]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[23]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[24]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[25]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[26]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[27]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[28]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[29]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[30]	12539864	1			T21	64		T22	191		T23	113830
bins_for_gpio_bits[31]	12539864	1			T21	64		T22	191		T23	113830

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238565371

1

T21

1581

T22

4841

T23

120367

auto[1]

162710277

1

T21

467

T22

1271

T23

243888

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238556127

1

T21

1575

T22

4841

T23

120394

auto[1]

162719521

1

T21

473

T22

1271

T23

243861

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7237261	1			T21	51		T22	138		T23	35682
bins_for_gpio_bits[0]	auto[0]	auto[1]	217865	1			T22	5		T23	2480		T25	51
bins_for_gpio_bits[0]	auto[1]	auto[0]	218179	1			T22	5		T23	2470		T25	51
bins_for_gpio_bits[0]	auto[1]	auto[1]	4866559	1			T21	13		T22	43		T23	73198
bins_for_gpio_bits[1]	auto[0]	auto[0]	7231116	1			T21	44		T22	135		T23	35392
bins_for_gpio_bits[1]	auto[0]	auto[1]	217382	1			T21	1		T22	6		T23	2424
bins_for_gpio_bits[1]	auto[1]	auto[0]	217684	1			T21	1		T22	6		T23	2416
bins_for_gpio_bits[1]	auto[1]	auto[1]	4873682	1			T21	18		T22	44		T23	73598
bins_for_gpio_bits[2]	auto[0]	auto[0]	7229340	1			T21	40		T22	140		T23	35220
bins_for_gpio_bits[2]	auto[0]	auto[1]	217693	1			T21	1		T22	4		T23	2443
bins_for_gpio_bits[2]	auto[1]	auto[0]	218000	1			T21	1		T22	4		T23	2427
bins_for_gpio_bits[2]	auto[1]	auto[1]	4874831	1			T21	22		T22	43		T23	73740
bins_for_gpio_bits[3]	auto[0]	auto[0]	7244030	1			T21	42		T22	162		T23	34980
bins_for_gpio_bits[3]	auto[0]	auto[1]	217271	1			T21	2		T22	2		T23	2437
bins_for_gpio_bits[3]	auto[1]	auto[0]	217559	1			T21	2		T22	2		T23	2425
bins_for_gpio_bits[3]	auto[1]	auto[1]	4861004	1			T21	18		T22	25		T23	73988
bins_for_gpio_bits[4]	auto[0]	auto[0]	7233681	1			T21	54		T22	151		T23	34978
bins_for_gpio_bits[4]	auto[0]	auto[1]	218397	1			T22	4		T23	2380		T25	46
bins_for_gpio_bits[4]	auto[1]	auto[0]	218683	1			T22	4		T23	2371		T25	46
bins_for_gpio_bits[4]	auto[1]	auto[1]	4869103	1			T21	10		T22	32		T23	74101
bins_for_gpio_bits[5]	auto[0]	auto[0]	7229228	1			T21	42		T22	178		T23	35254
bins_for_gpio_bits[5]	auto[0]	auto[1]	217950	1			T22	1		T23	2447		T25	40
bins_for_gpio_bits[5]	auto[1]	auto[0]	218269	1			T21	1		T22	1		T23	2434
bins_for_gpio_bits[5]	auto[1]	auto[1]	4874417	1			T21	21		T22	11		T23	73695
bins_for_gpio_bits[6]	auto[0]	auto[0]	7234638	1			T21	53		T22	147		T23	35126
bins_for_gpio_bits[6]	auto[0]	auto[1]	217468	1			T22	5		T23	2415		T25	44
bins_for_gpio_bits[6]	auto[1]	auto[0]	217786	1			T22	5		T23	2407		T25	44
bins_for_gpio_bits[6]	auto[1]	auto[1]	4869972	1			T21	11		T22	34		T23	73882
bins_for_gpio_bits[7]	auto[0]	auto[0]	7238471	1			T21	58		T22	163		T23	35292
bins_for_gpio_bits[7]	auto[0]	auto[1]	218072	1			T22	3		T23	2430		T25	45
bins_for_gpio_bits[7]	auto[1]	auto[0]	218347	1			T22	3		T23	2424		T25	46
bins_for_gpio_bits[7]	auto[1]	auto[1]	4864974	1			T21	6		T22	22		T23	73684
bins_for_gpio_bits[8]	auto[0]	auto[0]	7240218	1			T21	51		T22	137		T23	34488
bins_for_gpio_bits[8]	auto[0]	auto[1]	217246	1			T22	7		T23	2361		T25	42
bins_for_gpio_bits[8]	auto[1]	auto[0]	217584	1			T22	7		T23	2355		T25	42
bins_for_gpio_bits[8]	auto[1]	auto[1]	4864816	1			T21	13		T22	40		T23	74626
bins_for_gpio_bits[9]	auto[0]	auto[0]	7228596	1			T21	47		T22	154		T23	35378
bins_for_gpio_bits[9]	auto[0]	auto[1]	218252	1			T21	1		T22	2		T23	2417
bins_for_gpio_bits[9]	auto[1]	auto[0]	218529	1			T21	1		T22	2		T23	2409
bins_for_gpio_bits[9]	auto[1]	auto[1]	4874487	1			T21	15		T22	33		T23	73626
bins_for_gpio_bits[10]	auto[0]	auto[0]	7236229	1			T21	44		T22	158		T23	35001
bins_for_gpio_bits[10]	auto[0]	auto[1]	217995	1			T21	1		T22	3		T23	2433
bins_for_gpio_bits[10]	auto[1]	auto[0]	218287	1			T21	1		T22	3		T23	2426
bins_for_gpio_bits[10]	auto[1]	auto[1]	4867353	1			T21	18		T22	27		T23	73970
bins_for_gpio_bits[11]	auto[0]	auto[0]	7249465	1			T21	52		T22	140		T23	35407
bins_for_gpio_bits[11]	auto[0]	auto[1]	217805	1			T22	7		T23	2416		T25	40
bins_for_gpio_bits[11]	auto[1]	auto[0]	218070	1			T22	7		T23	2406		T25	40
bins_for_gpio_bits[11]	auto[1]	auto[1]	4854524	1			T21	12		T22	37		T23	73601
bins_for_gpio_bits[12]	auto[0]	auto[0]	7238530	1			T21	40		T22	155		T23	35207
bins_for_gpio_bits[12]	auto[0]	auto[1]	216975	1			T21	3		T22	4		T23	2412
bins_for_gpio_bits[12]	auto[1]	auto[0]	217259	1			T21	3		T22	4		T23	2403
bins_for_gpio_bits[12]	auto[1]	auto[1]	4867100	1			T21	18		T22	28		T23	73808
bins_for_gpio_bits[13]	auto[0]	auto[0]	7229559	1			T21	59		T22	149		T23	35043
bins_for_gpio_bits[13]	auto[0]	auto[1]	217731	1			T22	4		T23	2469		T25	40
bins_for_gpio_bits[13]	auto[1]	auto[0]	218034	1			T22	4		T23	2459		T25	40
bins_for_gpio_bits[13]	auto[1]	auto[1]	4874540	1			T21	5		T22	34		T23	73859
bins_for_gpio_bits[14]	auto[0]	auto[0]	7236123	1			T21	55		T22	146		T23	34977
bins_for_gpio_bits[14]	auto[0]	auto[1]	217804	1			T21	1		T22	5		T23	2404
bins_for_gpio_bits[14]	auto[1]	auto[0]	218060	1			T21	1		T22	5		T23	2396
bins_for_gpio_bits[14]	auto[1]	auto[1]	4867877	1			T21	7		T22	35		T23	74053
bins_for_gpio_bits[15]	auto[0]	auto[0]	7234345	1			T21	51		T22	140		T23	35356
bins_for_gpio_bits[15]	auto[0]	auto[1]	218166	1			T21	1		T22	6		T23	2444
bins_for_gpio_bits[15]	auto[1]	auto[0]	218444	1			T21	1		T22	6		T23	2439
bins_for_gpio_bits[15]	auto[1]	auto[1]	4868909	1			T21	11		T22	39		T23	73591
bins_for_gpio_bits[16]	auto[0]	auto[0]	7241787	1			T21	52		T22	125		T23	35315
bins_for_gpio_bits[16]	auto[0]	auto[1]	217325	1			T21	1		T22	5		T23	2381
bins_for_gpio_bits[16]	auto[1]	auto[0]	217627	1			T21	1		T22	5		T23	2376
bins_for_gpio_bits[16]	auto[1]	auto[1]	4863125	1			T21	10		T22	56		T23	73758
bins_for_gpio_bits[17]	auto[0]	auto[0]	7245888	1			T21	51		T22	132		T23	35454
bins_for_gpio_bits[17]	auto[0]	auto[1]	217645	1			T22	5		T23	2348		T25	43
bins_for_gpio_bits[17]	auto[1]	auto[0]	217915	1			T22	5		T23	2341		T25	43
bins_for_gpio_bits[17]	auto[1]	auto[1]	4858416	1			T21	13		T22	49		T23	73687
bins_for_gpio_bits[18]	auto[0]	auto[0]	7246734	1			T21	52		T22	163		T23	35335
bins_for_gpio_bits[18]	auto[0]	auto[1]	216777	1			T21	1		T22	4		T23	2375
bins_for_gpio_bits[18]	auto[1]	auto[0]	217062	1			T21	1		T22	4		T23	2368
bins_for_gpio_bits[18]	auto[1]	auto[1]	4859291	1			T21	10		T22	20		T23	73752
bins_for_gpio_bits[19]	auto[0]	auto[0]	7237715	1			T21	57		T22	136		T23	35120
bins_for_gpio_bits[19]	auto[0]	auto[1]	217781	1			T22	3		T23	2374		T24	1
bins_for_gpio_bits[19]	auto[1]	auto[0]	218074	1			T22	3		T23	2365		T25	41
bins_for_gpio_bits[19]	auto[1]	auto[1]	4866294	1			T21	7		T22	49		T23	73971
bins_for_gpio_bits[20]	auto[0]	auto[0]	7233718	1			T21	44		T22	134		T23	35196
bins_for_gpio_bits[20]	auto[0]	auto[1]	217530	1			T21	2		T22	8		T23	2448
bins_for_gpio_bits[20]	auto[1]	auto[0]	217827	1			T21	2		T22	8		T23	2442
bins_for_gpio_bits[20]	auto[1]	auto[1]	4870789	1			T21	16		T22	41		T23	73744
bins_for_gpio_bits[21]	auto[0]	auto[0]	7234507	1			T21	52		T22	146		T23	34565
bins_for_gpio_bits[21]	auto[0]	auto[1]	217488	1			T22	4		T23	2367		T25	42
bins_for_gpio_bits[21]	auto[1]	auto[0]	217771	1			T21	1		T22	4		T23	2356
bins_for_gpio_bits[21]	auto[1]	auto[1]	4870098	1			T21	11		T22	37		T23	74542
bins_for_gpio_bits[22]	auto[0]	auto[0]	7234953	1			T21	44		T22	141		T23	35136
bins_for_gpio_bits[22]	auto[0]	auto[1]	218027	1			T21	1		T22	7		T23	2439
bins_for_gpio_bits[22]	auto[1]	auto[0]	218356	1			T21	2		T22	7		T23	2429
bins_for_gpio_bits[22]	auto[1]	auto[1]	4868528	1			T21	17		T22	36		T23	73826
bins_for_gpio_bits[23]	auto[0]	auto[0]	7232338	1			T21	52		T22	172		T23	34959
bins_for_gpio_bits[23]	auto[0]	auto[1]	217729	1			T22	2		T23	2406		T25	36
bins_for_gpio_bits[23]	auto[1]	auto[0]	218056	1			T22	2		T23	2400		T25	36
bins_for_gpio_bits[23]	auto[1]	auto[1]	4871741	1			T21	12		T22	15		T23	74065
bins_for_gpio_bits[24]	auto[0]	auto[0]	7242423	1			T21	45		T22	161		T23	35318
bins_for_gpio_bits[24]	auto[0]	auto[1]	217564	1			T21	1		T22	2		T23	2511
bins_for_gpio_bits[24]	auto[1]	auto[0]	217801	1			T21	1		T22	2		T23	2502
bins_for_gpio_bits[24]	auto[1]	auto[1]	4862076	1			T21	17		T22	26		T23	73499
bins_for_gpio_bits[25]	auto[0]	auto[0]	7236822	1			T21	45		T22	141		T23	35176
bins_for_gpio_bits[25]	auto[0]	auto[1]	217652	1			T22	3		T23	2449		T25	39
bins_for_gpio_bits[25]	auto[1]	auto[0]	217941	1			T21	1		T22	3		T23	2441
bins_for_gpio_bits[25]	auto[1]	auto[1]	4867449	1			T21	18		T22	44		T23	73764
bins_for_gpio_bits[26]	auto[0]	auto[0]	7245177	1			T21	45		T22	169		T23	35161
bins_for_gpio_bits[26]	auto[0]	auto[1]	217563	1			T22	3		T23	2451		T25	33
bins_for_gpio_bits[26]	auto[1]	auto[0]	217857	1			T21	1		T22	3		T23	2447
bins_for_gpio_bits[26]	auto[1]	auto[1]	4859267	1			T21	18		T22	16		T23	73771
bins_for_gpio_bits[27]	auto[0]	auto[0]	7239197	1			T21	50		T22	115		T23	35541
bins_for_gpio_bits[27]	auto[0]	auto[1]	217239	1			T22	9		T23	2432		T25	38
bins_for_gpio_bits[27]	auto[1]	auto[0]	217531	1			T22	9		T23	2427		T25	38
bins_for_gpio_bits[27]	auto[1]	auto[1]	4865897	1			T21	14		T22	58		T23	73430
bins_for_gpio_bits[28]	auto[0]	auto[0]	7236773	1			T21	43		T22	132		T23	35015
bins_for_gpio_bits[28]	auto[0]	auto[1]	218266	1			T21	2		T22	7		T23	2452
bins_for_gpio_bits[28]	auto[1]	auto[0]	218533	1			T21	2		T22	7		T23	2438
bins_for_gpio_bits[28]	auto[1]	auto[1]	4866292	1			T21	17		T22	45		T23	73925
bins_for_gpio_bits[29]	auto[0]	auto[0]	7236153	1			T21	45		T22	124		T23	35139
bins_for_gpio_bits[29]	auto[0]	auto[1]	218497	1			T21	1		T22	6		T23	2416
bins_for_gpio_bits[29]	auto[1]	auto[0]	218741	1			T21	1		T22	6		T23	2408
bins_for_gpio_bits[29]	auto[1]	auto[1]	4866473	1			T21	17		T22	55		T23	73867
bins_for_gpio_bits[30]	auto[0]	auto[0]	7234786	1			T21	51		T22	161		T23	35738
bins_for_gpio_bits[30]	auto[0]	auto[1]	217746	1			T22	3		T23	2475		T25	39
bins_for_gpio_bits[30]	auto[1]	auto[0]	218002	1			T22	3		T23	2468		T25	40
bins_for_gpio_bits[30]	auto[1]	auto[1]	4869330	1			T21	13		T22	24		T23	73149
bins_for_gpio_bits[31]	auto[0]	auto[0]	7239442	1			T21	43		T22	152		T23	35464
bins_for_gpio_bits[31]	auto[0]	auto[1]	217983	1			T21	1		T22	5		T23	2396
bins_for_gpio_bits[31]	auto[1]	auto[0]	218260	1			T21	2		T22	5		T23	2386
bins_for_gpio_bits[31]	auto[1]	auto[1]	4864179	1			T21	18		T22	29		T23	73584