Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7468969 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
67993 |
| auto[1] |
5284925 |
1 |
|
|
T23 |
47514 |
|
T24 |
3 |
|
T26 |
58108 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12079230 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
109993 |
| auto[1] |
674664 |
1 |
|
|
T23 |
5514 |
|
T26 |
6353 |
|
T29 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7446815 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
67007 |
| auto[1] |
5307079 |
1 |
|
|
T23 |
48500 |
|
T24 |
11 |
|
T26 |
56354 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2318366 |
1 |
|
|
T23 |
22059 |
|
T24 |
8 |
|
T26 |
24740 |
| auto[1] |
auto[0] |
auto[1] |
337028 |
1 |
|
|
T23 |
2827 |
|
T26 |
3095 |
|
T29 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2314049 |
1 |
|
|
T23 |
20927 |
|
T24 |
3 |
|
T26 |
25261 |
| auto[1] |
auto[1] |
auto[1] |
337636 |
1 |
|
|
T23 |
2687 |
|
T26 |
3258 |
|
T29 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |