Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7479838 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
66666 |
| auto[1] |
5274056 |
1 |
|
|
T23 |
48841 |
|
T24 |
4 |
|
T26 |
54915 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12082516 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
109759 |
| auto[1] |
671378 |
1 |
|
|
T23 |
5748 |
|
T24 |
1 |
|
T26 |
6931 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7473897 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
65816 |
| auto[1] |
5279997 |
1 |
|
|
T23 |
49691 |
|
T24 |
13 |
|
T26 |
58934 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2320363 |
1 |
|
|
T23 |
22931 |
|
T24 |
12 |
|
T26 |
27162 |
| auto[1] |
auto[0] |
auto[1] |
337882 |
1 |
|
|
T23 |
3040 |
|
T24 |
1 |
|
T26 |
3522 |
| auto[1] |
auto[1] |
auto[0] |
2288256 |
1 |
|
|
T23 |
21012 |
|
T26 |
24841 |
|
T29 |
112 |
| auto[1] |
auto[1] |
auto[1] |
333496 |
1 |
|
|
T23 |
2708 |
|
T26 |
3409 |
|
T29 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |