Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7469072 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
64685 |
| auto[1] |
5284822 |
1 |
|
|
T23 |
50822 |
|
T24 |
25 |
|
T26 |
59736 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12080974 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
109335 |
| auto[1] |
672920 |
1 |
|
|
T23 |
6172 |
|
T26 |
6745 |
|
T29 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7465644 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
63257 |
| auto[1] |
5288250 |
1 |
|
|
T23 |
52250 |
|
T24 |
13 |
|
T26 |
57725 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2293249 |
1 |
|
|
T23 |
22445 |
|
T24 |
10 |
|
T26 |
24043 |
| auto[1] |
auto[0] |
auto[1] |
333796 |
1 |
|
|
T23 |
2991 |
|
T26 |
3213 |
|
T29 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2322081 |
1 |
|
|
T23 |
23633 |
|
T24 |
3 |
|
T26 |
26937 |
| auto[1] |
auto[1] |
auto[1] |
339124 |
1 |
|
|
T23 |
3181 |
|
T26 |
3532 |
|
T29 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |