Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7489762 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
65490 |
auto[1] |
5264132 |
1 |
|
|
T23 |
50017 |
|
T24 |
16 |
|
T26 |
57453 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10557713 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
83811 |
auto[1] |
2196181 |
1 |
|
|
T23 |
31696 |
|
T26 |
20601 |
|
T29 |
117 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7464194 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
65019 |
auto[1] |
5289700 |
1 |
|
|
T23 |
50488 |
|
T24 |
3 |
|
T26 |
55717 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1556403 |
1 |
|
|
T23 |
9263 |
|
T24 |
2 |
|
T26 |
17469 |
auto[1] |
auto[0] |
auto[1] |
1106344 |
1 |
|
|
T23 |
16474 |
|
T26 |
10199 |
|
T29 |
53 |
auto[1] |
auto[1] |
auto[0] |
1537116 |
1 |
|
|
T23 |
9529 |
|
T24 |
1 |
|
T26 |
17647 |
auto[1] |
auto[1] |
auto[1] |
1089837 |
1 |
|
|
T23 |
15222 |
|
T26 |
10402 |
|
T29 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |