Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7495062 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
66085 |
auto[1] |
5258832 |
1 |
|
|
T23 |
49422 |
|
T24 |
34 |
|
T26 |
59325 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10561528 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
83441 |
auto[1] |
2192366 |
1 |
|
|
T23 |
32066 |
|
T26 |
21026 |
|
T29 |
197 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7461683 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
63968 |
auto[1] |
5292211 |
1 |
|
|
T23 |
51539 |
|
T24 |
8 |
|
T26 |
56878 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1560362 |
1 |
|
|
T23 |
9944 |
|
T24 |
2 |
|
T26 |
17431 |
auto[1] |
auto[0] |
auto[1] |
1105977 |
1 |
|
|
T23 |
16273 |
|
T26 |
10587 |
|
T29 |
81 |
auto[1] |
auto[1] |
auto[0] |
1539483 |
1 |
|
|
T23 |
9529 |
|
T24 |
6 |
|
T26 |
18421 |
auto[1] |
auto[1] |
auto[1] |
1086389 |
1 |
|
|
T23 |
15793 |
|
T26 |
10439 |
|
T29 |
116 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |