Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7442526 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
64021 |
| auto[1] |
5311368 |
1 |
|
|
T23 |
51486 |
|
T24 |
13 |
|
T26 |
57050 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10576174 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
83403 |
| auto[1] |
2177720 |
1 |
|
|
T23 |
32104 |
|
T24 |
6 |
|
T26 |
21412 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7490620 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
64020 |
| auto[1] |
5263274 |
1 |
|
|
T23 |
51487 |
|
T24 |
9 |
|
T26 |
56234 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1528019 |
1 |
|
|
T23 |
9469 |
|
T24 |
3 |
|
T26 |
17370 |
| auto[1] |
auto[0] |
auto[1] |
1083017 |
1 |
|
|
T23 |
16231 |
|
T24 |
2 |
|
T26 |
10685 |
| auto[1] |
auto[1] |
auto[0] |
1557535 |
1 |
|
|
T23 |
9914 |
|
T26 |
17452 |
|
T29 |
16 |
| auto[1] |
auto[1] |
auto[1] |
1094703 |
1 |
|
|
T23 |
15873 |
|
T24 |
4 |
|
T26 |
10727 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |