Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7433904 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
65253 |
| auto[1] |
5319990 |
1 |
|
|
T23 |
50254 |
|
T24 |
4 |
|
T26 |
56006 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10559528 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
84181 |
| auto[1] |
2194366 |
1 |
|
|
T23 |
31326 |
|
T24 |
2 |
|
T26 |
21300 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7453367 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
65336 |
| auto[1] |
5300527 |
1 |
|
|
T23 |
50171 |
|
T24 |
2 |
|
T26 |
57536 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1552948 |
1 |
|
|
T23 |
9306 |
|
T26 |
18399 |
|
T29 |
12 |
| auto[1] |
auto[0] |
auto[1] |
1097255 |
1 |
|
|
T23 |
15718 |
|
T24 |
2 |
|
T26 |
11283 |
| auto[1] |
auto[1] |
auto[0] |
1553213 |
1 |
|
|
T23 |
9539 |
|
T26 |
17837 |
|
T29 |
3 |
| auto[1] |
auto[1] |
auto[1] |
1097111 |
1 |
|
|
T23 |
15608 |
|
T26 |
10017 |
|
T29 |
77 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |