Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7465377 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
66089 |
| auto[1] |
5288517 |
1 |
|
|
T23 |
49418 |
|
T24 |
8 |
|
T26 |
58666 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12079759 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
109668 |
| auto[1] |
674135 |
1 |
|
|
T23 |
5839 |
|
T26 |
6808 |
|
T29 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7445586 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
65407 |
| auto[1] |
5308308 |
1 |
|
|
T23 |
50100 |
|
T26 |
58750 |
|
T29 |
214 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2334444 |
1 |
|
|
T23 |
23059 |
|
T26 |
25954 |
|
T29 |
147 |
| auto[1] |
auto[0] |
auto[1] |
340729 |
1 |
|
|
T23 |
3130 |
|
T26 |
3402 |
|
T29 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2299729 |
1 |
|
|
T23 |
21202 |
|
T26 |
25988 |
|
T29 |
61 |
| auto[1] |
auto[1] |
auto[1] |
333406 |
1 |
|
|
T23 |
2709 |
|
T26 |
3406 |
|
T29 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |