Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7426680 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
65040 |
auto[1] |
5327214 |
1 |
|
|
T23 |
50467 |
|
T24 |
31 |
|
T26 |
60318 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12087256 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
109554 |
auto[1] |
666638 |
1 |
|
|
T23 |
5953 |
|
T26 |
6344 |
|
T29 |
6 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7502580 |
1 |
|
|
T21 |
31 |
|
T22 |
97 |
|
T23 |
64509 |
auto[1] |
5251314 |
1 |
|
|
T23 |
50998 |
|
T24 |
16 |
|
T26 |
55422 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2276747 |
1 |
|
|
T23 |
22669 |
|
T24 |
4 |
|
T26 |
23676 |
auto[1] |
auto[0] |
auto[1] |
328895 |
1 |
|
|
T23 |
3004 |
|
T26 |
3031 |
|
T29 |
1 |
auto[1] |
auto[1] |
auto[0] |
2307929 |
1 |
|
|
T23 |
22376 |
|
T24 |
12 |
|
T26 |
25402 |
auto[1] |
auto[1] |
auto[1] |
337743 |
1 |
|
|
T23 |
2949 |
|
T26 |
3313 |
|
T29 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |