Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 941
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T760 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2717047849 Jul 12 05:42:17 PM PDT 24 Jul 12 05:42:21 PM PDT 24 180143477 ps
T761 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2925088072 Jul 12 05:42:27 PM PDT 24 Jul 12 05:42:30 PM PDT 24 19388587 ps
T95 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1190917206 Jul 12 05:41:57 PM PDT 24 Jul 12 05:41:59 PM PDT 24 38945173 ps
T97 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1644585539 Jul 12 05:41:57 PM PDT 24 Jul 12 05:42:00 PM PDT 24 135739245 ps
T762 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.4229381237 Jul 12 05:42:34 PM PDT 24 Jul 12 05:42:35 PM PDT 24 237112099 ps
T763 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2697057950 Jul 12 05:42:38 PM PDT 24 Jul 12 05:42:40 PM PDT 24 38116560 ps
T764 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.888532854 Jul 12 05:42:38 PM PDT 24 Jul 12 05:42:42 PM PDT 24 520049079 ps
T47 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.392735777 Jul 12 05:42:19 PM PDT 24 Jul 12 05:42:21 PM PDT 24 406445219 ps
T109 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.51239036 Jul 12 05:42:18 PM PDT 24 Jul 12 05:42:19 PM PDT 24 76962565 ps
T765 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1523065571 Jul 12 05:42:30 PM PDT 24 Jul 12 05:42:32 PM PDT 24 19270316 ps
T766 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.4096771361 Jul 12 05:42:37 PM PDT 24 Jul 12 05:42:39 PM PDT 24 298299343 ps
T767 /workspace/coverage/cover_reg_top/8.gpio_intr_test.4205238711 Jul 12 05:42:10 PM PDT 24 Jul 12 05:42:12 PM PDT 24 39304122 ps
T768 /workspace/coverage/cover_reg_top/40.gpio_intr_test.1505877854 Jul 12 05:42:45 PM PDT 24 Jul 12 05:42:47 PM PDT 24 20156673 ps
T769 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2651543866 Jul 12 05:42:26 PM PDT 24 Jul 12 05:42:29 PM PDT 24 174697438 ps
T770 /workspace/coverage/cover_reg_top/14.gpio_intr_test.3732462665 Jul 12 05:42:28 PM PDT 24 Jul 12 05:42:30 PM PDT 24 21706327 ps
T771 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2828474164 Jul 12 05:42:12 PM PDT 24 Jul 12 05:42:13 PM PDT 24 43560709 ps
T772 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2516221462 Jul 12 05:42:10 PM PDT 24 Jul 12 05:42:12 PM PDT 24 124102023 ps
T773 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1501412607 Jul 12 05:42:36 PM PDT 24 Jul 12 05:42:37 PM PDT 24 16388812 ps
T98 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.521838461 Jul 12 05:41:41 PM PDT 24 Jul 12 05:41:44 PM PDT 24 1680801816 ps
T774 /workspace/coverage/cover_reg_top/25.gpio_intr_test.1138637220 Jul 12 05:42:46 PM PDT 24 Jul 12 05:42:47 PM PDT 24 12220533 ps
T775 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3468184207 Jul 12 05:42:34 PM PDT 24 Jul 12 05:42:35 PM PDT 24 39437936 ps
T776 /workspace/coverage/cover_reg_top/43.gpio_intr_test.2831643009 Jul 12 05:42:41 PM PDT 24 Jul 12 05:42:43 PM PDT 24 38380248 ps
T777 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3338345472 Jul 12 05:41:36 PM PDT 24 Jul 12 05:41:37 PM PDT 24 30353063 ps
T48 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1498066635 Jul 12 05:42:03 PM PDT 24 Jul 12 05:42:05 PM PDT 24 45189055 ps
T778 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3665237683 Jul 12 05:42:41 PM PDT 24 Jul 12 05:42:43 PM PDT 24 45065999 ps
T779 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3425837782 Jul 12 05:42:31 PM PDT 24 Jul 12 05:42:33 PM PDT 24 24430781 ps
T780 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1746499714 Jul 12 05:42:27 PM PDT 24 Jul 12 05:42:30 PM PDT 24 15124174 ps
T781 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3270458954 Jul 12 05:41:48 PM PDT 24 Jul 12 05:41:50 PM PDT 24 104690567 ps
T782 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.889106191 Jul 12 05:41:43 PM PDT 24 Jul 12 05:41:45 PM PDT 24 34761356 ps
T783 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1017914492 Jul 12 05:42:04 PM PDT 24 Jul 12 05:42:06 PM PDT 24 61474331 ps
T784 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3876678969 Jul 12 05:42:34 PM PDT 24 Jul 12 05:42:35 PM PDT 24 26378388 ps
T785 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2970357309 Jul 12 05:41:49 PM PDT 24 Jul 12 05:41:50 PM PDT 24 27048164 ps
T786 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1964618523 Jul 12 05:42:20 PM PDT 24 Jul 12 05:42:21 PM PDT 24 85526846 ps
T787 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2415009559 Jul 12 05:41:56 PM PDT 24 Jul 12 05:41:57 PM PDT 24 30482577 ps
T788 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2998565578 Jul 12 05:41:53 PM PDT 24 Jul 12 05:41:55 PM PDT 24 78075120 ps
T789 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.254982522 Jul 12 05:42:38 PM PDT 24 Jul 12 05:42:39 PM PDT 24 102867638 ps
T790 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3010511363 Jul 12 05:41:50 PM PDT 24 Jul 12 05:41:52 PM PDT 24 23852104 ps
T791 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1030217928 Jul 12 05:42:27 PM PDT 24 Jul 12 05:42:31 PM PDT 24 681416819 ps
T99 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3294963381 Jul 12 05:42:19 PM PDT 24 Jul 12 05:42:20 PM PDT 24 41131050 ps
T792 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1665997127 Jul 12 05:42:29 PM PDT 24 Jul 12 05:42:31 PM PDT 24 14280520 ps
T793 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1859641006 Jul 12 05:42:35 PM PDT 24 Jul 12 05:42:37 PM PDT 24 42039157 ps
T794 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.4198045786 Jul 12 05:42:17 PM PDT 24 Jul 12 05:42:21 PM PDT 24 286095075 ps
T795 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1691680527 Jul 12 05:42:38 PM PDT 24 Jul 12 05:42:40 PM PDT 24 60703400 ps
T796 /workspace/coverage/cover_reg_top/5.gpio_intr_test.160497774 Jul 12 05:42:02 PM PDT 24 Jul 12 05:42:03 PM PDT 24 16485391 ps
T797 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2432479153 Jul 12 05:42:27 PM PDT 24 Jul 12 05:42:31 PM PDT 24 411548311 ps
T798 /workspace/coverage/cover_reg_top/24.gpio_intr_test.1503009911 Jul 12 05:42:41 PM PDT 24 Jul 12 05:42:43 PM PDT 24 31306233 ps
T799 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3228842536 Jul 12 05:42:27 PM PDT 24 Jul 12 05:42:29 PM PDT 24 43922253 ps
T800 /workspace/coverage/cover_reg_top/26.gpio_intr_test.3878160274 Jul 12 05:42:43 PM PDT 24 Jul 12 05:42:44 PM PDT 24 45753219 ps
T801 /workspace/coverage/cover_reg_top/32.gpio_intr_test.552186743 Jul 12 05:42:43 PM PDT 24 Jul 12 05:42:44 PM PDT 24 12927481 ps
T802 /workspace/coverage/cover_reg_top/9.gpio_intr_test.4053038237 Jul 12 05:42:20 PM PDT 24 Jul 12 05:42:22 PM PDT 24 16327094 ps
T803 /workspace/coverage/cover_reg_top/7.gpio_intr_test.4233022810 Jul 12 05:42:12 PM PDT 24 Jul 12 05:42:14 PM PDT 24 101740880 ps
T804 /workspace/coverage/cover_reg_top/15.gpio_intr_test.2832836114 Jul 12 05:42:27 PM PDT 24 Jul 12 05:42:30 PM PDT 24 12987120 ps
T805 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.438648494 Jul 12 05:41:56 PM PDT 24 Jul 12 05:41:58 PM PDT 24 81317604 ps
T806 /workspace/coverage/cover_reg_top/46.gpio_intr_test.746257717 Jul 12 05:42:48 PM PDT 24 Jul 12 05:42:50 PM PDT 24 20405338 ps
T807 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2605164860 Jul 12 05:42:27 PM PDT 24 Jul 12 05:42:29 PM PDT 24 146589166 ps
T808 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1693220260 Jul 12 05:41:34 PM PDT 24 Jul 12 05:41:35 PM PDT 24 29668935 ps
T809 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1096103633 Jul 12 05:41:42 PM PDT 24 Jul 12 05:41:44 PM PDT 24 179466623 ps
T810 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.551083343 Jul 12 05:42:04 PM PDT 24 Jul 12 05:42:06 PM PDT 24 52722152 ps
T811 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.386058064 Jul 12 05:42:03 PM PDT 24 Jul 12 05:42:04 PM PDT 24 13500341 ps
T812 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1851745812 Jul 12 05:42:21 PM PDT 24 Jul 12 05:42:23 PM PDT 24 686057500 ps
T813 /workspace/coverage/cover_reg_top/6.gpio_intr_test.482383174 Jul 12 05:42:12 PM PDT 24 Jul 12 05:42:13 PM PDT 24 53329420 ps
T814 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3311043385 Jul 12 05:42:38 PM PDT 24 Jul 12 05:42:40 PM PDT 24 64031681 ps
T815 /workspace/coverage/cover_reg_top/37.gpio_intr_test.2859021867 Jul 12 05:42:39 PM PDT 24 Jul 12 05:42:40 PM PDT 24 74781291 ps
T816 /workspace/coverage/cover_reg_top/10.gpio_intr_test.274237363 Jul 12 05:42:17 PM PDT 24 Jul 12 05:42:18 PM PDT 24 23627129 ps
T817 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2021044521 Jul 12 05:42:29 PM PDT 24 Jul 12 05:42:31 PM PDT 24 92899482 ps
T818 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3775543991 Jul 12 05:42:18 PM PDT 24 Jul 12 05:42:20 PM PDT 24 540616299 ps
T100 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1968809748 Jul 12 05:41:50 PM PDT 24 Jul 12 05:41:51 PM PDT 24 13649026 ps
T819 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.38019694 Jul 12 05:42:36 PM PDT 24 Jul 12 05:42:37 PM PDT 24 16872467 ps
T820 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.617945103 Jul 12 05:42:04 PM PDT 24 Jul 12 05:42:06 PM PDT 24 19122814 ps
T821 /workspace/coverage/cover_reg_top/44.gpio_intr_test.845165266 Jul 12 05:42:45 PM PDT 24 Jul 12 05:42:46 PM PDT 24 49407826 ps
T822 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.330981161 Jul 12 05:42:03 PM PDT 24 Jul 12 05:42:04 PM PDT 24 84516037 ps
T823 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1867781462 Jul 12 05:42:28 PM PDT 24 Jul 12 05:42:30 PM PDT 24 40099440 ps
T101 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1314566308 Jul 12 05:42:26 PM PDT 24 Jul 12 05:42:27 PM PDT 24 50501323 ps
T824 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3216541283 Jul 12 05:41:41 PM PDT 24 Jul 12 05:41:43 PM PDT 24 133155695 ps
T825 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2607297486 Jul 12 05:42:21 PM PDT 24 Jul 12 05:42:23 PM PDT 24 38863102 ps
T826 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.4255072194 Jul 12 05:42:31 PM PDT 24 Jul 12 05:42:33 PM PDT 24 117409024 ps
T827 /workspace/coverage/cover_reg_top/18.gpio_intr_test.4128375301 Jul 12 05:42:40 PM PDT 24 Jul 12 05:42:41 PM PDT 24 41638397 ps
T828 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2117754549 Jul 12 05:41:41 PM PDT 24 Jul 12 05:41:43 PM PDT 24 35089777 ps
T829 /workspace/coverage/cover_reg_top/41.gpio_intr_test.3207030641 Jul 12 05:42:40 PM PDT 24 Jul 12 05:42:42 PM PDT 24 16762106 ps
T830 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2759662498 Jul 12 05:41:55 PM PDT 24 Jul 12 05:41:57 PM PDT 24 42627162 ps
T831 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2290387006 Jul 12 05:41:55 PM PDT 24 Jul 12 05:41:57 PM PDT 24 42666139 ps
T832 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3285233167 Jul 12 05:42:48 PM PDT 24 Jul 12 05:42:49 PM PDT 24 11417392 ps
T833 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4243283973 Jul 12 05:41:56 PM PDT 24 Jul 12 05:41:58 PM PDT 24 145720405 ps
T834 /workspace/coverage/cover_reg_top/38.gpio_intr_test.1367340633 Jul 12 05:42:40 PM PDT 24 Jul 12 05:42:42 PM PDT 24 18010165 ps
T835 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1087576599 Jul 12 05:42:04 PM PDT 24 Jul 12 05:42:07 PM PDT 24 82482109 ps
T836 /workspace/coverage/cover_reg_top/45.gpio_intr_test.1545579298 Jul 12 05:42:40 PM PDT 24 Jul 12 05:42:42 PM PDT 24 13935575 ps
T837 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3502334074 Jul 12 05:42:12 PM PDT 24 Jul 12 05:42:14 PM PDT 24 121834718 ps
T838 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1331494238 Jul 12 05:42:05 PM PDT 24 Jul 12 05:42:07 PM PDT 24 58975533 ps
T839 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2921120731 Jul 12 05:42:29 PM PDT 24 Jul 12 05:42:31 PM PDT 24 35846561 ps
T840 /workspace/coverage/cover_reg_top/49.gpio_intr_test.718457081 Jul 12 05:42:48 PM PDT 24 Jul 12 05:42:50 PM PDT 24 116659641 ps
T841 /workspace/coverage/cover_reg_top/39.gpio_intr_test.352184855 Jul 12 05:42:43 PM PDT 24 Jul 12 05:42:44 PM PDT 24 31627607 ps
T842 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1914611194 Jul 12 05:42:47 PM PDT 24 Jul 12 05:42:49 PM PDT 24 177715750 ps
T843 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2975711916 Jul 12 05:43:09 PM PDT 24 Jul 12 05:43:11 PM PDT 24 133127016 ps
T844 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1302665523 Jul 12 05:42:55 PM PDT 24 Jul 12 05:42:58 PM PDT 24 62281612 ps
T845 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3003740350 Jul 12 05:42:53 PM PDT 24 Jul 12 05:42:55 PM PDT 24 104949932 ps
T846 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1752126887 Jul 12 05:42:52 PM PDT 24 Jul 12 05:42:55 PM PDT 24 74244576 ps
T847 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2611911480 Jul 12 05:42:53 PM PDT 24 Jul 12 05:42:56 PM PDT 24 112542085 ps
T848 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4117469480 Jul 12 05:43:03 PM PDT 24 Jul 12 05:43:04 PM PDT 24 120957591 ps
T849 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1823124138 Jul 12 05:42:51 PM PDT 24 Jul 12 05:42:54 PM PDT 24 85072828 ps
T850 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.750177061 Jul 12 05:43:12 PM PDT 24 Jul 12 05:43:14 PM PDT 24 167164543 ps
T851 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3196204284 Jul 12 05:43:09 PM PDT 24 Jul 12 05:43:11 PM PDT 24 255553945 ps
T852 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.152070194 Jul 12 05:42:50 PM PDT 24 Jul 12 05:42:53 PM PDT 24 429410845 ps
T853 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3336050620 Jul 12 05:42:50 PM PDT 24 Jul 12 05:42:52 PM PDT 24 95141452 ps
T854 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1118333213 Jul 12 05:42:51 PM PDT 24 Jul 12 05:42:53 PM PDT 24 87797678 ps
T855 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.113120716 Jul 12 05:42:49 PM PDT 24 Jul 12 05:42:51 PM PDT 24 449729634 ps
T856 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3490965354 Jul 12 05:43:11 PM PDT 24 Jul 12 05:43:13 PM PDT 24 125887600 ps
T857 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3308592778 Jul 12 05:42:47 PM PDT 24 Jul 12 05:42:49 PM PDT 24 445891172 ps
T858 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.673783975 Jul 12 05:43:00 PM PDT 24 Jul 12 05:43:02 PM PDT 24 166179207 ps
T859 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3135484802 Jul 12 05:42:59 PM PDT 24 Jul 12 05:43:01 PM PDT 24 52847396 ps
T860 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3222646937 Jul 12 05:42:49 PM PDT 24 Jul 12 05:42:52 PM PDT 24 653504866 ps
T861 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1081034965 Jul 12 05:43:08 PM PDT 24 Jul 12 05:43:10 PM PDT 24 50142750 ps
T862 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1622393696 Jul 12 05:42:49 PM PDT 24 Jul 12 05:42:51 PM PDT 24 44091807 ps
T863 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2017061271 Jul 12 05:42:48 PM PDT 24 Jul 12 05:42:50 PM PDT 24 798078489 ps
T864 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1346231859 Jul 12 05:42:58 PM PDT 24 Jul 12 05:43:01 PM PDT 24 82528734 ps
T865 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2740848790 Jul 12 05:43:00 PM PDT 24 Jul 12 05:43:02 PM PDT 24 141113056 ps
T866 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.24616917 Jul 12 05:43:07 PM PDT 24 Jul 12 05:43:10 PM PDT 24 56976915 ps
T867 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3749446049 Jul 12 05:42:53 PM PDT 24 Jul 12 05:42:55 PM PDT 24 57531584 ps
T868 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3638252703 Jul 12 05:43:06 PM PDT 24 Jul 12 05:43:08 PM PDT 24 1447576072 ps
T869 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1744314211 Jul 12 05:42:54 PM PDT 24 Jul 12 05:42:57 PM PDT 24 163405262 ps
T870 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3772046442 Jul 12 05:42:48 PM PDT 24 Jul 12 05:42:50 PM PDT 24 56738283 ps
T871 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.235614258 Jul 12 05:42:48 PM PDT 24 Jul 12 05:42:50 PM PDT 24 48170588 ps
T872 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2149903004 Jul 12 05:43:01 PM PDT 24 Jul 12 05:43:02 PM PDT 24 449851792 ps
T873 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.783237019 Jul 12 05:42:54 PM PDT 24 Jul 12 05:42:56 PM PDT 24 60053339 ps
T874 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4006182085 Jul 12 05:42:55 PM PDT 24 Jul 12 05:42:58 PM PDT 24 86089832 ps
T875 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2191257857 Jul 12 05:43:06 PM PDT 24 Jul 12 05:43:08 PM PDT 24 103097886 ps
T876 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1534082842 Jul 12 05:42:51 PM PDT 24 Jul 12 05:42:53 PM PDT 24 44039230 ps
T877 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3375364090 Jul 12 05:42:49 PM PDT 24 Jul 12 05:42:52 PM PDT 24 76596094 ps
T878 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3527201244 Jul 12 05:43:06 PM PDT 24 Jul 12 05:43:08 PM PDT 24 63741689 ps
T879 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3749955296 Jul 12 05:42:54 PM PDT 24 Jul 12 05:42:57 PM PDT 24 54203040 ps
T880 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1552846986 Jul 12 05:42:53 PM PDT 24 Jul 12 05:42:56 PM PDT 24 37230882 ps
T881 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.118444989 Jul 12 05:42:55 PM PDT 24 Jul 12 05:42:58 PM PDT 24 195889003 ps
T882 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.296143932 Jul 12 05:43:07 PM PDT 24 Jul 12 05:43:10 PM PDT 24 133859425 ps
T883 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.20133277 Jul 12 05:42:50 PM PDT 24 Jul 12 05:42:53 PM PDT 24 197807236 ps
T884 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1041165721 Jul 12 05:42:59 PM PDT 24 Jul 12 05:43:01 PM PDT 24 69991328 ps
T885 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1249674130 Jul 12 05:43:06 PM PDT 24 Jul 12 05:43:08 PM PDT 24 28125414 ps
T886 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3088560477 Jul 12 05:43:08 PM PDT 24 Jul 12 05:43:10 PM PDT 24 20806503 ps
T887 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3752807196 Jul 12 05:42:54 PM PDT 24 Jul 12 05:42:57 PM PDT 24 491891170 ps
T888 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3799389922 Jul 12 05:42:51 PM PDT 24 Jul 12 05:42:53 PM PDT 24 208217389 ps
T889 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.97907136 Jul 12 05:43:07 PM PDT 24 Jul 12 05:43:10 PM PDT 24 1329534027 ps
T890 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1943536134 Jul 12 05:42:47 PM PDT 24 Jul 12 05:42:50 PM PDT 24 41373094 ps
T891 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2591801221 Jul 12 05:42:49 PM PDT 24 Jul 12 05:42:52 PM PDT 24 194627003 ps
T892 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1759612921 Jul 12 05:43:02 PM PDT 24 Jul 12 05:43:04 PM PDT 24 219518169 ps
T893 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1440083740 Jul 12 05:42:58 PM PDT 24 Jul 12 05:43:00 PM PDT 24 113044104 ps
T894 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1991074520 Jul 12 05:43:08 PM PDT 24 Jul 12 05:43:10 PM PDT 24 54747002 ps
T895 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3848370725 Jul 12 05:42:49 PM PDT 24 Jul 12 05:42:51 PM PDT 24 100800531 ps
T896 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1718264549 Jul 12 05:43:00 PM PDT 24 Jul 12 05:43:02 PM PDT 24 102646324 ps
T897 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1739619297 Jul 12 05:43:07 PM PDT 24 Jul 12 05:43:09 PM PDT 24 200412643 ps
T898 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2918981346 Jul 12 05:43:13 PM PDT 24 Jul 12 05:43:15 PM PDT 24 117040703 ps
T899 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4137325827 Jul 12 05:42:56 PM PDT 24 Jul 12 05:42:58 PM PDT 24 31930851 ps
T900 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2227052300 Jul 12 05:42:54 PM PDT 24 Jul 12 05:42:57 PM PDT 24 73128398 ps
T901 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.74550739 Jul 12 05:42:54 PM PDT 24 Jul 12 05:42:57 PM PDT 24 258804561 ps
T902 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.110909917 Jul 12 05:42:54 PM PDT 24 Jul 12 05:42:56 PM PDT 24 91041221 ps
T903 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1280786297 Jul 12 05:42:57 PM PDT 24 Jul 12 05:42:59 PM PDT 24 277910254 ps
T904 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1163802309 Jul 12 05:43:01 PM PDT 24 Jul 12 05:43:02 PM PDT 24 115702458 ps
T905 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.753179542 Jul 12 05:43:08 PM PDT 24 Jul 12 05:43:10 PM PDT 24 35265407 ps
T906 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3652536391 Jul 12 05:42:50 PM PDT 24 Jul 12 05:42:52 PM PDT 24 84119806 ps
T907 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3553966033 Jul 12 05:42:51 PM PDT 24 Jul 12 05:42:53 PM PDT 24 263708821 ps
T908 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2616638536 Jul 12 05:43:06 PM PDT 24 Jul 12 05:43:09 PM PDT 24 76514619 ps
T909 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2877261668 Jul 12 05:43:07 PM PDT 24 Jul 12 05:43:10 PM PDT 24 140515804 ps
T910 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1653273900 Jul 12 05:42:54 PM PDT 24 Jul 12 05:42:57 PM PDT 24 85762668 ps
T911 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.920638675 Jul 12 05:43:06 PM PDT 24 Jul 12 05:43:08 PM PDT 24 35128365 ps
T912 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3910075349 Jul 12 05:43:02 PM PDT 24 Jul 12 05:43:04 PM PDT 24 51250392 ps
T913 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3473293597 Jul 12 05:43:11 PM PDT 24 Jul 12 05:43:13 PM PDT 24 57696994 ps
T914 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.131786632 Jul 12 05:42:49 PM PDT 24 Jul 12 05:42:52 PM PDT 24 88045509 ps
T915 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4156454619 Jul 12 05:43:08 PM PDT 24 Jul 12 05:43:10 PM PDT 24 201433791 ps
T916 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3373925964 Jul 12 05:42:53 PM PDT 24 Jul 12 05:42:55 PM PDT 24 101313019 ps
T917 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2443906372 Jul 12 05:42:49 PM PDT 24 Jul 12 05:42:51 PM PDT 24 72460707 ps
T918 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3106124564 Jul 12 05:42:58 PM PDT 24 Jul 12 05:43:00 PM PDT 24 25353384 ps
T919 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3543860739 Jul 12 05:43:08 PM PDT 24 Jul 12 05:43:10 PM PDT 24 335719821 ps
T920 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.889475042 Jul 12 05:42:53 PM PDT 24 Jul 12 05:42:56 PM PDT 24 287361942 ps
T921 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.11530243 Jul 12 05:42:59 PM PDT 24 Jul 12 05:43:01 PM PDT 24 59594248 ps
T922 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.828691149 Jul 12 05:42:52 PM PDT 24 Jul 12 05:42:54 PM PDT 24 30282836 ps
T923 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2807622853 Jul 12 05:43:09 PM PDT 24 Jul 12 05:43:11 PM PDT 24 331307801 ps
T924 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4097423483 Jul 12 05:43:01 PM PDT 24 Jul 12 05:43:02 PM PDT 24 221110971 ps
T925 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2853043590 Jul 12 05:42:54 PM PDT 24 Jul 12 05:42:57 PM PDT 24 144698282 ps
T926 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.914669222 Jul 12 05:43:03 PM PDT 24 Jul 12 05:43:05 PM PDT 24 185384445 ps
T927 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2883972262 Jul 12 05:42:54 PM PDT 24 Jul 12 05:42:56 PM PDT 24 31663455 ps
T928 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3301787663 Jul 12 05:43:10 PM PDT 24 Jul 12 05:43:12 PM PDT 24 74940014 ps
T929 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.365013734 Jul 12 05:42:54 PM PDT 24 Jul 12 05:42:58 PM PDT 24 95966111 ps
T930 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2116261320 Jul 12 05:43:09 PM PDT 24 Jul 12 05:43:11 PM PDT 24 89809161 ps
T931 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2890768327 Jul 12 05:43:07 PM PDT 24 Jul 12 05:43:09 PM PDT 24 549870848 ps
T932 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3617299972 Jul 12 05:42:53 PM PDT 24 Jul 12 05:42:56 PM PDT 24 494339785 ps
T933 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2949180749 Jul 12 05:42:56 PM PDT 24 Jul 12 05:42:59 PM PDT 24 86753157 ps
T934 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3785900795 Jul 12 05:43:00 PM PDT 24 Jul 12 05:43:02 PM PDT 24 121671143 ps
T935 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3862542368 Jul 12 05:43:03 PM PDT 24 Jul 12 05:43:05 PM PDT 24 70155763 ps
T936 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3839147851 Jul 12 05:43:05 PM PDT 24 Jul 12 05:43:07 PM PDT 24 327811112 ps
T937 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2830254430 Jul 12 05:42:54 PM PDT 24 Jul 12 05:42:57 PM PDT 24 124338653 ps
T938 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1294624640 Jul 12 05:43:10 PM PDT 24 Jul 12 05:43:12 PM PDT 24 363624783 ps
T939 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3933311999 Jul 12 05:42:53 PM PDT 24 Jul 12 05:42:55 PM PDT 24 90221304 ps
T940 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3691968310 Jul 12 05:42:52 PM PDT 24 Jul 12 05:42:54 PM PDT 24 219676958 ps
T941 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.990538353 Jul 12 05:42:54 PM PDT 24 Jul 12 05:42:56 PM PDT 24 76856454 ps

Test location /workspace/coverage/default/7.gpio_full_random.830271420
Short name T24
Test name
Test status
Simulation time 56011068 ps
CPU time 0.74 seconds
Started Jul 12 05:43:30 PM PDT 24
Finished Jul 12 05:43:31 PM PDT 24
Peak memory 197160 kb
Host smart-78561285-8fa3-4c78-92c7-20d7b2bc9875
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830271420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.830271420
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3119393008
Short name T11
Test name
Test status
Simulation time 56612488 ps
CPU time 2.45 seconds
Started Jul 12 05:44:31 PM PDT 24
Finished Jul 12 05:44:35 PM PDT 24
Peak memory 198716 kb
Host smart-16b6e2cc-36ca-4de9-a9dc-2e57c5431bfd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119393008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3119393008
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_stress_all.233211435
Short name T1
Test name
Test status
Simulation time 12700665308 ps
CPU time 145.22 seconds
Started Jul 12 05:43:30 PM PDT 24
Finished Jul 12 05:45:57 PM PDT 24
Peak memory 198800 kb
Host smart-48ee9c22-8ec9-4699-9313-ce737654e36d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233211435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.233211435
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.3833215627
Short name T61
Test name
Test status
Simulation time 487472837493 ps
CPU time 2400.75 seconds
Started Jul 12 05:44:14 PM PDT 24
Finished Jul 12 06:24:16 PM PDT 24
Peak memory 198800 kb
Host smart-425417a6-e386-4669-b65d-b3bdcb7dba5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3833215627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.3833215627
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1822966273
Short name T34
Test name
Test status
Simulation time 391766514 ps
CPU time 1.44 seconds
Started Jul 12 05:42:37 PM PDT 24
Finished Jul 12 05:42:39 PM PDT 24
Peak memory 198756 kb
Host smart-e2e7aece-75c1-4b8b-b09f-1bd440d0f3e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822966273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1822966273
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.549911046
Short name T162
Test name
Test status
Simulation time 16007147 ps
CPU time 0.56 seconds
Started Jul 12 05:43:12 PM PDT 24
Finished Jul 12 05:43:13 PM PDT 24
Peak memory 195508 kb
Host smart-0185661c-3de2-49a6-a668-d4f12dc9667d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549911046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.549911046
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1946583395
Short name T37
Test name
Test status
Simulation time 54764185 ps
CPU time 0.95 seconds
Started Jul 12 05:43:13 PM PDT 24
Finished Jul 12 05:43:15 PM PDT 24
Peak memory 214228 kb
Host smart-a6943071-5d87-41aa-8cf0-5fbc24913142
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946583395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1946583395
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.824729181
Short name T86
Test name
Test status
Simulation time 17052879 ps
CPU time 0.66 seconds
Started Jul 12 05:41:34 PM PDT 24
Finished Jul 12 05:41:36 PM PDT 24
Peak memory 195460 kb
Host smart-c4632c54-46bb-4074-9249-932b3dd41a9d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824729181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.824729181
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3270632890
Short name T103
Test name
Test status
Simulation time 65321672 ps
CPU time 0.79 seconds
Started Jul 12 05:42:19 PM PDT 24
Finished Jul 12 05:42:21 PM PDT 24
Peak memory 196672 kb
Host smart-c33c6160-406f-4607-a838-0eaa2ab859db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270632890 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3270632890
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1851745812
Short name T812
Test name
Test status
Simulation time 686057500 ps
CPU time 1.49 seconds
Started Jul 12 05:42:21 PM PDT 24
Finished Jul 12 05:42:23 PM PDT 24
Peak memory 198708 kb
Host smart-eb9e1601-16a1-43f8-b742-60ed78ada2d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851745812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1851745812
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3439787426
Short name T45
Test name
Test status
Simulation time 152683607 ps
CPU time 1.08 seconds
Started Jul 12 05:42:28 PM PDT 24
Finished Jul 12 05:42:31 PM PDT 24
Peak memory 198744 kb
Host smart-f909318a-cac5-4e32-ae2e-9171f4358454
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439787426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.3439787426
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1954333895
Short name T83
Test name
Test status
Simulation time 476222850 ps
CPU time 0.86 seconds
Started Jul 12 05:41:34 PM PDT 24
Finished Jul 12 05:41:35 PM PDT 24
Peak memory 196640 kb
Host smart-6bfde3cf-1545-4eb2-9ebf-1906614f5363
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954333895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1954333895
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2117754549
Short name T828
Test name
Test status
Simulation time 35089777 ps
CPU time 1.36 seconds
Started Jul 12 05:41:41 PM PDT 24
Finished Jul 12 05:41:43 PM PDT 24
Peak memory 197328 kb
Host smart-a92bcf86-15d6-46ab-a59a-c51ee4ef0708
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117754549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2117754549
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.230692931
Short name T89
Test name
Test status
Simulation time 15002466 ps
CPU time 0.6 seconds
Started Jul 12 05:41:42 PM PDT 24
Finished Jul 12 05:41:44 PM PDT 24
Peak memory 195260 kb
Host smart-08ddf8ea-dbfd-44e3-86d2-08e9f988f96f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230692931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.230692931
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1693220260
Short name T808
Test name
Test status
Simulation time 29668935 ps
CPU time 0.69 seconds
Started Jul 12 05:41:34 PM PDT 24
Finished Jul 12 05:41:35 PM PDT 24
Peak memory 197752 kb
Host smart-d578ba81-ab32-4981-a0bf-12c30d1faa83
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693220260 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1693220260
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3613648016
Short name T726
Test name
Test status
Simulation time 14422463 ps
CPU time 0.63 seconds
Started Jul 12 05:41:42 PM PDT 24
Finished Jul 12 05:41:44 PM PDT 24
Peak memory 194420 kb
Host smart-dc97ccea-52b2-4d04-abfe-e52a55509c48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613648016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3613648016
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3338345472
Short name T777
Test name
Test status
Simulation time 30353063 ps
CPU time 0.75 seconds
Started Jul 12 05:41:36 PM PDT 24
Finished Jul 12 05:41:37 PM PDT 24
Peak memory 195724 kb
Host smart-ae49f977-e7a8-4d84-9f6d-6d79efac884f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338345472 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3338345472
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3962987206
Short name T745
Test name
Test status
Simulation time 816947948 ps
CPU time 3.07 seconds
Started Jul 12 05:41:34 PM PDT 24
Finished Jul 12 05:41:37 PM PDT 24
Peak memory 198632 kb
Host smart-e8af4d17-c29c-4650-b698-7424a21752b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962987206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3962987206
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.107359921
Short name T744
Test name
Test status
Simulation time 142750391 ps
CPU time 1.16 seconds
Started Jul 12 05:41:33 PM PDT 24
Finished Jul 12 05:41:35 PM PDT 24
Peak memory 198756 kb
Host smart-541ff931-abff-4826-86eb-f1b835a29d5a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107359921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.107359921
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.39751483
Short name T94
Test name
Test status
Simulation time 28725965 ps
CPU time 0.81 seconds
Started Jul 12 05:41:42 PM PDT 24
Finished Jul 12 05:41:43 PM PDT 24
Peak memory 196724 kb
Host smart-50e64044-bce0-413f-8a90-2866087a3912
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39751483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
gpio_csr_aliasing.39751483
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.521838461
Short name T98
Test name
Test status
Simulation time 1680801816 ps
CPU time 3.32 seconds
Started Jul 12 05:41:41 PM PDT 24
Finished Jul 12 05:41:44 PM PDT 24
Peak memory 198688 kb
Host smart-effc2b42-b790-4cbd-bee5-b139e68ec9b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521838461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.521838461
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2353639290
Short name T91
Test name
Test status
Simulation time 27670813 ps
CPU time 0.63 seconds
Started Jul 12 05:41:42 PM PDT 24
Finished Jul 12 05:41:43 PM PDT 24
Peak memory 195968 kb
Host smart-2049757b-82d1-446a-b8ca-34e54a241cac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353639290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2353639290
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1458056348
Short name T729
Test name
Test status
Simulation time 181098068 ps
CPU time 0.93 seconds
Started Jul 12 05:44:29 PM PDT 24
Finished Jul 12 05:44:33 PM PDT 24
Peak memory 198492 kb
Host smart-8fd31add-2441-4a66-b401-39357b3fb198
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458056348 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1458056348
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.889106191
Short name T782
Test name
Test status
Simulation time 34761356 ps
CPU time 0.56 seconds
Started Jul 12 05:41:43 PM PDT 24
Finished Jul 12 05:41:45 PM PDT 24
Peak memory 195460 kb
Host smart-de998295-89ea-4c2c-8d09-cc649d563280
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889106191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_
csr_rw.889106191
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.692246719
Short name T731
Test name
Test status
Simulation time 20909908 ps
CPU time 0.6 seconds
Started Jul 12 05:41:41 PM PDT 24
Finished Jul 12 05:41:42 PM PDT 24
Peak memory 194444 kb
Host smart-93642673-218d-463b-a4af-dc2c1919d49a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692246719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.692246719
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1096103633
Short name T809
Test name
Test status
Simulation time 179466623 ps
CPU time 0.63 seconds
Started Jul 12 05:41:42 PM PDT 24
Finished Jul 12 05:41:44 PM PDT 24
Peak memory 195452 kb
Host smart-08946193-7cc0-4b9f-95de-2de67ee2779b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096103633 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1096103633
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.4083628370
Short name T716
Test name
Test status
Simulation time 387549765 ps
CPU time 2.11 seconds
Started Jul 12 05:41:44 PM PDT 24
Finished Jul 12 05:41:47 PM PDT 24
Peak memory 198728 kb
Host smart-ac8a1298-f073-4795-8dec-09ccb14068b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083628370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.4083628370
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3216541283
Short name T824
Test name
Test status
Simulation time 133155695 ps
CPU time 1.44 seconds
Started Jul 12 05:41:41 PM PDT 24
Finished Jul 12 05:41:43 PM PDT 24
Peak memory 198832 kb
Host smart-c50e8962-c45d-4b11-b879-a4d2c415b802
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216541283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3216541283
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2607297486
Short name T825
Test name
Test status
Simulation time 38863102 ps
CPU time 1.61 seconds
Started Jul 12 05:42:21 PM PDT 24
Finished Jul 12 05:42:23 PM PDT 24
Peak memory 198768 kb
Host smart-0c63e5bc-763a-4be3-8f44-ca60236820a9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607297486 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2607297486
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3294963381
Short name T99
Test name
Test status
Simulation time 41131050 ps
CPU time 0.64 seconds
Started Jul 12 05:42:19 PM PDT 24
Finished Jul 12 05:42:20 PM PDT 24
Peak memory 196236 kb
Host smart-e7bce5a1-bff0-41c9-b067-2d7202bdeab2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294963381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3294963381
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.274237363
Short name T816
Test name
Test status
Simulation time 23627129 ps
CPU time 0.6 seconds
Started Jul 12 05:42:17 PM PDT 24
Finished Jul 12 05:42:18 PM PDT 24
Peak memory 194352 kb
Host smart-71431b67-f315-4788-9bed-af7e5b87b967
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274237363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.274237363
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2717047849
Short name T760
Test name
Test status
Simulation time 180143477 ps
CPU time 2.83 seconds
Started Jul 12 05:42:17 PM PDT 24
Finished Jul 12 05:42:21 PM PDT 24
Peak memory 198920 kb
Host smart-52e813b6-4929-43da-9219-da0553088f54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717047849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2717047849
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.392735777
Short name T47
Test name
Test status
Simulation time 406445219 ps
CPU time 1.41 seconds
Started Jul 12 05:42:19 PM PDT 24
Finished Jul 12 05:42:21 PM PDT 24
Peak memory 198696 kb
Host smart-da1bc179-ceb9-4df2-8b4f-445541bc2e7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392735777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.392735777
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1964618523
Short name T786
Test name
Test status
Simulation time 85526846 ps
CPU time 0.74 seconds
Started Jul 12 05:42:20 PM PDT 24
Finished Jul 12 05:42:21 PM PDT 24
Peak memory 198548 kb
Host smart-1c125073-f3a3-4503-98f5-54e490c406b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964618523 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1964618523
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.809742997
Short name T110
Test name
Test status
Simulation time 45983816 ps
CPU time 0.64 seconds
Started Jul 12 05:42:20 PM PDT 24
Finished Jul 12 05:42:22 PM PDT 24
Peak memory 195340 kb
Host smart-e5a120ca-fb7f-4ea5-8e83-ac73e834701e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809742997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.809742997
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1033919502
Short name T727
Test name
Test status
Simulation time 18110000 ps
CPU time 0.58 seconds
Started Jul 12 05:42:30 PM PDT 24
Finished Jul 12 05:42:31 PM PDT 24
Peak memory 194296 kb
Host smart-1eb22b2b-8b14-4725-b757-7738fbb9a297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033919502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1033919502
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.51239036
Short name T109
Test name
Test status
Simulation time 76962565 ps
CPU time 0.68 seconds
Started Jul 12 05:42:18 PM PDT 24
Finished Jul 12 05:42:19 PM PDT 24
Peak memory 195480 kb
Host smart-40874529-5991-41b8-b31b-d0b7eccda0b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51239036 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.gpio_same_csr_outstanding.51239036
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2432479153
Short name T797
Test name
Test status
Simulation time 411548311 ps
CPU time 2.19 seconds
Started Jul 12 05:42:27 PM PDT 24
Finished Jul 12 05:42:31 PM PDT 24
Peak memory 198716 kb
Host smart-ebd98636-913b-4a9d-ac45-af10682ec2e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432479153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2432479153
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3775543991
Short name T818
Test name
Test status
Simulation time 540616299 ps
CPU time 1.38 seconds
Started Jul 12 05:42:18 PM PDT 24
Finished Jul 12 05:42:20 PM PDT 24
Peak memory 198632 kb
Host smart-cc5cd040-6615-421a-ba94-d4162d0caf4a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775543991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3775543991
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3228842536
Short name T799
Test name
Test status
Simulation time 43922253 ps
CPU time 0.97 seconds
Started Jul 12 05:42:27 PM PDT 24
Finished Jul 12 05:42:29 PM PDT 24
Peak memory 198548 kb
Host smart-42a156f8-0b94-4e0a-8aeb-99bd0e2dcd38
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228842536 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3228842536
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1314566308
Short name T101
Test name
Test status
Simulation time 50501323 ps
CPU time 0.58 seconds
Started Jul 12 05:42:26 PM PDT 24
Finished Jul 12 05:42:27 PM PDT 24
Peak memory 194928 kb
Host smart-9792dfa9-037f-448a-b07f-9c90ead8c036
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314566308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1314566308
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1665997127
Short name T792
Test name
Test status
Simulation time 14280520 ps
CPU time 0.6 seconds
Started Jul 12 05:42:29 PM PDT 24
Finished Jul 12 05:42:31 PM PDT 24
Peak memory 194312 kb
Host smart-e2b8b1ac-23f1-4d69-82dc-2057b10882b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665997127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1665997127
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1867781462
Short name T823
Test name
Test status
Simulation time 40099440 ps
CPU time 0.75 seconds
Started Jul 12 05:42:28 PM PDT 24
Finished Jul 12 05:42:30 PM PDT 24
Peak memory 196468 kb
Host smart-077e3204-3325-4052-a87a-4684fb22e017
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867781462 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.1867781462
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2605164860
Short name T807
Test name
Test status
Simulation time 146589166 ps
CPU time 1.56 seconds
Started Jul 12 05:42:27 PM PDT 24
Finished Jul 12 05:42:29 PM PDT 24
Peak memory 198704 kb
Host smart-384ee085-1b04-479d-966b-32dedf121762
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605164860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2605164860
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2021044521
Short name T817
Test name
Test status
Simulation time 92899482 ps
CPU time 0.86 seconds
Started Jul 12 05:42:29 PM PDT 24
Finished Jul 12 05:42:31 PM PDT 24
Peak memory 198204 kb
Host smart-df19e308-5431-4e63-ac2b-03a5ccd9ab05
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021044521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2021044521
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2389363384
Short name T728
Test name
Test status
Simulation time 30899677 ps
CPU time 0.73 seconds
Started Jul 12 05:42:27 PM PDT 24
Finished Jul 12 05:42:29 PM PDT 24
Peak memory 198600 kb
Host smart-2e827041-75f3-4dbf-8d21-f9573b3cba88
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389363384 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2389363384
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3601500625
Short name T756
Test name
Test status
Simulation time 13464842 ps
CPU time 0.62 seconds
Started Jul 12 05:42:28 PM PDT 24
Finished Jul 12 05:42:31 PM PDT 24
Peak memory 196132 kb
Host smart-a0b76d06-93d1-4807-aec3-c4a3a77942a9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601500625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3601500625
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1128945448
Short name T720
Test name
Test status
Simulation time 27564213 ps
CPU time 0.6 seconds
Started Jul 12 05:42:27 PM PDT 24
Finished Jul 12 05:42:29 PM PDT 24
Peak memory 194292 kb
Host smart-1d871120-1fe1-4096-ab00-f906edebca83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128945448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1128945448
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1523065571
Short name T765
Test name
Test status
Simulation time 19270316 ps
CPU time 0.63 seconds
Started Jul 12 05:42:30 PM PDT 24
Finished Jul 12 05:42:32 PM PDT 24
Peak memory 194932 kb
Host smart-a8c07572-8453-4f0d-9ec2-857fd150d8f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523065571 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1523065571
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1030217928
Short name T791
Test name
Test status
Simulation time 681416819 ps
CPU time 2.7 seconds
Started Jul 12 05:42:27 PM PDT 24
Finished Jul 12 05:42:31 PM PDT 24
Peak memory 198744 kb
Host smart-4f2c9f60-c81d-429a-ac60-e132fc5787f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030217928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1030217928
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3425837782
Short name T779
Test name
Test status
Simulation time 24430781 ps
CPU time 0.8 seconds
Started Jul 12 05:42:31 PM PDT 24
Finished Jul 12 05:42:33 PM PDT 24
Peak memory 198616 kb
Host smart-a5c28e88-e861-45ed-8df6-2588662d9224
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425837782 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3425837782
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2938397812
Short name T90
Test name
Test status
Simulation time 47456391 ps
CPU time 0.61 seconds
Started Jul 12 05:42:29 PM PDT 24
Finished Jul 12 05:42:31 PM PDT 24
Peak memory 196240 kb
Host smart-2a5e9dd1-6e1e-4e9f-b575-7a95c0941e62
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938397812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2938397812
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3732462665
Short name T770
Test name
Test status
Simulation time 21706327 ps
CPU time 0.61 seconds
Started Jul 12 05:42:28 PM PDT 24
Finished Jul 12 05:42:30 PM PDT 24
Peak memory 194464 kb
Host smart-2483bd94-0a42-4870-a822-988518b63ca2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732462665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3732462665
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.4255072194
Short name T826
Test name
Test status
Simulation time 117409024 ps
CPU time 0.93 seconds
Started Jul 12 05:42:31 PM PDT 24
Finished Jul 12 05:42:33 PM PDT 24
Peak memory 197800 kb
Host smart-d4d59500-01d8-4510-a18d-f243737bd9ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255072194 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.4255072194
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2040008833
Short name T750
Test name
Test status
Simulation time 120306695 ps
CPU time 2.69 seconds
Started Jul 12 05:42:28 PM PDT 24
Finished Jul 12 05:42:32 PM PDT 24
Peak memory 198948 kb
Host smart-ffcef6e3-e670-40b5-ac51-59e3653715d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040008833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2040008833
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.258509254
Short name T35
Test name
Test status
Simulation time 89875151 ps
CPU time 1.43 seconds
Started Jul 12 05:42:29 PM PDT 24
Finished Jul 12 05:42:32 PM PDT 24
Peak memory 198684 kb
Host smart-a968d24d-d0dc-4198-b0bb-fdc041fd9446
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258509254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.258509254
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2921120731
Short name T839
Test name
Test status
Simulation time 35846561 ps
CPU time 0.96 seconds
Started Jul 12 05:42:29 PM PDT 24
Finished Jul 12 05:42:31 PM PDT 24
Peak memory 198596 kb
Host smart-9d57cf7e-d807-42bf-96a6-29e59ad9be22
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921120731 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2921120731
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1746499714
Short name T780
Test name
Test status
Simulation time 15124174 ps
CPU time 0.58 seconds
Started Jul 12 05:42:27 PM PDT 24
Finished Jul 12 05:42:30 PM PDT 24
Peak memory 193996 kb
Host smart-2f28fc1e-77eb-4996-abaa-55d3f02b8f39
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746499714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1746499714
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2832836114
Short name T804
Test name
Test status
Simulation time 12987120 ps
CPU time 0.58 seconds
Started Jul 12 05:42:27 PM PDT 24
Finished Jul 12 05:42:30 PM PDT 24
Peak memory 194256 kb
Host smart-ea521c84-d960-4fd8-8e69-7ec08732973a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832836114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2832836114
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1566837104
Short name T102
Test name
Test status
Simulation time 42294679 ps
CPU time 0.65 seconds
Started Jul 12 05:42:27 PM PDT 24
Finished Jul 12 05:42:29 PM PDT 24
Peak memory 195748 kb
Host smart-e263a98e-b0ce-4521-a8dd-03b5072366f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566837104 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1566837104
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2651543866
Short name T769
Test name
Test status
Simulation time 174697438 ps
CPU time 2.4 seconds
Started Jul 12 05:42:26 PM PDT 24
Finished Jul 12 05:42:29 PM PDT 24
Peak memory 198688 kb
Host smart-6f39aeb7-a957-459a-95a0-ca5cb8b2b7cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651543866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2651543866
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.978699450
Short name T36
Test name
Test status
Simulation time 441149852 ps
CPU time 1.44 seconds
Started Jul 12 05:42:27 PM PDT 24
Finished Jul 12 05:42:29 PM PDT 24
Peak memory 198648 kb
Host smart-7e81994d-76d0-4066-9c42-476b9b5df9e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978699450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.978699450
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.4109927123
Short name T741
Test name
Test status
Simulation time 33838127 ps
CPU time 1.31 seconds
Started Jul 12 05:42:34 PM PDT 24
Finished Jul 12 05:42:36 PM PDT 24
Peak memory 198688 kb
Host smart-3204a091-6db0-46ee-bea8-20884427bb55
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109927123 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.4109927123
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2925088072
Short name T761
Test name
Test status
Simulation time 19388587 ps
CPU time 0.62 seconds
Started Jul 12 05:42:27 PM PDT 24
Finished Jul 12 05:42:30 PM PDT 24
Peak memory 195768 kb
Host smart-d2089e5d-ce76-4c8b-a575-c576a4a5fad4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925088072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2925088072
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3468184207
Short name T775
Test name
Test status
Simulation time 39437936 ps
CPU time 0.59 seconds
Started Jul 12 05:42:34 PM PDT 24
Finished Jul 12 05:42:35 PM PDT 24
Peak memory 194336 kb
Host smart-38476553-e1ff-49d9-bdd4-928c30571031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468184207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3468184207
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2665205042
Short name T81
Test name
Test status
Simulation time 78150066 ps
CPU time 0.89 seconds
Started Jul 12 05:42:30 PM PDT 24
Finished Jul 12 05:42:32 PM PDT 24
Peak memory 197780 kb
Host smart-dac09bd4-3a6c-4664-95ee-7f44f64e3400
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665205042 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2665205042
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.888532854
Short name T764
Test name
Test status
Simulation time 520049079 ps
CPU time 2.32 seconds
Started Jul 12 05:42:38 PM PDT 24
Finished Jul 12 05:42:42 PM PDT 24
Peak memory 198708 kb
Host smart-5bb2e08c-276f-4419-92ce-790e6a1d98be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888532854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.888532854
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.4096771361
Short name T766
Test name
Test status
Simulation time 298299343 ps
CPU time 1.14 seconds
Started Jul 12 05:42:37 PM PDT 24
Finished Jul 12 05:42:39 PM PDT 24
Peak memory 198708 kb
Host smart-ff4ca557-12fa-48e9-870b-901ca98dad88
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096771361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.4096771361
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.254982522
Short name T789
Test name
Test status
Simulation time 102867638 ps
CPU time 0.9 seconds
Started Jul 12 05:42:38 PM PDT 24
Finished Jul 12 05:42:39 PM PDT 24
Peak memory 198612 kb
Host smart-d862f81b-fae0-4ac7-845b-ed16fb78d113
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254982522 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.254982522
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3876678969
Short name T784
Test name
Test status
Simulation time 26378388 ps
CPU time 0.59 seconds
Started Jul 12 05:42:34 PM PDT 24
Finished Jul 12 05:42:35 PM PDT 24
Peak memory 195560 kb
Host smart-c94ae8da-1a02-44db-92d6-42fd3bd831ba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876678969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3876678969
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3857537143
Short name T754
Test name
Test status
Simulation time 35513028 ps
CPU time 0.61 seconds
Started Jul 12 05:42:40 PM PDT 24
Finished Jul 12 05:42:41 PM PDT 24
Peak memory 194968 kb
Host smart-ea5dc11b-fce1-4f58-9d1f-7358cf9f08ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857537143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3857537143
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.601506473
Short name T82
Test name
Test status
Simulation time 44435121 ps
CPU time 0.6 seconds
Started Jul 12 05:42:36 PM PDT 24
Finished Jul 12 05:42:37 PM PDT 24
Peak memory 195640 kb
Host smart-26431597-d935-4bd8-8559-7dfedcbe0cbb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601506473 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.601506473
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1771998146
Short name T759
Test name
Test status
Simulation time 85153486 ps
CPU time 2.36 seconds
Started Jul 12 05:42:35 PM PDT 24
Finished Jul 12 05:42:39 PM PDT 24
Peak memory 198780 kb
Host smart-58843719-c016-4e6b-a557-f9bb03424d45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771998146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1771998146
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1612263197
Short name T739
Test name
Test status
Simulation time 77046830 ps
CPU time 1.86 seconds
Started Jul 12 05:42:54 PM PDT 24
Finished Jul 12 05:42:57 PM PDT 24
Peak memory 198820 kb
Host smart-297a578f-4c6b-4b13-852e-8fec1ba5e8ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612263197 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.1612263197
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.38019694
Short name T819
Test name
Test status
Simulation time 16872467 ps
CPU time 0.66 seconds
Started Jul 12 05:42:36 PM PDT 24
Finished Jul 12 05:42:37 PM PDT 24
Peak memory 195512 kb
Host smart-0e93c667-8a0a-4329-bfac-962e04c03631
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38019694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_
csr_rw.38019694
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.4128375301
Short name T827
Test name
Test status
Simulation time 41638397 ps
CPU time 0.58 seconds
Started Jul 12 05:42:40 PM PDT 24
Finished Jul 12 05:42:41 PM PDT 24
Peak memory 194388 kb
Host smart-1ad0e213-1e58-4c73-b67b-51af57890767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128375301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.4128375301
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3311043385
Short name T814
Test name
Test status
Simulation time 64031681 ps
CPU time 0.7 seconds
Started Jul 12 05:42:38 PM PDT 24
Finished Jul 12 05:42:40 PM PDT 24
Peak memory 195960 kb
Host smart-0cc3655d-8bcb-4df3-b1f4-57e3d2f42a29
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311043385 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3311043385
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1062042353
Short name T721
Test name
Test status
Simulation time 70908571 ps
CPU time 1.75 seconds
Started Jul 12 05:42:38 PM PDT 24
Finished Jul 12 05:42:40 PM PDT 24
Peak memory 198708 kb
Host smart-b7c1fabe-7d1e-42a5-95d0-53711df327b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062042353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1062042353
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.4229381237
Short name T762
Test name
Test status
Simulation time 237112099 ps
CPU time 1.13 seconds
Started Jul 12 05:42:34 PM PDT 24
Finished Jul 12 05:42:35 PM PDT 24
Peak memory 198640 kb
Host smart-e4c8fb77-042c-45d3-99de-daeaa47b561e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229381237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.4229381237
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1859641006
Short name T793
Test name
Test status
Simulation time 42039157 ps
CPU time 0.99 seconds
Started Jul 12 05:42:35 PM PDT 24
Finished Jul 12 05:42:37 PM PDT 24
Peak memory 198596 kb
Host smart-646476c2-3014-4261-b653-5983ddc2862d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859641006 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1859641006
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2697057950
Short name T763
Test name
Test status
Simulation time 38116560 ps
CPU time 0.63 seconds
Started Jul 12 05:42:38 PM PDT 24
Finished Jul 12 05:42:40 PM PDT 24
Peak memory 196036 kb
Host smart-cf26ff89-c73b-45fc-aa7c-dd709c2fe397
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697057950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2697057950
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1501412607
Short name T773
Test name
Test status
Simulation time 16388812 ps
CPU time 0.6 seconds
Started Jul 12 05:42:36 PM PDT 24
Finished Jul 12 05:42:37 PM PDT 24
Peak memory 194420 kb
Host smart-924406b5-5cd9-4774-b516-8c23b86ac994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501412607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1501412607
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1691680527
Short name T795
Test name
Test status
Simulation time 60703400 ps
CPU time 0.83 seconds
Started Jul 12 05:42:38 PM PDT 24
Finished Jul 12 05:42:40 PM PDT 24
Peak memory 197600 kb
Host smart-c1d7ecb5-9bd6-4c81-ac8e-0c7ff505b826
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691680527 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1691680527
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3763319542
Short name T717
Test name
Test status
Simulation time 154417583 ps
CPU time 1.57 seconds
Started Jul 12 05:42:35 PM PDT 24
Finished Jul 12 05:42:37 PM PDT 24
Peak memory 198612 kb
Host smart-12f3d132-78ee-414c-8c99-79f17eff1c60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763319542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3763319542
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1425417036
Short name T44
Test name
Test status
Simulation time 199566278 ps
CPU time 1.31 seconds
Started Jul 12 05:42:35 PM PDT 24
Finished Jul 12 05:42:37 PM PDT 24
Peak memory 198636 kb
Host smart-59f60361-0a4e-47e3-8efd-fffb4c9c740c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425417036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1425417036
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1968809748
Short name T100
Test name
Test status
Simulation time 13649026 ps
CPU time 0.66 seconds
Started Jul 12 05:41:50 PM PDT 24
Finished Jul 12 05:41:51 PM PDT 24
Peak memory 195616 kb
Host smart-b57a8963-8eaa-4ea8-a026-2e1b0f184ffc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968809748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1968809748
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1390518857
Short name T96
Test name
Test status
Simulation time 145626503 ps
CPU time 2.21 seconds
Started Jul 12 05:41:50 PM PDT 24
Finished Jul 12 05:41:52 PM PDT 24
Peak memory 197860 kb
Host smart-9c010b53-bfbf-4f88-9140-ba79334687ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390518857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1390518857
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.907410532
Short name T740
Test name
Test status
Simulation time 51229201 ps
CPU time 0.64 seconds
Started Jul 12 05:41:48 PM PDT 24
Finished Jul 12 05:41:50 PM PDT 24
Peak memory 196132 kb
Host smart-1a5f021e-c944-4c6d-8cf3-cf92aa00f6d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907410532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.907410532
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2970357309
Short name T785
Test name
Test status
Simulation time 27048164 ps
CPU time 0.74 seconds
Started Jul 12 05:41:49 PM PDT 24
Finished Jul 12 05:41:50 PM PDT 24
Peak memory 198820 kb
Host smart-b72b951d-4e92-420c-b16f-36ee596dccea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970357309 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2970357309
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1208257563
Short name T87
Test name
Test status
Simulation time 33992979 ps
CPU time 0.64 seconds
Started Jul 12 05:41:49 PM PDT 24
Finished Jul 12 05:41:50 PM PDT 24
Peak memory 195536 kb
Host smart-c25f4021-aea7-4341-8b5b-5bb7d7fa603f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208257563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1208257563
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1092944485
Short name T743
Test name
Test status
Simulation time 50504818 ps
CPU time 0.57 seconds
Started Jul 12 05:41:50 PM PDT 24
Finished Jul 12 05:41:51 PM PDT 24
Peak memory 194308 kb
Host smart-5225d57b-5a64-446f-a6f1-55ac7e5d8c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092944485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1092944485
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.50007695
Short name T107
Test name
Test status
Simulation time 156363998 ps
CPU time 0.89 seconds
Started Jul 12 05:41:49 PM PDT 24
Finished Jul 12 05:41:50 PM PDT 24
Peak memory 196912 kb
Host smart-3ffa8691-3895-4692-8504-3389a29eca58
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50007695 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.gpio_same_csr_outstanding.50007695
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2998565578
Short name T788
Test name
Test status
Simulation time 78075120 ps
CPU time 1.36 seconds
Started Jul 12 05:41:53 PM PDT 24
Finished Jul 12 05:41:55 PM PDT 24
Peak memory 198720 kb
Host smart-0d3bdeac-7abd-4e7e-8907-80e1c4c3dac0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998565578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2998565578
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3270458954
Short name T781
Test name
Test status
Simulation time 104690567 ps
CPU time 1.37 seconds
Started Jul 12 05:41:48 PM PDT 24
Finished Jul 12 05:41:50 PM PDT 24
Peak memory 198724 kb
Host smart-4512ac09-beee-44da-866e-9a8cdf3b7070
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270458954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3270458954
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2833312322
Short name T724
Test name
Test status
Simulation time 14519021 ps
CPU time 0.61 seconds
Started Jul 12 05:42:35 PM PDT 24
Finished Jul 12 05:42:36 PM PDT 24
Peak memory 195020 kb
Host smart-c6ecda34-7a0c-429b-8e3e-0a6b5915f005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833312322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2833312322
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.113848585
Short name T751
Test name
Test status
Simulation time 16688201 ps
CPU time 0.61 seconds
Started Jul 12 05:42:38 PM PDT 24
Finished Jul 12 05:42:40 PM PDT 24
Peak memory 194376 kb
Host smart-5e6ecc37-2a61-49f9-bc99-df3977694069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113848585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.113848585
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3688676443
Short name T736
Test name
Test status
Simulation time 20789625 ps
CPU time 0.57 seconds
Started Jul 12 05:42:34 PM PDT 24
Finished Jul 12 05:42:35 PM PDT 24
Peak memory 194976 kb
Host smart-b84fcb5c-5e97-4117-8fc4-39cdd9814170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688676443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3688676443
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3240748728
Short name T738
Test name
Test status
Simulation time 18907218 ps
CPU time 0.6 seconds
Started Jul 12 05:42:33 PM PDT 24
Finished Jul 12 05:42:34 PM PDT 24
Peak memory 194308 kb
Host smart-e4993a9e-249b-4eee-baf6-410446c8097d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240748728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3240748728
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1503009911
Short name T798
Test name
Test status
Simulation time 31306233 ps
CPU time 0.61 seconds
Started Jul 12 05:42:41 PM PDT 24
Finished Jul 12 05:42:43 PM PDT 24
Peak memory 194532 kb
Host smart-0e70f340-ddb7-473f-a742-57b9fdb3d71d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503009911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1503009911
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1138637220
Short name T774
Test name
Test status
Simulation time 12220533 ps
CPU time 0.58 seconds
Started Jul 12 05:42:46 PM PDT 24
Finished Jul 12 05:42:47 PM PDT 24
Peak memory 194448 kb
Host smart-b341a2de-6b09-41bc-ac9d-e52c6c71e452
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138637220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1138637220
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3878160274
Short name T800
Test name
Test status
Simulation time 45753219 ps
CPU time 0.58 seconds
Started Jul 12 05:42:43 PM PDT 24
Finished Jul 12 05:42:44 PM PDT 24
Peak memory 194276 kb
Host smart-3f420141-a15f-4eb3-9eee-114cbe2ae83e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878160274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3878160274
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1494962276
Short name T730
Test name
Test status
Simulation time 28753683 ps
CPU time 0.61 seconds
Started Jul 12 05:42:40 PM PDT 24
Finished Jul 12 05:42:41 PM PDT 24
Peak memory 195064 kb
Host smart-d7f777ae-6bf1-4344-b2da-d9db698ed49f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494962276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1494962276
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.4228445849
Short name T752
Test name
Test status
Simulation time 17545587 ps
CPU time 0.62 seconds
Started Jul 12 05:42:48 PM PDT 24
Finished Jul 12 05:42:49 PM PDT 24
Peak memory 194464 kb
Host smart-3c07aeae-8f7f-47bd-b1a6-467d739ffad8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228445849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.4228445849
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2991992757
Short name T733
Test name
Test status
Simulation time 16119633 ps
CPU time 0.55 seconds
Started Jul 12 05:42:42 PM PDT 24
Finished Jul 12 05:42:43 PM PDT 24
Peak memory 194260 kb
Host smart-8ba3eda8-3027-4947-b08d-13a131a2b8c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991992757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2991992757
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1644585539
Short name T97
Test name
Test status
Simulation time 135739245 ps
CPU time 0.73 seconds
Started Jul 12 05:41:57 PM PDT 24
Finished Jul 12 05:42:00 PM PDT 24
Peak memory 196456 kb
Host smart-1db44488-b59f-4db6-9bfd-af74b3a1efee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644585539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1644585539
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.4014011342
Short name T92
Test name
Test status
Simulation time 303488675 ps
CPU time 2.94 seconds
Started Jul 12 05:42:03 PM PDT 24
Finished Jul 12 05:42:07 PM PDT 24
Peak memory 198692 kb
Host smart-330624fc-4ef3-4d0c-befe-eb3c947c49c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014011342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.4014011342
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1190917206
Short name T95
Test name
Test status
Simulation time 38945173 ps
CPU time 0.68 seconds
Started Jul 12 05:41:57 PM PDT 24
Finished Jul 12 05:41:59 PM PDT 24
Peak memory 195920 kb
Host smart-1b1004f8-75b2-4ffe-8931-2d0532a0cbf3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190917206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1190917206
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2759662498
Short name T830
Test name
Test status
Simulation time 42627162 ps
CPU time 1.06 seconds
Started Jul 12 05:41:55 PM PDT 24
Finished Jul 12 05:41:57 PM PDT 24
Peak memory 198608 kb
Host smart-276d6863-a4da-4fdb-9de8-714b36b87182
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759662498 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2759662498
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3010511363
Short name T790
Test name
Test status
Simulation time 23852104 ps
CPU time 0.59 seconds
Started Jul 12 05:41:50 PM PDT 24
Finished Jul 12 05:41:52 PM PDT 24
Peak memory 196168 kb
Host smart-a0492d52-2ce5-46b5-867f-114c77de531f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010511363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3010511363
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2415009559
Short name T787
Test name
Test status
Simulation time 30482577 ps
CPU time 0.64 seconds
Started Jul 12 05:41:56 PM PDT 24
Finished Jul 12 05:41:57 PM PDT 24
Peak memory 194412 kb
Host smart-8895b9a0-4a7d-4018-8b2c-e4aa0656c9e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415009559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2415009559
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.438648494
Short name T805
Test name
Test status
Simulation time 81317604 ps
CPU time 0.86 seconds
Started Jul 12 05:41:56 PM PDT 24
Finished Jul 12 05:41:58 PM PDT 24
Peak memory 196876 kb
Host smart-f0c87f2f-54fa-4fcd-a9ef-4734fde27911
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438648494 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.438648494
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1087576599
Short name T835
Test name
Test status
Simulation time 82482109 ps
CPU time 2.15 seconds
Started Jul 12 05:42:04 PM PDT 24
Finished Jul 12 05:42:07 PM PDT 24
Peak memory 198724 kb
Host smart-fdde8632-a280-4545-bdc0-6323bbd8506e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087576599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1087576599
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.614089449
Short name T757
Test name
Test status
Simulation time 40163114 ps
CPU time 0.82 seconds
Started Jul 12 05:41:57 PM PDT 24
Finished Jul 12 05:41:59 PM PDT 24
Peak memory 197840 kb
Host smart-a3b47b81-c89e-4e34-882e-52996ee2dabc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614089449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.614089449
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.857683265
Short name T748
Test name
Test status
Simulation time 12512297 ps
CPU time 0.55 seconds
Started Jul 12 05:42:40 PM PDT 24
Finished Jul 12 05:42:41 PM PDT 24
Peak memory 194308 kb
Host smart-276eb48a-16bf-4b10-8750-943a25f1a23b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857683265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.857683265
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.4268539833
Short name T746
Test name
Test status
Simulation time 24012150 ps
CPU time 0.58 seconds
Started Jul 12 05:42:40 PM PDT 24
Finished Jul 12 05:42:41 PM PDT 24
Peak memory 194324 kb
Host smart-c826142a-08e1-403c-949d-fb71d57f7b5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268539833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.4268539833
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.552186743
Short name T801
Test name
Test status
Simulation time 12927481 ps
CPU time 0.62 seconds
Started Jul 12 05:42:43 PM PDT 24
Finished Jul 12 05:42:44 PM PDT 24
Peak memory 194420 kb
Host smart-94b038ed-e0a8-4d7a-b17f-7a3e3c06b0f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552186743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.552186743
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3285233167
Short name T832
Test name
Test status
Simulation time 11417392 ps
CPU time 0.61 seconds
Started Jul 12 05:42:48 PM PDT 24
Finished Jul 12 05:42:49 PM PDT 24
Peak memory 194484 kb
Host smart-2043a499-63d7-4237-b2a8-482ee79e9341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285233167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3285233167
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1500262267
Short name T749
Test name
Test status
Simulation time 14226285 ps
CPU time 0.56 seconds
Started Jul 12 05:42:45 PM PDT 24
Finished Jul 12 05:42:46 PM PDT 24
Peak memory 194972 kb
Host smart-d951b8bd-3355-42b1-98c7-8a0abd7d0fb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500262267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1500262267
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2915255992
Short name T747
Test name
Test status
Simulation time 16155591 ps
CPU time 0.59 seconds
Started Jul 12 05:42:43 PM PDT 24
Finished Jul 12 05:42:44 PM PDT 24
Peak memory 195076 kb
Host smart-c745b4f2-38c6-41df-9ef4-feb1382d8b04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915255992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2915255992
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3665237683
Short name T778
Test name
Test status
Simulation time 45065999 ps
CPU time 0.72 seconds
Started Jul 12 05:42:41 PM PDT 24
Finished Jul 12 05:42:43 PM PDT 24
Peak memory 195044 kb
Host smart-1a6fb30d-1753-496e-8fa0-ea3e47937a78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665237683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3665237683
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2859021867
Short name T815
Test name
Test status
Simulation time 74781291 ps
CPU time 0.58 seconds
Started Jul 12 05:42:39 PM PDT 24
Finished Jul 12 05:42:40 PM PDT 24
Peak memory 194960 kb
Host smart-b1335644-69a4-4a59-923f-ac9bfcfb3239
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859021867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2859021867
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1367340633
Short name T834
Test name
Test status
Simulation time 18010165 ps
CPU time 0.61 seconds
Started Jul 12 05:42:40 PM PDT 24
Finished Jul 12 05:42:42 PM PDT 24
Peak memory 194372 kb
Host smart-f55d02de-a349-44a3-b1d5-eb676fc61f2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367340633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1367340633
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.352184855
Short name T841
Test name
Test status
Simulation time 31627607 ps
CPU time 0.61 seconds
Started Jul 12 05:42:43 PM PDT 24
Finished Jul 12 05:42:44 PM PDT 24
Peak memory 194352 kb
Host smart-1cb969c8-e5eb-4c82-aac8-91da0a134906
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352184855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.352184855
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2350610116
Short name T88
Test name
Test status
Simulation time 38448901 ps
CPU time 0.85 seconds
Started Jul 12 05:41:55 PM PDT 24
Finished Jul 12 05:41:56 PM PDT 24
Peak memory 196740 kb
Host smart-ab620e95-4786-42ad-a086-be57d2f85a1b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350610116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2350610116
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4102181401
Short name T93
Test name
Test status
Simulation time 697605990 ps
CPU time 3.58 seconds
Started Jul 12 05:42:02 PM PDT 24
Finished Jul 12 05:42:06 PM PDT 24
Peak memory 197992 kb
Host smart-e73b3e10-2546-40e8-b394-7c68f9344698
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102181401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.4102181401
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1429308620
Short name T84
Test name
Test status
Simulation time 14590129 ps
CPU time 0.59 seconds
Started Jul 12 05:42:06 PM PDT 24
Finished Jul 12 05:42:08 PM PDT 24
Peak memory 195708 kb
Host smart-d0b88824-d106-4c34-8334-3f6c3e649a90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429308620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1429308620
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3752970324
Short name T758
Test name
Test status
Simulation time 283337435 ps
CPU time 1.51 seconds
Started Jul 12 05:41:55 PM PDT 24
Finished Jul 12 05:41:57 PM PDT 24
Peak memory 198708 kb
Host smart-6c760f68-016d-4947-86df-bb2104fc7189
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752970324 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3752970324
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2290387006
Short name T831
Test name
Test status
Simulation time 42666139 ps
CPU time 0.59 seconds
Started Jul 12 05:41:55 PM PDT 24
Finished Jul 12 05:41:57 PM PDT 24
Peak memory 195220 kb
Host smart-3311aa3c-90f0-4e1c-8995-c56bd5cd04a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290387006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2290387006
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.414938234
Short name T732
Test name
Test status
Simulation time 15997521 ps
CPU time 0.59 seconds
Started Jul 12 05:42:07 PM PDT 24
Finished Jul 12 05:42:09 PM PDT 24
Peak memory 194328 kb
Host smart-e541a183-dc48-40df-bafb-e31c59452c32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414938234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.414938234
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4243283973
Short name T833
Test name
Test status
Simulation time 145720405 ps
CPU time 0.84 seconds
Started Jul 12 05:41:56 PM PDT 24
Finished Jul 12 05:41:58 PM PDT 24
Peak memory 196952 kb
Host smart-62132fae-7caa-4ba3-be95-39370ad33940
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243283973 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.4243283973
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1331494238
Short name T838
Test name
Test status
Simulation time 58975533 ps
CPU time 1.24 seconds
Started Jul 12 05:42:05 PM PDT 24
Finished Jul 12 05:42:07 PM PDT 24
Peak memory 198708 kb
Host smart-f1c8bc0a-095f-41d1-b723-aea4d5a06277
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331494238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1331494238
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3613186357
Short name T43
Test name
Test status
Simulation time 664244461 ps
CPU time 0.87 seconds
Started Jul 12 05:41:56 PM PDT 24
Finished Jul 12 05:41:59 PM PDT 24
Peak memory 197600 kb
Host smart-ccb18842-96c4-49e4-ad6c-b2ca86a27181
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613186357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3613186357
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1505877854
Short name T768
Test name
Test status
Simulation time 20156673 ps
CPU time 0.63 seconds
Started Jul 12 05:42:45 PM PDT 24
Finished Jul 12 05:42:47 PM PDT 24
Peak memory 194372 kb
Host smart-4ab1d390-fdd3-42ec-a26c-4417d148ef0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505877854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1505877854
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3207030641
Short name T829
Test name
Test status
Simulation time 16762106 ps
CPU time 0.6 seconds
Started Jul 12 05:42:40 PM PDT 24
Finished Jul 12 05:42:42 PM PDT 24
Peak memory 194276 kb
Host smart-02d9436f-f9a6-45b5-b4fb-ed74b4fe3702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207030641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3207030641
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1684710149
Short name T735
Test name
Test status
Simulation time 146375834 ps
CPU time 0.64 seconds
Started Jul 12 05:42:41 PM PDT 24
Finished Jul 12 05:42:43 PM PDT 24
Peak memory 194376 kb
Host smart-c8ff41fe-f128-4cd7-8ea5-98c523da3e51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684710149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1684710149
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2831643009
Short name T776
Test name
Test status
Simulation time 38380248 ps
CPU time 0.62 seconds
Started Jul 12 05:42:41 PM PDT 24
Finished Jul 12 05:42:43 PM PDT 24
Peak memory 194860 kb
Host smart-7c2f44f2-a3ed-46e6-94cb-eb22ce7bc413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831643009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2831643009
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.845165266
Short name T821
Test name
Test status
Simulation time 49407826 ps
CPU time 0.54 seconds
Started Jul 12 05:42:45 PM PDT 24
Finished Jul 12 05:42:46 PM PDT 24
Peak memory 194304 kb
Host smart-00eac9a8-d3d1-433f-92d5-92f66d3a3481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845165266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.845165266
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1545579298
Short name T836
Test name
Test status
Simulation time 13935575 ps
CPU time 0.64 seconds
Started Jul 12 05:42:40 PM PDT 24
Finished Jul 12 05:42:42 PM PDT 24
Peak memory 194884 kb
Host smart-d3c2a102-cf9b-4dc2-b550-5051d8f6e445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545579298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1545579298
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.746257717
Short name T806
Test name
Test status
Simulation time 20405338 ps
CPU time 0.6 seconds
Started Jul 12 05:42:48 PM PDT 24
Finished Jul 12 05:42:50 PM PDT 24
Peak memory 194376 kb
Host smart-7598b020-d3f6-4341-9ba9-0300d9ea97f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746257717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.746257717
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1435126444
Short name T725
Test name
Test status
Simulation time 80525826 ps
CPU time 0.6 seconds
Started Jul 12 05:42:46 PM PDT 24
Finished Jul 12 05:42:48 PM PDT 24
Peak memory 194368 kb
Host smart-d424b981-6b47-4bb1-99d9-5e0cbf6dfbe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435126444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1435126444
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1965471731
Short name T734
Test name
Test status
Simulation time 14560322 ps
CPU time 0.58 seconds
Started Jul 12 05:42:46 PM PDT 24
Finished Jul 12 05:42:48 PM PDT 24
Peak memory 194308 kb
Host smart-ae1d5664-0c2c-4e2c-8abc-111e647499f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965471731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1965471731
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.718457081
Short name T840
Test name
Test status
Simulation time 116659641 ps
CPU time 0.61 seconds
Started Jul 12 05:42:48 PM PDT 24
Finished Jul 12 05:42:50 PM PDT 24
Peak memory 194384 kb
Host smart-945ded4f-2906-49ec-bd5a-2e62a4c4d3ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718457081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.718457081
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.551083343
Short name T810
Test name
Test status
Simulation time 52722152 ps
CPU time 0.68 seconds
Started Jul 12 05:42:04 PM PDT 24
Finished Jul 12 05:42:06 PM PDT 24
Peak memory 196920 kb
Host smart-df247741-3134-4a93-bdfb-088f912bb901
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551083343 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.551083343
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1017914492
Short name T783
Test name
Test status
Simulation time 61474331 ps
CPU time 0.6 seconds
Started Jul 12 05:42:04 PM PDT 24
Finished Jul 12 05:42:06 PM PDT 24
Peak memory 195348 kb
Host smart-f88d8869-944b-4933-a6b6-745ab0d0bd0a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017914492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1017914492
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.160497774
Short name T796
Test name
Test status
Simulation time 16485391 ps
CPU time 0.58 seconds
Started Jul 12 05:42:02 PM PDT 24
Finished Jul 12 05:42:03 PM PDT 24
Peak memory 194328 kb
Host smart-0e4d2b3a-c56d-45b3-8b41-a3692847e512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160497774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.160497774
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.386058064
Short name T811
Test name
Test status
Simulation time 13500341 ps
CPU time 0.66 seconds
Started Jul 12 05:42:03 PM PDT 24
Finished Jul 12 05:42:04 PM PDT 24
Peak memory 196048 kb
Host smart-bb41ed56-dbf6-4df7-9658-e4f7effa40e7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386058064 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.386058064
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.194549680
Short name T718
Test name
Test status
Simulation time 46355406 ps
CPU time 2.24 seconds
Started Jul 12 05:42:03 PM PDT 24
Finished Jul 12 05:42:06 PM PDT 24
Peak memory 198700 kb
Host smart-23f9517d-ff1b-45a8-8964-7563160776c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194549680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.194549680
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1498066635
Short name T48
Test name
Test status
Simulation time 45189055 ps
CPU time 0.89 seconds
Started Jul 12 05:42:03 PM PDT 24
Finished Jul 12 05:42:05 PM PDT 24
Peak memory 198484 kb
Host smart-38f6c339-1936-4bbd-a603-33ddf16980d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498066635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1498066635
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.617945103
Short name T820
Test name
Test status
Simulation time 19122814 ps
CPU time 0.98 seconds
Started Jul 12 05:42:04 PM PDT 24
Finished Jul 12 05:42:06 PM PDT 24
Peak memory 198608 kb
Host smart-9277712d-e9db-4688-ace1-81f123e649aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617945103 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.617945103
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2694730305
Short name T742
Test name
Test status
Simulation time 44743373 ps
CPU time 0.56 seconds
Started Jul 12 05:42:07 PM PDT 24
Finished Jul 12 05:42:08 PM PDT 24
Peak memory 195972 kb
Host smart-1820381f-1926-4089-94ba-bfef4441bd1f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694730305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2694730305
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.482383174
Short name T813
Test name
Test status
Simulation time 53329420 ps
CPU time 0.59 seconds
Started Jul 12 05:42:12 PM PDT 24
Finished Jul 12 05:42:13 PM PDT 24
Peak memory 194992 kb
Host smart-cab5de13-80f4-4302-8ba2-559e5672296c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482383174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.482383174
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.506496692
Short name T104
Test name
Test status
Simulation time 37432239 ps
CPU time 0.86 seconds
Started Jul 12 05:42:03 PM PDT 24
Finished Jul 12 05:42:05 PM PDT 24
Peak memory 196852 kb
Host smart-27b7903e-0759-4162-a05d-7a60d3ff14ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506496692 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.506496692
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.587632323
Short name T723
Test name
Test status
Simulation time 257739782 ps
CPU time 2.73 seconds
Started Jul 12 05:42:04 PM PDT 24
Finished Jul 12 05:42:08 PM PDT 24
Peak memory 198716 kb
Host smart-d662f170-53db-4b2c-9575-bab80715c0b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587632323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.587632323
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.330981161
Short name T822
Test name
Test status
Simulation time 84516037 ps
CPU time 0.86 seconds
Started Jul 12 05:42:03 PM PDT 24
Finished Jul 12 05:42:04 PM PDT 24
Peak memory 197644 kb
Host smart-ee735e08-15d3-473e-a882-0732b8dcbccd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330981161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.330981161
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2516221462
Short name T772
Test name
Test status
Simulation time 124102023 ps
CPU time 0.85 seconds
Started Jul 12 05:42:10 PM PDT 24
Finished Jul 12 05:42:12 PM PDT 24
Peak memory 198540 kb
Host smart-ec8af2d5-352e-403d-8454-407b0b150634
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516221462 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2516221462
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2310136733
Short name T85
Test name
Test status
Simulation time 15278118 ps
CPU time 0.61 seconds
Started Jul 12 05:42:11 PM PDT 24
Finished Jul 12 05:42:12 PM PDT 24
Peak memory 195324 kb
Host smart-7f4d73c1-9b42-43d4-9b6e-2d226f87a165
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310136733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2310136733
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.4233022810
Short name T803
Test name
Test status
Simulation time 101740880 ps
CPU time 0.63 seconds
Started Jul 12 05:42:12 PM PDT 24
Finished Jul 12 05:42:14 PM PDT 24
Peak memory 194312 kb
Host smart-937da1ed-034f-4cc8-83c2-0f166dc96a05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233022810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.4233022810
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.826728258
Short name T105
Test name
Test status
Simulation time 19494310 ps
CPU time 0.74 seconds
Started Jul 12 05:42:11 PM PDT 24
Finished Jul 12 05:42:12 PM PDT 24
Peak memory 196840 kb
Host smart-c4da9f28-ef91-4b56-9f10-8a85b78cd7d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826728258 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.826728258
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2103628296
Short name T719
Test name
Test status
Simulation time 153205249 ps
CPU time 3.01 seconds
Started Jul 12 05:42:11 PM PDT 24
Finished Jul 12 05:42:14 PM PDT 24
Peak memory 198680 kb
Host smart-0ae616cb-9e04-4ea6-acfd-b8c761da7441
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103628296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2103628296
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.4024601847
Short name T46
Test name
Test status
Simulation time 372103775 ps
CPU time 1.39 seconds
Started Jul 12 05:42:11 PM PDT 24
Finished Jul 12 05:42:13 PM PDT 24
Peak memory 198716 kb
Host smart-2b9abb32-a0a5-41bc-b591-375263d789bf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024601847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.4024601847
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2515713742
Short name T737
Test name
Test status
Simulation time 73890449 ps
CPU time 0.91 seconds
Started Jul 12 05:42:10 PM PDT 24
Finished Jul 12 05:42:11 PM PDT 24
Peak memory 198612 kb
Host smart-47bb717e-d511-4021-b5f0-26eb7608f644
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515713742 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2515713742
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2828474164
Short name T771
Test name
Test status
Simulation time 43560709 ps
CPU time 0.57 seconds
Started Jul 12 05:42:12 PM PDT 24
Finished Jul 12 05:42:13 PM PDT 24
Peak memory 195288 kb
Host smart-5e2a3209-9d06-465d-bc39-31ea17820a42
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828474164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2828474164
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.4205238711
Short name T767
Test name
Test status
Simulation time 39304122 ps
CPU time 0.58 seconds
Started Jul 12 05:42:10 PM PDT 24
Finished Jul 12 05:42:12 PM PDT 24
Peak memory 194440 kb
Host smart-e27bebd2-a79f-469c-95c8-2b746cced017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205238711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.4205238711
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1062906277
Short name T108
Test name
Test status
Simulation time 60755327 ps
CPU time 0.62 seconds
Started Jul 12 05:42:16 PM PDT 24
Finished Jul 12 05:42:17 PM PDT 24
Peak memory 194968 kb
Host smart-3a82f4ab-e099-4597-a725-6fb030023f84
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062906277 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1062906277
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.333595954
Short name T722
Test name
Test status
Simulation time 242048608 ps
CPU time 1.42 seconds
Started Jul 12 05:42:12 PM PDT 24
Finished Jul 12 05:42:14 PM PDT 24
Peak memory 198704 kb
Host smart-2a90800c-2867-4a6e-97f8-2b16e20b5ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333595954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.333595954
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3502334074
Short name T837
Test name
Test status
Simulation time 121834718 ps
CPU time 1.44 seconds
Started Jul 12 05:42:12 PM PDT 24
Finished Jul 12 05:42:14 PM PDT 24
Peak memory 198704 kb
Host smart-10ea4904-d7f1-49ca-ac0b-8d01838914ba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502334074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3502334074
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.509145325
Short name T753
Test name
Test status
Simulation time 68405789 ps
CPU time 1.05 seconds
Started Jul 12 05:42:18 PM PDT 24
Finished Jul 12 05:42:19 PM PDT 24
Peak memory 198496 kb
Host smart-32f12c59-e653-4703-b3bf-945ff7903795
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509145325 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.509145325
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2261142989
Short name T755
Test name
Test status
Simulation time 13755121 ps
CPU time 0.6 seconds
Started Jul 12 05:42:12 PM PDT 24
Finished Jul 12 05:42:13 PM PDT 24
Peak memory 196132 kb
Host smart-565712cb-174f-4892-a35d-e0150533e08c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261142989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2261142989
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.4053038237
Short name T802
Test name
Test status
Simulation time 16327094 ps
CPU time 0.63 seconds
Started Jul 12 05:42:20 PM PDT 24
Finished Jul 12 05:42:22 PM PDT 24
Peak memory 194372 kb
Host smart-fa9492cf-025e-44aa-b9c9-a42f097c4866
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053038237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.4053038237
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2069517941
Short name T106
Test name
Test status
Simulation time 97714466 ps
CPU time 0.78 seconds
Started Jul 12 05:42:09 PM PDT 24
Finished Jul 12 05:42:10 PM PDT 24
Peak memory 197588 kb
Host smart-44193449-6313-4bcb-bb80-f3bdcc404eb3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069517941 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2069517941
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.4198045786
Short name T794
Test name
Test status
Simulation time 286095075 ps
CPU time 3.22 seconds
Started Jul 12 05:42:17 PM PDT 24
Finished Jul 12 05:42:21 PM PDT 24
Peak memory 198644 kb
Host smart-33d40e5b-c6ad-40bf-8246-5d8681217de5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198045786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.4198045786
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.475665077
Short name T214
Test name
Test status
Simulation time 205907801 ps
CPU time 0.74 seconds
Started Jul 12 05:43:11 PM PDT 24
Finished Jul 12 05:43:13 PM PDT 24
Peak memory 195888 kb
Host smart-57255992-ba08-4407-8b09-8d3f967e79fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475665077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.475665077
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2147585757
Short name T559
Test name
Test status
Simulation time 514151268 ps
CPU time 14.25 seconds
Started Jul 12 05:43:11 PM PDT 24
Finished Jul 12 05:43:27 PM PDT 24
Peak memory 197464 kb
Host smart-5a3d9c20-07de-46ae-8001-fcd1e1f743ea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147585757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2147585757
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3119980859
Short name T286
Test name
Test status
Simulation time 28600239 ps
CPU time 0.69 seconds
Started Jul 12 05:43:18 PM PDT 24
Finished Jul 12 05:43:20 PM PDT 24
Peak memory 195144 kb
Host smart-c2b12ec0-2e4d-408d-aadd-a470f18739e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119980859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3119980859
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.4068951154
Short name T486
Test name
Test status
Simulation time 87984987 ps
CPU time 0.97 seconds
Started Jul 12 05:43:13 PM PDT 24
Finished Jul 12 05:43:15 PM PDT 24
Peak memory 198244 kb
Host smart-9087e93b-28bc-4e60-b22e-539a2f92da68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068951154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.4068951154
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1805226270
Short name T345
Test name
Test status
Simulation time 107277887 ps
CPU time 1.27 seconds
Started Jul 12 05:43:16 PM PDT 24
Finished Jul 12 05:43:18 PM PDT 24
Peak memory 197532 kb
Host smart-2f815859-630b-443c-84a5-90195e4d5de2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805226270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1805226270
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.4258947632
Short name T392
Test name
Test status
Simulation time 140163749 ps
CPU time 2.35 seconds
Started Jul 12 05:43:13 PM PDT 24
Finished Jul 12 05:43:16 PM PDT 24
Peak memory 198720 kb
Host smart-f46b3531-d489-448f-9c9b-0f81f54522eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258947632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
4258947632
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3312534673
Short name T402
Test name
Test status
Simulation time 34501035 ps
CPU time 0.99 seconds
Started Jul 12 05:43:12 PM PDT 24
Finished Jul 12 05:43:14 PM PDT 24
Peak memory 196516 kb
Host smart-105ad256-34e7-4491-828d-a1e381fcbdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312534673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3312534673
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3747768138
Short name T530
Test name
Test status
Simulation time 63684801 ps
CPU time 1.24 seconds
Started Jul 12 05:43:13 PM PDT 24
Finished Jul 12 05:43:16 PM PDT 24
Peak memory 197288 kb
Host smart-ceffe01c-3b8d-483c-9331-d82913d040f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747768138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3747768138
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1406516662
Short name T293
Test name
Test status
Simulation time 1320697447 ps
CPU time 2.27 seconds
Started Jul 12 05:43:12 PM PDT 24
Finished Jul 12 05:43:15 PM PDT 24
Peak memory 198532 kb
Host smart-44f71790-6e73-4361-9d04-34f19438b92c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406516662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1406516662
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.204662903
Short name T198
Test name
Test status
Simulation time 133641156 ps
CPU time 1.22 seconds
Started Jul 12 05:43:17 PM PDT 24
Finished Jul 12 05:43:19 PM PDT 24
Peak memory 197380 kb
Host smart-9b359c1e-2d69-475b-bbe5-346a0125cd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204662903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.204662903
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2924881231
Short name T669
Test name
Test status
Simulation time 75068494 ps
CPU time 1.22 seconds
Started Jul 12 05:43:11 PM PDT 24
Finished Jul 12 05:43:13 PM PDT 24
Peak memory 197068 kb
Host smart-62c5dfe3-3cc4-4681-bdfd-9793ccd6166d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924881231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2924881231
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1028521602
Short name T679
Test name
Test status
Simulation time 7886520370 ps
CPU time 90.68 seconds
Started Jul 12 05:43:14 PM PDT 24
Finished Jul 12 05:44:45 PM PDT 24
Peak memory 198772 kb
Host smart-7047a68d-34a7-4c75-848f-0ebee49048ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028521602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1028521602
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.1855649874
Short name T617
Test name
Test status
Simulation time 34516503601 ps
CPU time 702.23 seconds
Started Jul 12 05:43:11 PM PDT 24
Finished Jul 12 05:54:55 PM PDT 24
Peak memory 198928 kb
Host smart-06a655d2-23b6-4ba1-8909-1ae26e1623b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1855649874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.1855649874
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1306801636
Short name T238
Test name
Test status
Simulation time 12221149 ps
CPU time 0.58 seconds
Started Jul 12 05:43:18 PM PDT 24
Finished Jul 12 05:43:20 PM PDT 24
Peak memory 194672 kb
Host smart-d240ad33-1001-48df-8e68-ad3e09132a91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306801636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1306801636
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3076531536
Short name T699
Test name
Test status
Simulation time 28976713 ps
CPU time 0.72 seconds
Started Jul 12 05:43:12 PM PDT 24
Finished Jul 12 05:43:14 PM PDT 24
Peak memory 194804 kb
Host smart-3028d5e4-f3be-4094-8138-54ef78a9173a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076531536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3076531536
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.2747898135
Short name T596
Test name
Test status
Simulation time 200082444 ps
CPU time 5.68 seconds
Started Jul 12 05:43:10 PM PDT 24
Finished Jul 12 05:43:17 PM PDT 24
Peak memory 197644 kb
Host smart-56722a13-9577-459f-9fbb-fbf959e02e90
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747898135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.2747898135
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3552312569
Short name T683
Test name
Test status
Simulation time 170445552 ps
CPU time 0.87 seconds
Started Jul 12 05:43:12 PM PDT 24
Finished Jul 12 05:43:14 PM PDT 24
Peak memory 196508 kb
Host smart-3d7930cd-3880-416a-90e0-2df14e6f4126
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552312569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3552312569
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.4163932852
Short name T282
Test name
Test status
Simulation time 217006429 ps
CPU time 1.15 seconds
Started Jul 12 05:43:12 PM PDT 24
Finished Jul 12 05:43:15 PM PDT 24
Peak memory 196660 kb
Host smart-7ba3fc23-30bc-4cf7-8d48-21a7aaeaff6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163932852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.4163932852
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2178536174
Short name T515
Test name
Test status
Simulation time 451421187 ps
CPU time 1.18 seconds
Started Jul 12 05:43:18 PM PDT 24
Finished Jul 12 05:43:21 PM PDT 24
Peak memory 197712 kb
Host smart-726a8a0b-d5e2-4132-aa75-8519a5a23805
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178536174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2178536174
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3101663108
Short name T304
Test name
Test status
Simulation time 449950155 ps
CPU time 2.51 seconds
Started Jul 12 05:43:12 PM PDT 24
Finished Jul 12 05:43:16 PM PDT 24
Peak memory 198648 kb
Host smart-50dcf41b-c58e-469d-a453-92a9c3baecca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101663108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3101663108
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3007265260
Short name T261
Test name
Test status
Simulation time 59186123 ps
CPU time 0.74 seconds
Started Jul 12 05:43:13 PM PDT 24
Finished Jul 12 05:43:14 PM PDT 24
Peak memory 196080 kb
Host smart-34d1b1e2-93e6-40a3-964f-29174d8a9e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007265260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3007265260
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.556036436
Short name T302
Test name
Test status
Simulation time 26757320 ps
CPU time 0.64 seconds
Started Jul 12 05:43:11 PM PDT 24
Finished Jul 12 05:43:12 PM PDT 24
Peak memory 195000 kb
Host smart-5b5cbdd1-2d9a-46ab-a2ed-0c8ffa526ea5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556036436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.556036436
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1249937142
Short name T510
Test name
Test status
Simulation time 117056173 ps
CPU time 4.93 seconds
Started Jul 12 05:43:16 PM PDT 24
Finished Jul 12 05:43:22 PM PDT 24
Peak memory 197000 kb
Host smart-25dae7d2-34f8-4cc1-b9ce-cfc9c531ebf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249937142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1249937142
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.368723576
Short name T38
Test name
Test status
Simulation time 204441514 ps
CPU time 0.85 seconds
Started Jul 12 05:43:21 PM PDT 24
Finished Jul 12 05:43:23 PM PDT 24
Peak memory 214284 kb
Host smart-2e3d11d9-a8fb-4faf-a215-9a60854f7e5f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368723576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.368723576
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3350876689
Short name T294
Test name
Test status
Simulation time 92258524 ps
CPU time 1.42 seconds
Started Jul 12 05:43:13 PM PDT 24
Finished Jul 12 05:43:15 PM PDT 24
Peak memory 197600 kb
Host smart-c3155d71-2ce1-4e09-a0a5-b077e8f60c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350876689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3350876689
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.4122844438
Short name T274
Test name
Test status
Simulation time 324799626 ps
CPU time 1.26 seconds
Started Jul 12 05:43:13 PM PDT 24
Finished Jul 12 05:43:15 PM PDT 24
Peak memory 196524 kb
Host smart-11bf10ff-def9-46c6-bc55-1b9462caef3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122844438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.4122844438
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3095533294
Short name T696
Test name
Test status
Simulation time 26936132648 ps
CPU time 174.85 seconds
Started Jul 12 05:43:15 PM PDT 24
Finished Jul 12 05:46:10 PM PDT 24
Peak memory 198832 kb
Host smart-b009073e-0eb1-4ce2-8626-cf49224906e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095533294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3095533294
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.2020501530
Short name T464
Test name
Test status
Simulation time 743668917562 ps
CPU time 1448.3 seconds
Started Jul 12 05:43:19 PM PDT 24
Finished Jul 12 06:07:29 PM PDT 24
Peak memory 207104 kb
Host smart-ca7a2c84-83fe-43b7-937d-6bd0f138401f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2020501530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.2020501530
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.781947817
Short name T340
Test name
Test status
Simulation time 53197813 ps
CPU time 0.58 seconds
Started Jul 12 05:43:39 PM PDT 24
Finished Jul 12 05:43:41 PM PDT 24
Peak memory 195448 kb
Host smart-5d3c84b1-8d40-4a5f-8101-c5494492351e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781947817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.781947817
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3585401579
Short name T605
Test name
Test status
Simulation time 28997888 ps
CPU time 0.64 seconds
Started Jul 12 05:43:40 PM PDT 24
Finished Jul 12 05:43:42 PM PDT 24
Peak memory 194640 kb
Host smart-3f7cb4f7-1eec-4986-90a9-a35adbba1639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585401579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3585401579
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1594069320
Short name T361
Test name
Test status
Simulation time 3884221613 ps
CPU time 26.88 seconds
Started Jul 12 05:43:41 PM PDT 24
Finished Jul 12 05:44:09 PM PDT 24
Peak memory 197584 kb
Host smart-5588d3c7-743f-411c-bf17-c9cb1a0a7284
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594069320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1594069320
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2324635488
Short name T301
Test name
Test status
Simulation time 53707296 ps
CPU time 0.94 seconds
Started Jul 12 05:43:41 PM PDT 24
Finished Jul 12 05:43:43 PM PDT 24
Peak memory 198036 kb
Host smart-75315fb6-8c34-4b2c-a660-34205dc39fc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324635488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2324635488
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3295743347
Short name T267
Test name
Test status
Simulation time 43404334 ps
CPU time 0.88 seconds
Started Jul 12 05:43:41 PM PDT 24
Finished Jul 12 05:43:43 PM PDT 24
Peak memory 196572 kb
Host smart-dc403de2-d181-4ae9-b928-97a47d27fbf7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295743347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3295743347
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.749692766
Short name T544
Test name
Test status
Simulation time 86533266 ps
CPU time 3.45 seconds
Started Jul 12 05:43:38 PM PDT 24
Finished Jul 12 05:43:42 PM PDT 24
Peak memory 198676 kb
Host smart-d5e53ea3-9198-46f4-aad9-ea7e49fdacae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749692766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.749692766
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.380859736
Short name T616
Test name
Test status
Simulation time 64449014 ps
CPU time 1.35 seconds
Started Jul 12 05:43:38 PM PDT 24
Finished Jul 12 05:43:40 PM PDT 24
Peak memory 196680 kb
Host smart-d6328447-2205-49f0-8216-cd20d67addc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380859736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.
380859736
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1335812595
Short name T22
Test name
Test status
Simulation time 23578988 ps
CPU time 0.73 seconds
Started Jul 12 05:43:40 PM PDT 24
Finished Jul 12 05:43:42 PM PDT 24
Peak memory 195988 kb
Host smart-dafa7f3d-0f93-4f46-8b52-a0c8f7cba520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335812595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1335812595
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2902142618
Short name T526
Test name
Test status
Simulation time 39183019 ps
CPU time 0.88 seconds
Started Jul 12 05:43:41 PM PDT 24
Finished Jul 12 05:43:43 PM PDT 24
Peak memory 196404 kb
Host smart-7a02787f-9404-43e3-a16b-a38ddec3f1e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902142618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2902142618
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1287105366
Short name T518
Test name
Test status
Simulation time 1286830195 ps
CPU time 3.37 seconds
Started Jul 12 05:43:39 PM PDT 24
Finished Jul 12 05:43:44 PM PDT 24
Peak memory 198668 kb
Host smart-1e2a105a-9132-4d22-a26c-23242b8ad84f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287105366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1287105366
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3158058684
Short name T387
Test name
Test status
Simulation time 65304780 ps
CPU time 1 seconds
Started Jul 12 05:43:39 PM PDT 24
Finished Jul 12 05:43:41 PM PDT 24
Peak memory 197212 kb
Host smart-d09ef7d8-26b2-4580-8357-55c6bcf6591a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158058684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3158058684
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.576192440
Short name T638
Test name
Test status
Simulation time 156792537 ps
CPU time 1.38 seconds
Started Jul 12 05:43:42 PM PDT 24
Finished Jul 12 05:43:45 PM PDT 24
Peak memory 198400 kb
Host smart-32120647-8377-424a-8bdf-e6ae2ac89827
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576192440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.576192440
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.283280995
Short name T450
Test name
Test status
Simulation time 21307940666 ps
CPU time 231.91 seconds
Started Jul 12 05:43:39 PM PDT 24
Finished Jul 12 05:47:33 PM PDT 24
Peak memory 198768 kb
Host smart-b5f81b70-262f-49fe-b796-6a310c85a229
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283280995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.283280995
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.110859706
Short name T700
Test name
Test status
Simulation time 15731179 ps
CPU time 0.56 seconds
Started Jul 12 05:43:49 PM PDT 24
Finished Jul 12 05:43:50 PM PDT 24
Peak memory 195520 kb
Host smart-fc60193c-99b8-461e-a1ac-bb0e1dbb9e58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110859706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.110859706
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3239540204
Short name T606
Test name
Test status
Simulation time 32529702 ps
CPU time 0.75 seconds
Started Jul 12 05:43:49 PM PDT 24
Finished Jul 12 05:43:51 PM PDT 24
Peak memory 196668 kb
Host smart-8f7cbdab-3959-4a2c-9a42-73afd561013c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239540204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3239540204
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1274132746
Short name T694
Test name
Test status
Simulation time 253758594 ps
CPU time 5.25 seconds
Started Jul 12 05:43:45 PM PDT 24
Finished Jul 12 05:43:51 PM PDT 24
Peak memory 196200 kb
Host smart-d782f93a-d4bf-4ce3-afa2-d07d4fcdabdb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274132746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1274132746
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.991148132
Short name T483
Test name
Test status
Simulation time 103012892 ps
CPU time 0.71 seconds
Started Jul 12 05:43:45 PM PDT 24
Finished Jul 12 05:43:47 PM PDT 24
Peak memory 195376 kb
Host smart-448f978e-8871-4f51-b9b9-42c4044da58b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991148132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.991148132
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.397908133
Short name T308
Test name
Test status
Simulation time 48333074 ps
CPU time 0.92 seconds
Started Jul 12 05:43:47 PM PDT 24
Finished Jul 12 05:43:49 PM PDT 24
Peak memory 196084 kb
Host smart-5f76a68d-bd99-4b1e-bbe3-213a3a7ceaa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397908133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.397908133
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.4111899113
Short name T378
Test name
Test status
Simulation time 181348527 ps
CPU time 3.67 seconds
Started Jul 12 05:43:43 PM PDT 24
Finished Jul 12 05:43:48 PM PDT 24
Peak memory 198632 kb
Host smart-7d9dc195-4ecb-4f07-9418-1e1eb371452e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111899113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.4111899113
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3597153126
Short name T159
Test name
Test status
Simulation time 555727191 ps
CPU time 3.27 seconds
Started Jul 12 05:43:47 PM PDT 24
Finished Jul 12 05:43:51 PM PDT 24
Peak memory 198712 kb
Host smart-76e60bc3-0197-4fb3-8f10-d191f7e006d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597153126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3597153126
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2056849395
Short name T651
Test name
Test status
Simulation time 210042286 ps
CPU time 1.36 seconds
Started Jul 12 05:43:46 PM PDT 24
Finished Jul 12 05:43:48 PM PDT 24
Peak memory 198816 kb
Host smart-2d33ba5d-2c25-41e4-ac63-d044a6cb3b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056849395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2056849395
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2020339559
Short name T139
Test name
Test status
Simulation time 113931385 ps
CPU time 1.16 seconds
Started Jul 12 05:43:46 PM PDT 24
Finished Jul 12 05:43:48 PM PDT 24
Peak memory 197688 kb
Host smart-61595bc5-2fbf-45a5-9992-89a8f2a58d6a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020339559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2020339559
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2783718733
Short name T29
Test name
Test status
Simulation time 77699835 ps
CPU time 1.55 seconds
Started Jul 12 05:43:49 PM PDT 24
Finished Jul 12 05:43:51 PM PDT 24
Peak memory 198524 kb
Host smart-621d8842-79f2-41e4-aae6-d6c9c44bb6cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783718733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2783718733
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1960004985
Short name T495
Test name
Test status
Simulation time 99226224 ps
CPU time 1.34 seconds
Started Jul 12 05:43:40 PM PDT 24
Finished Jul 12 05:43:43 PM PDT 24
Peak memory 197368 kb
Host smart-3409bfae-2dde-4659-9781-28d1e1273cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960004985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1960004985
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3429839698
Short name T151
Test name
Test status
Simulation time 275493737 ps
CPU time 1.21 seconds
Started Jul 12 05:43:38 PM PDT 24
Finished Jul 12 05:43:41 PM PDT 24
Peak memory 196464 kb
Host smart-bbb8a2cf-97d7-4637-8d54-11ee4fee060e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429839698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3429839698
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.749157865
Short name T711
Test name
Test status
Simulation time 7790081044 ps
CPU time 206.37 seconds
Started Jul 12 05:43:45 PM PDT 24
Finished Jul 12 05:47:13 PM PDT 24
Peak memory 198708 kb
Host smart-a5b3b009-4f23-42c5-9e75-53e05a5a0a9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749157865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.749157865
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2706077729
Short name T630
Test name
Test status
Simulation time 12691723 ps
CPU time 0.61 seconds
Started Jul 12 05:43:53 PM PDT 24
Finished Jul 12 05:43:55 PM PDT 24
Peak memory 194768 kb
Host smart-9998a557-3e9d-4180-9313-05e439e4e639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706077729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2706077729
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.133709207
Short name T140
Test name
Test status
Simulation time 30486093 ps
CPU time 0.79 seconds
Started Jul 12 05:43:43 PM PDT 24
Finished Jul 12 05:43:45 PM PDT 24
Peak memory 195960 kb
Host smart-136317b4-adb4-48c6-8e24-9caa6f13639c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133709207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.133709207
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2701668361
Short name T517
Test name
Test status
Simulation time 237411912 ps
CPU time 7.79 seconds
Started Jul 12 05:43:50 PM PDT 24
Finished Jul 12 05:43:58 PM PDT 24
Peak memory 198676 kb
Host smart-7d66ae24-6f1e-41d4-b8f6-c4f89d0a41d3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701668361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2701668361
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3492324792
Short name T710
Test name
Test status
Simulation time 367360983 ps
CPU time 1.09 seconds
Started Jul 12 05:43:50 PM PDT 24
Finished Jul 12 05:43:52 PM PDT 24
Peak memory 197388 kb
Host smart-1a78530d-8e47-4906-b906-6d33ae9b81c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492324792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3492324792
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.995470392
Short name T190
Test name
Test status
Simulation time 79320117 ps
CPU time 1.31 seconds
Started Jul 12 05:43:49 PM PDT 24
Finished Jul 12 05:43:51 PM PDT 24
Peak memory 198628 kb
Host smart-5564ed93-5ada-438a-8bb4-9f76f179cf12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995470392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.995470392
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.220446408
Short name T341
Test name
Test status
Simulation time 1571374949 ps
CPU time 3.32 seconds
Started Jul 12 05:43:47 PM PDT 24
Finished Jul 12 05:43:51 PM PDT 24
Peak memory 196900 kb
Host smart-1176bbd3-3af4-474f-b45d-eccd3eeade86
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220446408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.220446408
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.3238819843
Short name T404
Test name
Test status
Simulation time 106656280 ps
CPU time 2.36 seconds
Started Jul 12 05:43:45 PM PDT 24
Finished Jul 12 05:43:48 PM PDT 24
Peak memory 196416 kb
Host smart-ee039ac6-b5d6-47bb-88cc-3dce3b2fb9b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238819843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.3238819843
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1074583715
Short name T163
Test name
Test status
Simulation time 92039991 ps
CPU time 0.95 seconds
Started Jul 12 05:43:47 PM PDT 24
Finished Jul 12 05:43:49 PM PDT 24
Peak memory 196676 kb
Host smart-a5c706d7-bec6-46e6-8cfa-f391a34d51ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074583715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1074583715
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.192251124
Short name T242
Test name
Test status
Simulation time 170257487 ps
CPU time 1.09 seconds
Started Jul 12 05:43:45 PM PDT 24
Finished Jul 12 05:43:47 PM PDT 24
Peak memory 196616 kb
Host smart-e8b466fc-3f33-4e96-b5a7-05b79cc66135
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192251124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.192251124
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2698059067
Short name T461
Test name
Test status
Simulation time 413254402 ps
CPU time 5.16 seconds
Started Jul 12 05:43:46 PM PDT 24
Finished Jul 12 05:43:52 PM PDT 24
Peak memory 198140 kb
Host smart-c40840ec-217f-422b-a021-968175d9b0ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698059067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2698059067
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.656729157
Short name T458
Test name
Test status
Simulation time 101398051 ps
CPU time 1.08 seconds
Started Jul 12 05:43:46 PM PDT 24
Finished Jul 12 05:43:48 PM PDT 24
Peak memory 196480 kb
Host smart-19441e26-ecdd-48c5-b4a7-68f271f210d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656729157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.656729157
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3155243293
Short name T343
Test name
Test status
Simulation time 78718799 ps
CPU time 1.25 seconds
Started Jul 12 05:43:47 PM PDT 24
Finished Jul 12 05:43:49 PM PDT 24
Peak memory 197004 kb
Host smart-3965a0d7-26f3-4be3-bebc-452abf2b1493
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155243293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3155243293
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.195770266
Short name T23
Test name
Test status
Simulation time 13568004786 ps
CPU time 188.1 seconds
Started Jul 12 05:43:50 PM PDT 24
Finished Jul 12 05:46:59 PM PDT 24
Peak memory 198780 kb
Host smart-2fb2c7e4-e91d-48d0-aa76-4bad164991f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195770266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.195770266
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1888437160
Short name T374
Test name
Test status
Simulation time 14564452 ps
CPU time 0.58 seconds
Started Jul 12 05:43:58 PM PDT 24
Finished Jul 12 05:44:00 PM PDT 24
Peak memory 195332 kb
Host smart-efe01c76-768e-4244-83c5-77c647e368a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888437160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1888437160
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1953304739
Short name T132
Test name
Test status
Simulation time 36276888 ps
CPU time 0.67 seconds
Started Jul 12 05:43:53 PM PDT 24
Finished Jul 12 05:43:55 PM PDT 24
Peak memory 195344 kb
Host smart-1501b3fd-b519-45b2-b181-5b987ca609db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953304739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1953304739
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3282908810
Short name T225
Test name
Test status
Simulation time 369964871 ps
CPU time 18.69 seconds
Started Jul 12 05:43:53 PM PDT 24
Finished Jul 12 05:44:13 PM PDT 24
Peak memory 197568 kb
Host smart-52575591-2c27-4048-910a-6db9ab1be199
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282908810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3282908810
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.506710602
Short name T449
Test name
Test status
Simulation time 326949688 ps
CPU time 1.06 seconds
Started Jul 12 05:44:00 PM PDT 24
Finished Jul 12 05:44:03 PM PDT 24
Peak memory 197336 kb
Host smart-7a0efa4f-eb02-44c6-8019-bad4cec26023
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506710602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.506710602
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3598941290
Short name T389
Test name
Test status
Simulation time 114214025 ps
CPU time 1.17 seconds
Started Jul 12 05:43:55 PM PDT 24
Finished Jul 12 05:43:57 PM PDT 24
Peak memory 196356 kb
Host smart-ca52c6a3-1ef0-45dc-bf5d-4666c210dfaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598941290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3598941290
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.323062648
Short name T199
Test name
Test status
Simulation time 66941595 ps
CPU time 1.4 seconds
Started Jul 12 05:43:52 PM PDT 24
Finished Jul 12 05:43:55 PM PDT 24
Peak memory 198772 kb
Host smart-555b619f-d67d-4852-a5b3-97366aac413c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323062648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.323062648
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.587301779
Short name T639
Test name
Test status
Simulation time 378360673 ps
CPU time 2.39 seconds
Started Jul 12 05:43:59 PM PDT 24
Finished Jul 12 05:44:03 PM PDT 24
Peak memory 196520 kb
Host smart-1abaf188-98d5-4fd4-b196-b4764e473c57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587301779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
587301779
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3786211305
Short name T675
Test name
Test status
Simulation time 52831562 ps
CPU time 1.3 seconds
Started Jul 12 05:43:53 PM PDT 24
Finished Jul 12 05:43:56 PM PDT 24
Peak memory 197628 kb
Host smart-43942081-44e4-41de-a2f7-cd3dd7f2e950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786211305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3786211305
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3551690418
Short name T401
Test name
Test status
Simulation time 341039832 ps
CPU time 1.31 seconds
Started Jul 12 05:43:59 PM PDT 24
Finished Jul 12 05:44:02 PM PDT 24
Peak memory 196500 kb
Host smart-da7c716a-efbd-4940-bee5-81cecf139bb8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551690418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3551690418
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3467098420
Short name T523
Test name
Test status
Simulation time 287931712 ps
CPU time 4.43 seconds
Started Jul 12 05:43:51 PM PDT 24
Finished Jul 12 05:43:56 PM PDT 24
Peak memory 197796 kb
Host smart-1318efac-32be-4fe0-be96-03d6d3f175aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467098420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3467098420
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3389183572
Short name T521
Test name
Test status
Simulation time 43572535 ps
CPU time 1.08 seconds
Started Jul 12 05:43:51 PM PDT 24
Finished Jul 12 05:43:53 PM PDT 24
Peak memory 196040 kb
Host smart-3c9da60f-02cc-49f1-8229-762dbf806383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389183572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3389183572
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1067407247
Short name T209
Test name
Test status
Simulation time 88872934 ps
CPU time 0.86 seconds
Started Jul 12 05:43:52 PM PDT 24
Finished Jul 12 05:43:54 PM PDT 24
Peak memory 196020 kb
Host smart-3ef63caa-6fe0-42ce-85c9-41881915a5ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067407247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1067407247
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1681849124
Short name T568
Test name
Test status
Simulation time 25810672646 ps
CPU time 78.12 seconds
Started Jul 12 05:43:54 PM PDT 24
Finished Jul 12 05:45:14 PM PDT 24
Peak memory 198684 kb
Host smart-447f35c3-75f5-49c1-97a0-805769876d45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681849124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1681849124
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2742606684
Short name T128
Test name
Test status
Simulation time 14903664 ps
CPU time 0.61 seconds
Started Jul 12 05:43:56 PM PDT 24
Finished Jul 12 05:43:57 PM PDT 24
Peak memory 195076 kb
Host smart-b3d9076d-776a-4ab3-8a46-dbb77b3dc94f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742606684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2742606684
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.4227878091
Short name T292
Test name
Test status
Simulation time 31303689 ps
CPU time 0.71 seconds
Started Jul 12 05:43:53 PM PDT 24
Finished Jul 12 05:43:56 PM PDT 24
Peak memory 194816 kb
Host smart-0376144f-cd57-4ef5-9c55-7fab5528320e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227878091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.4227878091
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.561946548
Short name T276
Test name
Test status
Simulation time 655779570 ps
CPU time 8.73 seconds
Started Jul 12 05:43:53 PM PDT 24
Finished Jul 12 05:44:03 PM PDT 24
Peak memory 196188 kb
Host smart-ad90a16e-721c-460d-b7c2-bd92656d7783
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561946548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.561946548
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1350638680
Short name T235
Test name
Test status
Simulation time 144871385 ps
CPU time 0.84 seconds
Started Jul 12 05:43:50 PM PDT 24
Finished Jul 12 05:43:52 PM PDT 24
Peak memory 196376 kb
Host smart-5d1902f3-f4a5-4025-a4db-5d3de4f85fba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350638680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1350638680
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.279015589
Short name T394
Test name
Test status
Simulation time 36282097 ps
CPU time 0.97 seconds
Started Jul 12 05:43:53 PM PDT 24
Finished Jul 12 05:43:56 PM PDT 24
Peak memory 196624 kb
Host smart-83d3b177-3182-4c23-b2c7-7eb4cd43ceb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279015589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.279015589
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3065495550
Short name T264
Test name
Test status
Simulation time 291941569 ps
CPU time 3.07 seconds
Started Jul 12 05:43:55 PM PDT 24
Finished Jul 12 05:43:59 PM PDT 24
Peak memory 196948 kb
Host smart-254d30de-f347-4fdf-940e-8d882784ba20
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065495550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3065495550
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.802842951
Short name T55
Test name
Test status
Simulation time 115258793 ps
CPU time 2.52 seconds
Started Jul 12 05:43:52 PM PDT 24
Finished Jul 12 05:43:56 PM PDT 24
Peak memory 198900 kb
Host smart-96b36dc8-f28a-4be7-8f21-b82d53645c3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802842951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.
802842951
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2346247322
Short name T157
Test name
Test status
Simulation time 53816013 ps
CPU time 1.09 seconds
Started Jul 12 05:43:52 PM PDT 24
Finished Jul 12 05:43:54 PM PDT 24
Peak memory 196524 kb
Host smart-7c365e7e-defe-4373-8e93-256c99c4e8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346247322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2346247322
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3143008713
Short name T291
Test name
Test status
Simulation time 125707983 ps
CPU time 1 seconds
Started Jul 12 05:43:52 PM PDT 24
Finished Jul 12 05:43:54 PM PDT 24
Peak memory 197168 kb
Host smart-f3697676-2eff-4911-9539-4f0901a51cb9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143008713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3143008713
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.701085071
Short name T485
Test name
Test status
Simulation time 594377278 ps
CPU time 6.7 seconds
Started Jul 12 05:43:53 PM PDT 24
Finished Jul 12 05:44:02 PM PDT 24
Peak memory 198672 kb
Host smart-54354ac1-dbd4-4e80-98b0-65cf51bbc0dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701085071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ran
dom_long_reg_writes_reg_reads.701085071
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1629116614
Short name T686
Test name
Test status
Simulation time 37696887 ps
CPU time 0.69 seconds
Started Jul 12 05:44:05 PM PDT 24
Finished Jul 12 05:44:07 PM PDT 24
Peak memory 195488 kb
Host smart-d600fc4c-b3ee-4b81-8dc5-6569da1f5a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629116614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1629116614
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3055906731
Short name T317
Test name
Test status
Simulation time 181157126 ps
CPU time 0.81 seconds
Started Jul 12 05:43:55 PM PDT 24
Finished Jul 12 05:43:57 PM PDT 24
Peak memory 195748 kb
Host smart-47fe287c-98a3-4bc2-9601-3adf6343ca40
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055906731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3055906731
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.727836404
Short name T496
Test name
Test status
Simulation time 12031870572 ps
CPU time 84.67 seconds
Started Jul 12 05:43:54 PM PDT 24
Finished Jul 12 05:45:20 PM PDT 24
Peak memory 198732 kb
Host smart-6f1e6911-ba05-4474-b9ad-fce4790ffa63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727836404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.727836404
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1988103442
Short name T403
Test name
Test status
Simulation time 80007901 ps
CPU time 0.57 seconds
Started Jul 12 05:43:56 PM PDT 24
Finished Jul 12 05:43:57 PM PDT 24
Peak memory 195352 kb
Host smart-c01d2ca0-854c-4ffb-b5b2-19ff5c01f19e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988103442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1988103442
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3718616273
Short name T656
Test name
Test status
Simulation time 56375155 ps
CPU time 0.87 seconds
Started Jul 12 05:44:34 PM PDT 24
Finished Jul 12 05:44:37 PM PDT 24
Peak memory 196388 kb
Host smart-40f3d991-2403-4d5f-85a4-2f8f295f694d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718616273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3718616273
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1828758122
Short name T475
Test name
Test status
Simulation time 411232602 ps
CPU time 13.66 seconds
Started Jul 12 05:43:53 PM PDT 24
Finished Jul 12 05:44:08 PM PDT 24
Peak memory 196088 kb
Host smart-92116298-c412-4259-be30-f5174bd9126a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828758122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1828758122
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3719359301
Short name T248
Test name
Test status
Simulation time 92063951 ps
CPU time 1.06 seconds
Started Jul 12 05:43:59 PM PDT 24
Finished Jul 12 05:44:01 PM PDT 24
Peak memory 197128 kb
Host smart-4c5379bd-9cfc-4db3-ab0c-6cfe302cc42c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719359301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3719359301
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2179948885
Short name T498
Test name
Test status
Simulation time 85260547 ps
CPU time 1.25 seconds
Started Jul 12 05:43:53 PM PDT 24
Finished Jul 12 05:43:55 PM PDT 24
Peak memory 196428 kb
Host smart-48c2b252-d078-4eb4-a257-1a3160e6533a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179948885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2179948885
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1346788856
Short name T306
Test name
Test status
Simulation time 87116574 ps
CPU time 3.21 seconds
Started Jul 12 05:43:53 PM PDT 24
Finished Jul 12 05:43:58 PM PDT 24
Peak memory 197112 kb
Host smart-3ebb7c4e-b991-4b3c-b211-9cec2a8a062a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346788856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1346788856
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.237910225
Short name T226
Test name
Test status
Simulation time 1727167110 ps
CPU time 2.17 seconds
Started Jul 12 05:44:00 PM PDT 24
Finished Jul 12 05:44:05 PM PDT 24
Peak memory 197376 kb
Host smart-7bf2a7d9-34ff-43b5-814f-1c5fee523923
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237910225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
237910225
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.762924574
Short name T271
Test name
Test status
Simulation time 49786430 ps
CPU time 1.14 seconds
Started Jul 12 05:44:00 PM PDT 24
Finished Jul 12 05:44:04 PM PDT 24
Peak memory 196828 kb
Host smart-39bb8f6d-2987-43fd-ae84-d1257fdf86cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762924574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.762924574
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1644940235
Short name T447
Test name
Test status
Simulation time 169013997 ps
CPU time 1.09 seconds
Started Jul 12 05:43:53 PM PDT 24
Finished Jul 12 05:43:55 PM PDT 24
Peak memory 196560 kb
Host smart-a63c5f34-1a19-4d66-aa34-6b6c1e84d980
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644940235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1644940235
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.4038149008
Short name T265
Test name
Test status
Simulation time 77450450 ps
CPU time 1.29 seconds
Started Jul 12 05:43:53 PM PDT 24
Finished Jul 12 05:43:55 PM PDT 24
Peak memory 198604 kb
Host smart-a1c9f6eb-b389-43b1-b174-d92beae7f30d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038149008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.4038149008
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.4129751214
Short name T436
Test name
Test status
Simulation time 82619213 ps
CPU time 0.95 seconds
Started Jul 12 05:43:50 PM PDT 24
Finished Jul 12 05:43:52 PM PDT 24
Peak memory 196920 kb
Host smart-65cadd8d-8be6-42ef-bfb1-8df1a1925165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129751214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.4129751214
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3674287926
Short name T680
Test name
Test status
Simulation time 43469778 ps
CPU time 1.26 seconds
Started Jul 12 05:43:55 PM PDT 24
Finished Jul 12 05:43:57 PM PDT 24
Peak memory 197376 kb
Host smart-7d989291-f270-4d9a-a6f0-104671655153
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674287926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3674287926
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2919852070
Short name T195
Test name
Test status
Simulation time 7187767445 ps
CPU time 92.2 seconds
Started Jul 12 05:43:53 PM PDT 24
Finished Jul 12 05:45:26 PM PDT 24
Peak memory 198652 kb
Host smart-e5b628b8-e2e9-48ae-8aad-34b3e76655f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919852070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2919852070
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1726060226
Short name T52
Test name
Test status
Simulation time 20330781 ps
CPU time 0.6 seconds
Started Jul 12 05:44:03 PM PDT 24
Finished Jul 12 05:44:05 PM PDT 24
Peak memory 194648 kb
Host smart-ee9b9a1d-6f0a-4c38-b35b-dc259922610d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726060226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1726060226
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3375581465
Short name T665
Test name
Test status
Simulation time 14343576 ps
CPU time 0.63 seconds
Started Jul 12 05:43:57 PM PDT 24
Finished Jul 12 05:43:58 PM PDT 24
Peak memory 194652 kb
Host smart-350a4238-ed76-4346-8f60-25970f986ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375581465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3375581465
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3887613652
Short name T660
Test name
Test status
Simulation time 745481184 ps
CPU time 23.37 seconds
Started Jul 12 05:44:07 PM PDT 24
Finished Jul 12 05:44:31 PM PDT 24
Peak memory 197748 kb
Host smart-32b9ea6b-ff3a-4fe0-9343-75c792c09346
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887613652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3887613652
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3590997182
Short name T538
Test name
Test status
Simulation time 35791429 ps
CPU time 0.75 seconds
Started Jul 12 05:44:06 PM PDT 24
Finished Jul 12 05:44:07 PM PDT 24
Peak memory 196344 kb
Host smart-ac32115e-b923-4d47-a47e-443f895ce93a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590997182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3590997182
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.836077818
Short name T303
Test name
Test status
Simulation time 54743034 ps
CPU time 0.99 seconds
Started Jul 12 05:44:07 PM PDT 24
Finished Jul 12 05:44:09 PM PDT 24
Peak memory 197668 kb
Host smart-5ebcdcc2-c048-4e51-81f4-8a73086f6b07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836077818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.836077818
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1769880520
Short name T533
Test name
Test status
Simulation time 312725630 ps
CPU time 3.09 seconds
Started Jul 12 05:43:58 PM PDT 24
Finished Jul 12 05:44:02 PM PDT 24
Peak memory 196892 kb
Host smart-dd245770-1d33-4951-8b25-80ec34737f74
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769880520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1769880520
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3964007176
Short name T497
Test name
Test status
Simulation time 175396742 ps
CPU time 1.12 seconds
Started Jul 12 05:44:21 PM PDT 24
Finished Jul 12 05:44:23 PM PDT 24
Peak memory 197956 kb
Host smart-e34bfa22-af97-4fd8-95cc-99878946eaed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964007176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3964007176
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.4032274231
Short name T147
Test name
Test status
Simulation time 100206943 ps
CPU time 0.97 seconds
Started Jul 12 05:44:03 PM PDT 24
Finished Jul 12 05:44:06 PM PDT 24
Peak memory 196672 kb
Host smart-33919406-98e6-46be-85e9-e281c8ee2904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032274231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.4032274231
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.4162172976
Short name T309
Test name
Test status
Simulation time 40215045 ps
CPU time 0.74 seconds
Started Jul 12 05:44:00 PM PDT 24
Finished Jul 12 05:44:02 PM PDT 24
Peak memory 195576 kb
Host smart-8a598907-d1a8-499b-b1af-756d73b45a69
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162172976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.4162172976
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3880417166
Short name T166
Test name
Test status
Simulation time 343826617 ps
CPU time 3.64 seconds
Started Jul 12 05:44:01 PM PDT 24
Finished Jul 12 05:44:07 PM PDT 24
Peak memory 198572 kb
Host smart-e0f5950d-f946-47e2-8933-db0555e75b94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880417166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3880417166
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1050880691
Short name T428
Test name
Test status
Simulation time 61073770 ps
CPU time 1.11 seconds
Started Jul 12 05:43:51 PM PDT 24
Finished Jul 12 05:43:53 PM PDT 24
Peak memory 196912 kb
Host smart-4de222cd-b723-416b-94d6-63eb6f875357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050880691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1050880691
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1974689930
Short name T121
Test name
Test status
Simulation time 60449205 ps
CPU time 0.8 seconds
Started Jul 12 05:43:55 PM PDT 24
Finished Jul 12 05:43:57 PM PDT 24
Peak memory 195852 kb
Host smart-d3b85ef2-81e3-4557-b4fd-c02fe9f22ddc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974689930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1974689930
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.981296490
Short name T9
Test name
Test status
Simulation time 6906383666 ps
CPU time 86.97 seconds
Started Jul 12 05:44:04 PM PDT 24
Finished Jul 12 05:45:32 PM PDT 24
Peak memory 198720 kb
Host smart-24d50a79-eed7-49ad-8540-24022ad9143b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981296490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.981296490
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3475826910
Short name T192
Test name
Test status
Simulation time 39809399 ps
CPU time 0.57 seconds
Started Jul 12 05:44:20 PM PDT 24
Finished Jul 12 05:44:21 PM PDT 24
Peak memory 196256 kb
Host smart-f42ecfea-8c38-49dc-8e01-a4b2ab8055ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475826910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3475826910
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1742052468
Short name T184
Test name
Test status
Simulation time 230503053 ps
CPU time 0.94 seconds
Started Jul 12 05:44:00 PM PDT 24
Finished Jul 12 05:44:02 PM PDT 24
Peak memory 197672 kb
Host smart-a7ceef05-508f-4670-a530-f2d30b210cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742052468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1742052468
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.56822359
Short name T454
Test name
Test status
Simulation time 767561880 ps
CPU time 20.74 seconds
Started Jul 12 05:44:01 PM PDT 24
Finished Jul 12 05:44:24 PM PDT 24
Peak memory 198680 kb
Host smart-39c4e338-9266-4f78-a162-2dd362a541b2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56822359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stress
.56822359
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.4253155542
Short name T636
Test name
Test status
Simulation time 279923290 ps
CPU time 1.1 seconds
Started Jul 12 05:44:03 PM PDT 24
Finished Jul 12 05:44:06 PM PDT 24
Peak memory 197296 kb
Host smart-9099b53c-f488-477e-ae77-543971a04e21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253155542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.4253155542
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.362981694
Short name T207
Test name
Test status
Simulation time 15783280 ps
CPU time 0.7 seconds
Started Jul 12 05:44:23 PM PDT 24
Finished Jul 12 05:44:25 PM PDT 24
Peak memory 194844 kb
Host smart-7227d55d-b98f-4c75-bf80-a229ea6593be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362981694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.362981694
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1937391908
Short name T547
Test name
Test status
Simulation time 44208521 ps
CPU time 1.77 seconds
Started Jul 12 05:44:01 PM PDT 24
Finished Jul 12 05:44:05 PM PDT 24
Peak memory 198644 kb
Host smart-75668a51-2e86-4fd8-8b11-57bc86280c5c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937391908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1937391908
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.327176902
Short name T319
Test name
Test status
Simulation time 97777735 ps
CPU time 2.01 seconds
Started Jul 12 05:44:00 PM PDT 24
Finished Jul 12 05:44:05 PM PDT 24
Peak memory 196812 kb
Host smart-425b3c8f-5034-42b1-8775-d54b4b01c4a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327176902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
327176902
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.485673325
Short name T676
Test name
Test status
Simulation time 27972286 ps
CPU time 0.78 seconds
Started Jul 12 05:44:03 PM PDT 24
Finished Jul 12 05:44:06 PM PDT 24
Peak memory 196852 kb
Host smart-0217db11-7d93-453c-8300-5f07c88f5993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485673325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.485673325
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.272698562
Short name T118
Test name
Test status
Simulation time 59250136 ps
CPU time 0.99 seconds
Started Jul 12 05:44:00 PM PDT 24
Finished Jul 12 05:44:03 PM PDT 24
Peak memory 196568 kb
Host smart-8d08aca4-a11a-4b56-8dbf-a9b33870c85d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272698562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.272698562
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.367077542
Short name T76
Test name
Test status
Simulation time 942562112 ps
CPU time 5.52 seconds
Started Jul 12 05:44:06 PM PDT 24
Finished Jul 12 05:44:12 PM PDT 24
Peak memory 198568 kb
Host smart-9ed7cb38-db9a-4f98-ab62-c045468d8f75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367077542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.367077542
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1410582781
Short name T114
Test name
Test status
Simulation time 168586652 ps
CPU time 0.98 seconds
Started Jul 12 05:44:21 PM PDT 24
Finished Jul 12 05:44:23 PM PDT 24
Peak memory 196312 kb
Host smart-d0bdb39d-3a05-4d21-8d93-97398d99fe19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410582781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1410582781
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3822877870
Short name T178
Test name
Test status
Simulation time 83808940 ps
CPU time 0.97 seconds
Started Jul 12 05:44:02 PM PDT 24
Finished Jul 12 05:44:05 PM PDT 24
Peak memory 196176 kb
Host smart-74bc5290-730b-464b-9468-7c73267a4b3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822877870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3822877870
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2288080024
Short name T348
Test name
Test status
Simulation time 52381934876 ps
CPU time 144.7 seconds
Started Jul 12 05:44:20 PM PDT 24
Finished Jul 12 05:46:46 PM PDT 24
Peak memory 198668 kb
Host smart-0bd20da8-291f-4736-bdd6-7a47003dbd6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288080024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2288080024
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.4186541317
Short name T513
Test name
Test status
Simulation time 41162469 ps
CPU time 0.58 seconds
Started Jul 12 05:44:12 PM PDT 24
Finished Jul 12 05:44:14 PM PDT 24
Peak memory 194856 kb
Host smart-dbed0216-e731-46dc-91f6-28496532fb62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186541317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.4186541317
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1973496919
Short name T289
Test name
Test status
Simulation time 79395817 ps
CPU time 0.7 seconds
Started Jul 12 05:44:12 PM PDT 24
Finished Jul 12 05:44:13 PM PDT 24
Peak memory 195812 kb
Host smart-515ee658-f73e-41f1-8cea-16a22f000c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973496919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1973496919
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1749148195
Short name T407
Test name
Test status
Simulation time 2572675557 ps
CPU time 22.18 seconds
Started Jul 12 05:43:59 PM PDT 24
Finished Jul 12 05:44:22 PM PDT 24
Peak memory 197992 kb
Host smart-945f3d2c-bd82-4194-a519-f89460398d1e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749148195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1749148195
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2915494524
Short name T297
Test name
Test status
Simulation time 24064472 ps
CPU time 0.69 seconds
Started Jul 12 05:44:04 PM PDT 24
Finished Jul 12 05:44:06 PM PDT 24
Peak memory 195180 kb
Host smart-dd660483-1259-423c-9bd1-3f8532130687
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915494524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2915494524
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.3306816214
Short name T57
Test name
Test status
Simulation time 47793005 ps
CPU time 0.97 seconds
Started Jul 12 05:44:02 PM PDT 24
Finished Jul 12 05:44:05 PM PDT 24
Peak memory 197376 kb
Host smart-925fd5cc-46f5-4816-8053-6c22bd42998b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306816214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.3306816214
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3715039245
Short name T165
Test name
Test status
Simulation time 319296123 ps
CPU time 2.62 seconds
Started Jul 12 05:44:00 PM PDT 24
Finished Jul 12 05:44:05 PM PDT 24
Peak memory 197004 kb
Host smart-ef849834-9b50-403d-819e-f8a177c30bc2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715039245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3715039245
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3026586743
Short name T196
Test name
Test status
Simulation time 333778997 ps
CPU time 2.83 seconds
Started Jul 12 05:44:00 PM PDT 24
Finished Jul 12 05:44:06 PM PDT 24
Peak memory 197804 kb
Host smart-170c3447-6e30-42b3-8146-5c40b205e473
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026586743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3026586743
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1406005082
Short name T127
Test name
Test status
Simulation time 106157685 ps
CPU time 1.09 seconds
Started Jul 12 05:44:21 PM PDT 24
Finished Jul 12 05:44:23 PM PDT 24
Peak memory 198608 kb
Host smart-bc5b278f-e144-4c02-a416-2d5eb0375581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406005082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1406005082
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1654261893
Short name T506
Test name
Test status
Simulation time 39994248 ps
CPU time 0.93 seconds
Started Jul 12 05:44:01 PM PDT 24
Finished Jul 12 05:44:04 PM PDT 24
Peak memory 197368 kb
Host smart-8222a0be-4a36-44e9-9452-e3e79c9a9dcc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654261893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1654261893
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.426374714
Short name T244
Test name
Test status
Simulation time 648905975 ps
CPU time 5.24 seconds
Started Jul 12 05:44:07 PM PDT 24
Finished Jul 12 05:44:13 PM PDT 24
Peak memory 198848 kb
Host smart-0cd8394b-2d3d-419d-8152-8f6d5b3e6107
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426374714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ran
dom_long_reg_writes_reg_reads.426374714
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1818342170
Short name T240
Test name
Test status
Simulation time 272997451 ps
CPU time 1.11 seconds
Started Jul 12 05:44:08 PM PDT 24
Finished Jul 12 05:44:09 PM PDT 24
Peak memory 197156 kb
Host smart-9e1bed03-dd08-4c79-81f6-a7725884cae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818342170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1818342170
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.4073977230
Short name T393
Test name
Test status
Simulation time 123508947 ps
CPU time 0.97 seconds
Started Jul 12 05:44:06 PM PDT 24
Finished Jul 12 05:44:08 PM PDT 24
Peak memory 197220 kb
Host smart-ea49419e-d53e-43cd-bd63-a87b3f2e5618
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073977230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.4073977230
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.220000331
Short name T272
Test name
Test status
Simulation time 11797021139 ps
CPU time 167 seconds
Started Jul 12 05:44:06 PM PDT 24
Finished Jul 12 05:46:54 PM PDT 24
Peak memory 198776 kb
Host smart-83c4885f-2898-4511-9777-5f431d7d56eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220000331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.220000331
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.203522150
Short name T466
Test name
Test status
Simulation time 29832279356 ps
CPU time 469.91 seconds
Started Jul 12 05:44:06 PM PDT 24
Finished Jul 12 05:51:57 PM PDT 24
Peak memory 198908 kb
Host smart-b1d3df79-f5e4-4016-8e47-962e5b19523c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=203522150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.203522150
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.950996432
Short name T574
Test name
Test status
Simulation time 177710646 ps
CPU time 0.61 seconds
Started Jul 12 05:44:08 PM PDT 24
Finished Jul 12 05:44:09 PM PDT 24
Peak memory 195296 kb
Host smart-0e9d5dbb-d00f-4d54-b786-9e1fd86d871a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950996432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.950996432
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.4001068425
Short name T541
Test name
Test status
Simulation time 90391156 ps
CPU time 0.69 seconds
Started Jul 12 05:44:06 PM PDT 24
Finished Jul 12 05:44:07 PM PDT 24
Peak memory 194844 kb
Host smart-9caffa5d-983a-425c-acea-2310159610b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001068425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.4001068425
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.212426377
Short name T457
Test name
Test status
Simulation time 441596761 ps
CPU time 12.66 seconds
Started Jul 12 05:44:08 PM PDT 24
Finished Jul 12 05:44:21 PM PDT 24
Peak memory 197432 kb
Host smart-412a6bc7-dae6-4cc9-800d-31a9004e93b3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212426377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.212426377
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.331076541
Short name T452
Test name
Test status
Simulation time 103377337 ps
CPU time 1.03 seconds
Started Jul 12 05:44:10 PM PDT 24
Finished Jul 12 05:44:12 PM PDT 24
Peak memory 197016 kb
Host smart-064460cd-a0b5-41d0-8794-7415cb747fdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331076541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.331076541
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.3157859290
Short name T397
Test name
Test status
Simulation time 151056758 ps
CPU time 1.08 seconds
Started Jul 12 05:44:13 PM PDT 24
Finished Jul 12 05:44:15 PM PDT 24
Peak memory 196504 kb
Host smart-03ad52b9-c181-47f0-ab3e-d14c90dda8b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157859290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.3157859290
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1686252187
Short name T588
Test name
Test status
Simulation time 322026649 ps
CPU time 3.42 seconds
Started Jul 12 05:44:07 PM PDT 24
Finished Jul 12 05:44:11 PM PDT 24
Peak memory 198708 kb
Host smart-01003a61-bdfc-4a33-a6fc-91a54c274dce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686252187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1686252187
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3726158441
Short name T219
Test name
Test status
Simulation time 145322756 ps
CPU time 2.56 seconds
Started Jul 12 05:44:08 PM PDT 24
Finished Jul 12 05:44:11 PM PDT 24
Peak memory 196400 kb
Host smart-308137b5-c890-4483-a66c-aa899ed8a91f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726158441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3726158441
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.245851041
Short name T654
Test name
Test status
Simulation time 112959933 ps
CPU time 1.1 seconds
Started Jul 12 05:44:13 PM PDT 24
Finished Jul 12 05:44:15 PM PDT 24
Peak memory 197180 kb
Host smart-7f32a784-489e-4b49-9fb9-b1d346a393b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245851041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.245851041
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3912583749
Short name T221
Test name
Test status
Simulation time 103817320 ps
CPU time 0.78 seconds
Started Jul 12 05:44:11 PM PDT 24
Finished Jul 12 05:44:13 PM PDT 24
Peak memory 194948 kb
Host smart-a130355e-dd6e-4fb2-99a6-f3dbe4ec75c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912583749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3912583749
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1557232872
Short name T687
Test name
Test status
Simulation time 1527091077 ps
CPU time 2.88 seconds
Started Jul 12 05:44:13 PM PDT 24
Finished Jul 12 05:44:17 PM PDT 24
Peak memory 198596 kb
Host smart-f568e8d0-2c63-43c8-ad0d-4cbbe2ff4d67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557232872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1557232872
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.523777761
Short name T575
Test name
Test status
Simulation time 177358704 ps
CPU time 1.18 seconds
Started Jul 12 05:44:14 PM PDT 24
Finished Jul 12 05:44:17 PM PDT 24
Peak memory 197736 kb
Host smart-33da2d2b-0650-4589-820c-1f20a95f0401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523777761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.523777761
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.638694538
Short name T405
Test name
Test status
Simulation time 233792337 ps
CPU time 1.27 seconds
Started Jul 12 05:44:10 PM PDT 24
Finished Jul 12 05:44:12 PM PDT 24
Peak memory 197264 kb
Host smart-a8831163-6e4f-4fc6-9f97-6274fd6f0648
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638694538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.638694538
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.4203288612
Short name T365
Test name
Test status
Simulation time 50208170843 ps
CPU time 200.71 seconds
Started Jul 12 05:44:09 PM PDT 24
Finished Jul 12 05:47:31 PM PDT 24
Peak memory 198668 kb
Host smart-f8ca67eb-8e2c-45b9-8b3a-f26c32bf83f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203288612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.4203288612
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.1184027853
Short name T390
Test name
Test status
Simulation time 34740701350 ps
CPU time 798.06 seconds
Started Jul 12 05:44:09 PM PDT 24
Finished Jul 12 05:57:29 PM PDT 24
Peak memory 198900 kb
Host smart-08d00f93-ac08-4bc3-a58e-75a5352d14b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1184027853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.1184027853
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.751443020
Short name T417
Test name
Test status
Simulation time 37886926 ps
CPU time 0.56 seconds
Started Jul 12 05:43:18 PM PDT 24
Finished Jul 12 05:43:20 PM PDT 24
Peak memory 193444 kb
Host smart-4808ffe4-b883-47ab-b044-58190ec45f23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751443020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.751443020
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1729800282
Short name T113
Test name
Test status
Simulation time 17380527 ps
CPU time 0.61 seconds
Started Jul 12 05:43:18 PM PDT 24
Finished Jul 12 05:43:20 PM PDT 24
Peak memory 194612 kb
Host smart-5c4e7ae7-10cc-4543-976c-0b8185691981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729800282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1729800282
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1589677459
Short name T328
Test name
Test status
Simulation time 290737728 ps
CPU time 15.36 seconds
Started Jul 12 05:43:20 PM PDT 24
Finished Jul 12 05:43:36 PM PDT 24
Peak memory 197396 kb
Host smart-bfd4fade-9b87-4cdd-af6b-079b5c92b258
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589677459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1589677459
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.3816446137
Short name T334
Test name
Test status
Simulation time 81760921 ps
CPU time 0.68 seconds
Started Jul 12 05:43:16 PM PDT 24
Finished Jul 12 05:43:17 PM PDT 24
Peak memory 196056 kb
Host smart-9c2aacda-b76f-4932-b9ce-1e633f417ec0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816446137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3816446137
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2167582311
Short name T152
Test name
Test status
Simulation time 28414334 ps
CPU time 0.89 seconds
Started Jul 12 05:43:17 PM PDT 24
Finished Jul 12 05:43:19 PM PDT 24
Peak memory 197308 kb
Host smart-0f9c3cb5-c0ac-4bb1-8cd2-ed757758d96b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167582311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2167582311
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2985806663
Short name T438
Test name
Test status
Simulation time 324754299 ps
CPU time 3.42 seconds
Started Jul 12 05:43:18 PM PDT 24
Finished Jul 12 05:43:23 PM PDT 24
Peak memory 198656 kb
Host smart-a9f3d4ee-314b-4b5e-a3c6-8cd56e4dda18
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985806663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2985806663
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2133363701
Short name T411
Test name
Test status
Simulation time 568505231 ps
CPU time 2.81 seconds
Started Jul 12 05:43:18 PM PDT 24
Finished Jul 12 05:43:22 PM PDT 24
Peak memory 198640 kb
Host smart-7a9ca0c1-b416-4d22-bb2e-f95232cd0c51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133363701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2133363701
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3552128870
Short name T145
Test name
Test status
Simulation time 143530800 ps
CPU time 1.29 seconds
Started Jul 12 05:43:18 PM PDT 24
Finished Jul 12 05:43:20 PM PDT 24
Peak memory 196552 kb
Host smart-0467def0-f2fd-48fe-941f-868338c80b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552128870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3552128870
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3088636551
Short name T661
Test name
Test status
Simulation time 48671161 ps
CPU time 0.88 seconds
Started Jul 12 05:43:17 PM PDT 24
Finished Jul 12 05:43:18 PM PDT 24
Peak memory 196500 kb
Host smart-10000a56-072b-4a7a-a08f-fa2ec47496aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088636551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3088636551
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1340335617
Short name T350
Test name
Test status
Simulation time 1929467837 ps
CPU time 4.07 seconds
Started Jul 12 05:43:22 PM PDT 24
Finished Jul 12 05:43:27 PM PDT 24
Peak memory 198704 kb
Host smart-8a9e4692-779a-4a52-961e-705c46708dd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340335617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1340335617
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1353571582
Short name T49
Test name
Test status
Simulation time 153911148 ps
CPU time 0.87 seconds
Started Jul 12 05:43:19 PM PDT 24
Finished Jul 12 05:43:21 PM PDT 24
Peak memory 214364 kb
Host smart-dcfe0590-f139-4d4f-b545-65bac8fa1e22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353571582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1353571582
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.4097746393
Short name T160
Test name
Test status
Simulation time 36012014 ps
CPU time 1.07 seconds
Started Jul 12 05:43:19 PM PDT 24
Finished Jul 12 05:43:21 PM PDT 24
Peak memory 196184 kb
Host smart-1015949f-7143-4ea6-8ea8-724612e21b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097746393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.4097746393
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3670397310
Short name T695
Test name
Test status
Simulation time 207035865 ps
CPU time 1.54 seconds
Started Jul 12 05:43:19 PM PDT 24
Finished Jul 12 05:43:22 PM PDT 24
Peak memory 198656 kb
Host smart-c3d90647-cdfb-4ba8-8f5e-a974b6147553
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670397310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3670397310
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1975759132
Short name T26
Test name
Test status
Simulation time 72632879733 ps
CPU time 208 seconds
Started Jul 12 05:43:19 PM PDT 24
Finished Jul 12 05:46:48 PM PDT 24
Peak memory 198812 kb
Host smart-7a8e79b8-201c-4578-9a7f-79211b059064
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975759132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1975759132
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.94268688
Short name T423
Test name
Test status
Simulation time 17755489 ps
CPU time 0.59 seconds
Started Jul 12 05:44:08 PM PDT 24
Finished Jul 12 05:44:10 PM PDT 24
Peak memory 194524 kb
Host smart-fa02ef25-99c3-4d70-9349-5a04a6ca3c3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94268688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.94268688
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3270438362
Short name T440
Test name
Test status
Simulation time 146916450 ps
CPU time 0.89 seconds
Started Jul 12 05:44:05 PM PDT 24
Finished Jul 12 05:44:07 PM PDT 24
Peak memory 197004 kb
Host smart-fcaa8f0a-fad7-4d85-9802-ffffcf1a159e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270438362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3270438362
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1590570969
Short name T344
Test name
Test status
Simulation time 408140779 ps
CPU time 10.96 seconds
Started Jul 12 05:44:05 PM PDT 24
Finished Jul 12 05:44:17 PM PDT 24
Peak memory 197644 kb
Host smart-a0cb944a-8195-4253-b59e-24285d0bbb2c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590570969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1590570969
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1719079947
Short name T268
Test name
Test status
Simulation time 33783759 ps
CPU time 0.64 seconds
Started Jul 12 05:44:20 PM PDT 24
Finished Jul 12 05:44:22 PM PDT 24
Peak memory 194956 kb
Host smart-f0a7f948-3bbc-4879-a938-4607d601e75c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719079947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1719079947
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2960210332
Short name T120
Test name
Test status
Simulation time 52739155 ps
CPU time 1.37 seconds
Started Jul 12 05:44:09 PM PDT 24
Finished Jul 12 05:44:12 PM PDT 24
Peak memory 197620 kb
Host smart-056d8819-50c8-42cd-b15c-df2eff035468
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960210332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2960210332
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.645078089
Short name T175
Test name
Test status
Simulation time 63499082 ps
CPU time 2.52 seconds
Started Jul 12 05:44:10 PM PDT 24
Finished Jul 12 05:44:13 PM PDT 24
Peak memory 198856 kb
Host smart-91c54fc4-2e6f-473c-86ab-d40f4ab83828
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645078089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.645078089
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3017330041
Short name T613
Test name
Test status
Simulation time 360555332 ps
CPU time 2.15 seconds
Started Jul 12 05:44:08 PM PDT 24
Finished Jul 12 05:44:11 PM PDT 24
Peak memory 196496 kb
Host smart-30585e06-891e-43ab-b19b-81333a48ddc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017330041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3017330041
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3855284434
Short name T262
Test name
Test status
Simulation time 26342129 ps
CPU time 0.85 seconds
Started Jul 12 05:44:20 PM PDT 24
Finished Jul 12 05:44:22 PM PDT 24
Peak memory 197248 kb
Host smart-ae8a0bfc-e53d-401a-89e7-784fcb0dc853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855284434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3855284434
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3777789742
Short name T366
Test name
Test status
Simulation time 207407654 ps
CPU time 1.08 seconds
Started Jul 12 05:44:09 PM PDT 24
Finished Jul 12 05:44:12 PM PDT 24
Peak memory 196676 kb
Host smart-7404133c-9781-4a76-98d7-e261b2042e9c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777789742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3777789742
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2497691991
Short name T579
Test name
Test status
Simulation time 172989094 ps
CPU time 1.54 seconds
Started Jul 12 05:44:09 PM PDT 24
Finished Jul 12 05:44:11 PM PDT 24
Peak memory 198640 kb
Host smart-8e3445e3-0cf7-4572-9a0a-752ee71bf758
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497691991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2497691991
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2372594986
Short name T473
Test name
Test status
Simulation time 229283843 ps
CPU time 1.11 seconds
Started Jul 12 05:44:06 PM PDT 24
Finished Jul 12 05:44:08 PM PDT 24
Peak memory 197180 kb
Host smart-d49d214f-b1a6-4e3d-b24c-21e6cc0d896b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372594986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2372594986
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1009647610
Short name T492
Test name
Test status
Simulation time 204696847 ps
CPU time 1.09 seconds
Started Jul 12 05:44:07 PM PDT 24
Finished Jul 12 05:44:09 PM PDT 24
Peak memory 196420 kb
Host smart-e537e6d1-2031-4f18-a65b-66dbf141d320
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009647610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1009647610
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2794363712
Short name T519
Test name
Test status
Simulation time 73564316436 ps
CPU time 100.33 seconds
Started Jul 12 05:44:08 PM PDT 24
Finished Jul 12 05:45:49 PM PDT 24
Peak memory 198760 kb
Host smart-f2ed3ef3-ac0a-4604-a309-71db0e560802
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794363712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2794363712
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.911289833
Short name T643
Test name
Test status
Simulation time 4133372557 ps
CPU time 132.48 seconds
Started Jul 12 05:44:10 PM PDT 24
Finished Jul 12 05:46:24 PM PDT 24
Peak memory 198760 kb
Host smart-3196dbcc-194c-42bb-a1f8-c00411d84efb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=911289833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.911289833
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3648379913
Short name T714
Test name
Test status
Simulation time 27408526 ps
CPU time 0.55 seconds
Started Jul 12 05:44:15 PM PDT 24
Finished Jul 12 05:44:17 PM PDT 24
Peak memory 194584 kb
Host smart-105b4f35-eaac-47c8-a1f8-f5e8993f6508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648379913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3648379913
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3894295238
Short name T662
Test name
Test status
Simulation time 46428020 ps
CPU time 0.81 seconds
Started Jul 12 05:44:15 PM PDT 24
Finished Jul 12 05:44:17 PM PDT 24
Peak memory 196000 kb
Host smart-1e9e4a3c-3c38-43dc-b836-f9ca9905beb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894295238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3894295238
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1822644367
Short name T415
Test name
Test status
Simulation time 1261733046 ps
CPU time 16.96 seconds
Started Jul 12 05:44:18 PM PDT 24
Finished Jul 12 05:44:35 PM PDT 24
Peak memory 196336 kb
Host smart-e6471eef-52f6-42b4-8b35-f322e5c87a39
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822644367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1822644367
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1472197320
Short name T432
Test name
Test status
Simulation time 167303545 ps
CPU time 1.05 seconds
Started Jul 12 05:44:13 PM PDT 24
Finished Jul 12 05:44:16 PM PDT 24
Peak memory 197196 kb
Host smart-f1995903-8d44-4bed-9cdd-704374dd7cc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472197320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1472197320
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.261995339
Short name T658
Test name
Test status
Simulation time 215426980 ps
CPU time 1.01 seconds
Started Jul 12 05:44:10 PM PDT 24
Finished Jul 12 05:44:12 PM PDT 24
Peak memory 197296 kb
Host smart-5d974826-c8b6-4daf-97e0-b59e16b352a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261995339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.261995339
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1204046659
Short name T703
Test name
Test status
Simulation time 315929047 ps
CPU time 3.26 seconds
Started Jul 12 05:44:15 PM PDT 24
Finished Jul 12 05:44:19 PM PDT 24
Peak memory 198676 kb
Host smart-716300e0-c827-4074-88d3-20257bf8e422
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204046659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1204046659
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2903633369
Short name T445
Test name
Test status
Simulation time 126620125 ps
CPU time 1.01 seconds
Started Jul 12 05:44:08 PM PDT 24
Finished Jul 12 05:44:11 PM PDT 24
Peak memory 196236 kb
Host smart-154c48a4-3645-435a-8696-77bc995f4cbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903633369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2903633369
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.4034339106
Short name T587
Test name
Test status
Simulation time 50655813 ps
CPU time 1.05 seconds
Started Jul 12 05:44:08 PM PDT 24
Finished Jul 12 05:44:10 PM PDT 24
Peak memory 196484 kb
Host smart-c27d08bf-a5e4-41bf-aa08-16902f0f3ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034339106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.4034339106
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.297212823
Short name T406
Test name
Test status
Simulation time 63834396 ps
CPU time 1.45 seconds
Started Jul 12 05:44:08 PM PDT 24
Finished Jul 12 05:44:10 PM PDT 24
Peak memory 198612 kb
Host smart-0a142dc9-1184-460b-bf20-a1fcf3f47be3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297212823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.297212823
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1674983106
Short name T182
Test name
Test status
Simulation time 1424021959 ps
CPU time 5.74 seconds
Started Jul 12 05:44:18 PM PDT 24
Finished Jul 12 05:44:24 PM PDT 24
Peak memory 198552 kb
Host smart-da1684ef-5c52-4b0b-8803-320b1b7aa5c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674983106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1674983106
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.799989132
Short name T459
Test name
Test status
Simulation time 95302462 ps
CPU time 1.11 seconds
Started Jul 12 05:44:07 PM PDT 24
Finished Jul 12 05:44:09 PM PDT 24
Peak memory 196316 kb
Host smart-24c3ac2d-2865-4e7f-8d08-51346fe70c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799989132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.799989132
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2591719344
Short name T567
Test name
Test status
Simulation time 499842405 ps
CPU time 1.1 seconds
Started Jul 12 05:44:12 PM PDT 24
Finished Jul 12 05:44:14 PM PDT 24
Peak memory 196316 kb
Host smart-ba444eb5-4d1d-40f7-9c9a-0021dbe362dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591719344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2591719344
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1353148876
Short name T69
Test name
Test status
Simulation time 18685455878 ps
CPU time 117.14 seconds
Started Jul 12 05:44:14 PM PDT 24
Finished Jul 12 05:46:13 PM PDT 24
Peak memory 198756 kb
Host smart-be316cbb-f7e6-4360-8ae6-4c9dcb8824e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353148876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1353148876
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.869372794
Short name T329
Test name
Test status
Simulation time 21851416 ps
CPU time 0.58 seconds
Started Jul 12 05:44:13 PM PDT 24
Finished Jul 12 05:44:15 PM PDT 24
Peak memory 195256 kb
Host smart-f18fe511-ab5c-4c51-b659-7f60350222b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869372794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.869372794
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3299323758
Short name T241
Test name
Test status
Simulation time 51075102 ps
CPU time 0.82 seconds
Started Jul 12 05:44:13 PM PDT 24
Finished Jul 12 05:44:16 PM PDT 24
Peak memory 196616 kb
Host smart-adf111b9-14a6-42bf-b228-3fc81cd445d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299323758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3299323758
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3192506786
Short name T542
Test name
Test status
Simulation time 206703158 ps
CPU time 7.47 seconds
Started Jul 12 05:44:16 PM PDT 24
Finished Jul 12 05:44:24 PM PDT 24
Peak memory 197572 kb
Host smart-8dd0adae-b28b-404f-abe4-31d5f8a71d38
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192506786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3192506786
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1143761980
Short name T448
Test name
Test status
Simulation time 300077676 ps
CPU time 1.02 seconds
Started Jul 12 05:44:14 PM PDT 24
Finished Jul 12 05:44:17 PM PDT 24
Peak memory 198712 kb
Host smart-16a955b0-9407-4b99-8bc0-d22f3ffc5616
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143761980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1143761980
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1338364709
Short name T562
Test name
Test status
Simulation time 89860946 ps
CPU time 1.17 seconds
Started Jul 12 05:44:16 PM PDT 24
Finished Jul 12 05:44:18 PM PDT 24
Peak memory 196512 kb
Host smart-b548718d-0c5e-485e-a381-81874bbc4a40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338364709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1338364709
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2177388410
Short name T504
Test name
Test status
Simulation time 60606837 ps
CPU time 2.45 seconds
Started Jul 12 05:44:16 PM PDT 24
Finished Jul 12 05:44:19 PM PDT 24
Peak memory 198652 kb
Host smart-28467340-47cb-46b8-aad8-143fc8c970d4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177388410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2177388410
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2569906213
Short name T124
Test name
Test status
Simulation time 531727051 ps
CPU time 2.84 seconds
Started Jul 12 05:44:17 PM PDT 24
Finished Jul 12 05:44:20 PM PDT 24
Peak memory 197892 kb
Host smart-c58b9f36-79e9-4e04-98b9-6a3f582d1c2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569906213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2569906213
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3105531565
Short name T705
Test name
Test status
Simulation time 121944685 ps
CPU time 1.18 seconds
Started Jul 12 05:44:15 PM PDT 24
Finished Jul 12 05:44:18 PM PDT 24
Peak memory 197928 kb
Host smart-627dda5b-25e7-4ca2-9ba5-0907f9eeeee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105531565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3105531565
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1641990729
Short name T215
Test name
Test status
Simulation time 29910268 ps
CPU time 0.71 seconds
Started Jul 12 05:44:17 PM PDT 24
Finished Jul 12 05:44:18 PM PDT 24
Peak memory 196084 kb
Host smart-80006ca1-fe8e-4890-80d8-af1e7d523c45
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641990729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1641990729
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.4228187937
Short name T583
Test name
Test status
Simulation time 317507325 ps
CPU time 5.06 seconds
Started Jul 12 05:44:13 PM PDT 24
Finished Jul 12 05:44:19 PM PDT 24
Peak memory 198608 kb
Host smart-aca388a5-9510-4d64-9702-46ea11d6b10b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228187937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.4228187937
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.215709626
Short name T193
Test name
Test status
Simulation time 51457518 ps
CPU time 0.98 seconds
Started Jul 12 05:44:16 PM PDT 24
Finished Jul 12 05:44:18 PM PDT 24
Peak memory 196432 kb
Host smart-dbd6ee78-621a-46ff-a789-a0675d85e28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215709626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.215709626
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2841008789
Short name T655
Test name
Test status
Simulation time 59243742 ps
CPU time 1.2 seconds
Started Jul 12 05:44:17 PM PDT 24
Finished Jul 12 05:44:19 PM PDT 24
Peak memory 197032 kb
Host smart-2350009a-3538-4d89-9138-0f02565bc8d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841008789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2841008789
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3698032119
Short name T551
Test name
Test status
Simulation time 74245501663 ps
CPU time 192.31 seconds
Started Jul 12 05:44:14 PM PDT 24
Finished Jul 12 05:47:28 PM PDT 24
Peak memory 198780 kb
Host smart-2519f3f0-f615-4ae2-8f3e-5b5fbad14789
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698032119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3698032119
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3239328690
Short name T476
Test name
Test status
Simulation time 13379896 ps
CPU time 0.58 seconds
Started Jul 12 05:44:23 PM PDT 24
Finished Jul 12 05:44:25 PM PDT 24
Peak memory 194656 kb
Host smart-91c6db5e-f85f-4e28-a7c2-1dd51704d3f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239328690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3239328690
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2273630592
Short name T174
Test name
Test status
Simulation time 18556715 ps
CPU time 0.63 seconds
Started Jul 12 05:44:23 PM PDT 24
Finished Jul 12 05:44:25 PM PDT 24
Peak memory 194560 kb
Host smart-8f285fff-3f71-441b-9548-13384ae3124a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273630592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2273630592
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.281299017
Short name T578
Test name
Test status
Simulation time 300748355 ps
CPU time 9.24 seconds
Started Jul 12 05:44:27 PM PDT 24
Finished Jul 12 05:44:38 PM PDT 24
Peak memory 196956 kb
Host smart-9f2c6f8b-97b7-42af-9fe7-580c3a0c3bea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281299017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.281299017
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3585601516
Short name T20
Test name
Test status
Simulation time 237859173 ps
CPU time 0.86 seconds
Started Jul 12 05:44:23 PM PDT 24
Finished Jul 12 05:44:26 PM PDT 24
Peak memory 197432 kb
Host smart-d3b9f628-5756-49cd-bfa8-0e580e7c8c77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585601516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3585601516
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.87216991
Short name T634
Test name
Test status
Simulation time 20001649 ps
CPU time 0.66 seconds
Started Jul 12 05:44:22 PM PDT 24
Finished Jul 12 05:44:24 PM PDT 24
Peak memory 194924 kb
Host smart-e85bc3ad-8c6a-4d23-a6b2-f42ad7be156e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87216991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.87216991
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3023464474
Short name T189
Test name
Test status
Simulation time 95641704 ps
CPU time 2.1 seconds
Started Jul 12 05:44:21 PM PDT 24
Finished Jul 12 05:44:24 PM PDT 24
Peak memory 198732 kb
Host smart-8a99e9ea-4d83-427c-9ba0-3539c8813f72
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023464474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3023464474
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3091417571
Short name T220
Test name
Test status
Simulation time 262533829 ps
CPU time 3.74 seconds
Started Jul 12 05:44:23 PM PDT 24
Finished Jul 12 05:44:28 PM PDT 24
Peak memory 198520 kb
Host smart-6d28ae40-e437-4fe0-a80f-91d5832df0e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091417571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3091417571
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2746828079
Short name T631
Test name
Test status
Simulation time 95947908 ps
CPU time 0.95 seconds
Started Jul 12 05:44:14 PM PDT 24
Finished Jul 12 05:44:17 PM PDT 24
Peak memory 196416 kb
Host smart-da80543d-fd1b-4cb9-b89c-1b0e950738ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746828079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2746828079
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.202105052
Short name T315
Test name
Test status
Simulation time 28223508 ps
CPU time 1.03 seconds
Started Jul 12 05:44:15 PM PDT 24
Finished Jul 12 05:44:17 PM PDT 24
Peak memory 196544 kb
Host smart-337f6eff-3a6e-41d7-a2bd-8d15d0ca727c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202105052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.202105052
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1243919129
Short name T3
Test name
Test status
Simulation time 713516239 ps
CPU time 4.48 seconds
Started Jul 12 05:44:23 PM PDT 24
Finished Jul 12 05:44:29 PM PDT 24
Peak memory 198596 kb
Host smart-4766c97d-6b5a-4a60-afd5-b3d2e0774bc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243919129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1243919129
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2111343962
Short name T702
Test name
Test status
Simulation time 158117084 ps
CPU time 1.22 seconds
Started Jul 12 05:44:16 PM PDT 24
Finished Jul 12 05:44:18 PM PDT 24
Peak memory 196416 kb
Host smart-30c87024-466e-4323-8e4b-b61c6500e2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111343962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2111343962
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1080969435
Short name T25
Test name
Test status
Simulation time 471777230 ps
CPU time 1.3 seconds
Started Jul 12 05:44:13 PM PDT 24
Finished Jul 12 05:44:15 PM PDT 24
Peak memory 198608 kb
Host smart-408696d7-6796-47e1-916f-1310ad127b9f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080969435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1080969435
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.131710500
Short name T410
Test name
Test status
Simulation time 21923470246 ps
CPU time 165.84 seconds
Started Jul 12 05:44:25 PM PDT 24
Finished Jul 12 05:47:12 PM PDT 24
Peak memory 198708 kb
Host smart-cf5c6a0d-01d3-40c3-809d-b751ff4675d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131710500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.g
pio_stress_all.131710500
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.3854522701
Short name T509
Test name
Test status
Simulation time 14326866082 ps
CPU time 492.37 seconds
Started Jul 12 05:44:21 PM PDT 24
Finished Jul 12 05:52:34 PM PDT 24
Peak memory 198904 kb
Host smart-374a2fbd-44c6-4ed1-9161-ec6d2567bc5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3854522701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.3854522701
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1968637593
Short name T400
Test name
Test status
Simulation time 89537410 ps
CPU time 0.59 seconds
Started Jul 12 05:44:29 PM PDT 24
Finished Jul 12 05:44:32 PM PDT 24
Peak memory 194652 kb
Host smart-d54ffc2a-b525-4185-b336-37a073c149bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968637593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1968637593
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3094465263
Short name T471
Test name
Test status
Simulation time 30585827 ps
CPU time 0.93 seconds
Started Jul 12 05:44:24 PM PDT 24
Finished Jul 12 05:44:27 PM PDT 24
Peak memory 196540 kb
Host smart-8a29b71d-bcf5-4065-8b98-de65c8dbcf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094465263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3094465263
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1351890848
Short name T413
Test name
Test status
Simulation time 1214051733 ps
CPU time 18.3 seconds
Started Jul 12 05:44:24 PM PDT 24
Finished Jul 12 05:44:44 PM PDT 24
Peak memory 196812 kb
Host smart-e91b149e-1335-4cc0-8b90-86751b334007
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351890848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1351890848
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3452050407
Short name T607
Test name
Test status
Simulation time 28400631 ps
CPU time 0.69 seconds
Started Jul 12 05:44:24 PM PDT 24
Finished Jul 12 05:44:27 PM PDT 24
Peak memory 195224 kb
Host smart-59befb9f-a8bd-45dc-938f-7e6ee41c5d0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452050407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3452050407
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.10782937
Short name T333
Test name
Test status
Simulation time 93696844 ps
CPU time 0.96 seconds
Started Jul 12 05:44:22 PM PDT 24
Finished Jul 12 05:44:25 PM PDT 24
Peak memory 197372 kb
Host smart-c2116638-9969-4523-bc4d-0734e381a2d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10782937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.10782937
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1161100887
Short name T667
Test name
Test status
Simulation time 45364197 ps
CPU time 1.92 seconds
Started Jul 12 05:44:23 PM PDT 24
Finished Jul 12 05:44:26 PM PDT 24
Peak memory 198680 kb
Host smart-a171e2e0-0c49-4b69-93b9-173ff22d6c98
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161100887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1161100887
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.2777451029
Short name T549
Test name
Test status
Simulation time 157069329 ps
CPU time 1.62 seconds
Started Jul 12 05:44:21 PM PDT 24
Finished Jul 12 05:44:24 PM PDT 24
Peak memory 196816 kb
Host smart-836b7e16-de4c-4f02-94a8-a63fdd41c52f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777451029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.2777451029
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.437856561
Short name T668
Test name
Test status
Simulation time 49207372 ps
CPU time 1.21 seconds
Started Jul 12 05:44:22 PM PDT 24
Finished Jul 12 05:44:25 PM PDT 24
Peak memory 197752 kb
Host smart-ddfc4bff-4583-416f-954a-e70a823d959f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437856561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.437856561
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.617068238
Short name T511
Test name
Test status
Simulation time 120743682 ps
CPU time 1.18 seconds
Started Jul 12 05:44:26 PM PDT 24
Finished Jul 12 05:44:28 PM PDT 24
Peak memory 197692 kb
Host smart-0c0ee76d-9494-44b5-a9e9-7cc46698d867
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617068238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.617068238
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3337646442
Short name T534
Test name
Test status
Simulation time 164958660 ps
CPU time 3.76 seconds
Started Jul 12 05:44:22 PM PDT 24
Finished Jul 12 05:44:28 PM PDT 24
Peak memory 198644 kb
Host smart-3609d6f1-a28d-48bd-8323-58a4e1bd6b3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337646442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3337646442
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.875851232
Short name T505
Test name
Test status
Simulation time 61077394 ps
CPU time 1.29 seconds
Started Jul 12 05:44:23 PM PDT 24
Finished Jul 12 05:44:26 PM PDT 24
Peak memory 196504 kb
Host smart-c29e6e16-7424-4f9e-8a52-7b6a10f3431f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875851232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.875851232
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2118109604
Short name T263
Test name
Test status
Simulation time 24935968 ps
CPU time 0.77 seconds
Started Jul 12 05:44:20 PM PDT 24
Finished Jul 12 05:44:22 PM PDT 24
Peak memory 196652 kb
Host smart-b05ecf2d-ea51-4a37-87cd-d4295bcd0e35
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118109604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2118109604
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3104785999
Short name T424
Test name
Test status
Simulation time 11087026776 ps
CPU time 37.35 seconds
Started Jul 12 05:44:23 PM PDT 24
Finished Jul 12 05:45:02 PM PDT 24
Peak memory 198828 kb
Host smart-7154fbb9-2692-4ec8-b035-bbe3c875af11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104785999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3104785999
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3304572662
Short name T63
Test name
Test status
Simulation time 85624021576 ps
CPU time 681.63 seconds
Started Jul 12 05:44:22 PM PDT 24
Finished Jul 12 05:55:45 PM PDT 24
Peak memory 198776 kb
Host smart-cb552dba-b453-4bcc-bea4-bb3af7084217
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3304572662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.3304572662
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2112959208
Short name T375
Test name
Test status
Simulation time 44627537 ps
CPU time 0.57 seconds
Started Jul 12 05:44:26 PM PDT 24
Finished Jul 12 05:44:28 PM PDT 24
Peak memory 195344 kb
Host smart-b3adfdf7-2087-4a4f-ab6f-2bdbe8e13a06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112959208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2112959208
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.56568106
Short name T203
Test name
Test status
Simulation time 29889394 ps
CPU time 0.67 seconds
Started Jul 12 05:44:26 PM PDT 24
Finished Jul 12 05:44:27 PM PDT 24
Peak memory 194624 kb
Host smart-596a9da9-243b-408c-acce-3f5d82ce158e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56568106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.56568106
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.735629649
Short name T384
Test name
Test status
Simulation time 370093581 ps
CPU time 18.73 seconds
Started Jul 12 05:44:25 PM PDT 24
Finished Jul 12 05:44:45 PM PDT 24
Peak memory 197168 kb
Host smart-d115c5c0-cc7d-445b-b325-59d0c9d9dc6e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735629649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.735629649
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.999536842
Short name T371
Test name
Test status
Simulation time 70270381 ps
CPU time 1.01 seconds
Started Jul 12 05:44:23 PM PDT 24
Finished Jul 12 05:44:26 PM PDT 24
Peak memory 197788 kb
Host smart-c943b81d-6517-4391-bb43-904e8d0c4533
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999536842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.999536842
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.18118597
Short name T508
Test name
Test status
Simulation time 135841276 ps
CPU time 1.09 seconds
Started Jul 12 05:44:28 PM PDT 24
Finished Jul 12 05:44:32 PM PDT 24
Peak memory 196448 kb
Host smart-76988c46-b30f-45a4-9375-02d8a33b0a7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18118597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.18118597
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2705714438
Short name T212
Test name
Test status
Simulation time 152974271 ps
CPU time 1.19 seconds
Started Jul 12 05:44:26 PM PDT 24
Finished Jul 12 05:44:29 PM PDT 24
Peak memory 197672 kb
Host smart-b7427a47-4a28-4d0c-b3d8-ed11df337d83
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705714438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2705714438
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3471896375
Short name T635
Test name
Test status
Simulation time 337033836 ps
CPU time 1.71 seconds
Started Jul 12 05:44:27 PM PDT 24
Finished Jul 12 05:44:31 PM PDT 24
Peak memory 196680 kb
Host smart-1df1acef-bddb-46ee-b4e8-85d8541018c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471896375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3471896375
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.446085496
Short name T591
Test name
Test status
Simulation time 23909200 ps
CPU time 0.86 seconds
Started Jul 12 05:44:29 PM PDT 24
Finished Jul 12 05:44:32 PM PDT 24
Peak memory 196676 kb
Host smart-6e84a4cf-eed5-4061-a9c6-a4b571518be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446085496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.446085496
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.906445235
Short name T525
Test name
Test status
Simulation time 25852178 ps
CPU time 0.82 seconds
Started Jul 12 05:44:27 PM PDT 24
Finished Jul 12 05:44:31 PM PDT 24
Peak memory 195940 kb
Host smart-7a109083-d94b-47ed-8254-16b457540dc7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906445235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.906445235
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2727053967
Short name T467
Test name
Test status
Simulation time 52904085 ps
CPU time 2.47 seconds
Started Jul 12 05:44:25 PM PDT 24
Finished Jul 12 05:44:28 PM PDT 24
Peak memory 198620 kb
Host smart-c8ae19e4-656e-4c24-b9d9-d2af5842e475
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727053967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2727053967
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3024935707
Short name T191
Test name
Test status
Simulation time 200337988 ps
CPU time 1.22 seconds
Started Jul 12 05:44:27 PM PDT 24
Finished Jul 12 05:44:30 PM PDT 24
Peak memory 197364 kb
Host smart-d9e8f8f0-8761-43e5-ae23-7da3f20ef2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024935707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3024935707
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.4263624977
Short name T581
Test name
Test status
Simulation time 129657736 ps
CPU time 0.8 seconds
Started Jul 12 05:44:27 PM PDT 24
Finished Jul 12 05:44:30 PM PDT 24
Peak memory 195828 kb
Host smart-3121b2b1-aa2d-4233-a57e-5b643d49e299
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263624977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.4263624977
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1854976083
Short name T310
Test name
Test status
Simulation time 23414707501 ps
CPU time 94.78 seconds
Started Jul 12 05:44:25 PM PDT 24
Finished Jul 12 05:46:01 PM PDT 24
Peak memory 198752 kb
Host smart-4dfb00b0-aef8-4fea-b52e-fd334698f9ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854976083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1854976083
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.4017840731
Short name T201
Test name
Test status
Simulation time 28899783 ps
CPU time 0.58 seconds
Started Jul 12 05:44:30 PM PDT 24
Finished Jul 12 05:44:33 PM PDT 24
Peak memory 195332 kb
Host smart-926122ec-8f19-41dd-8e13-42d234e02629
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017840731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.4017840731
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1858786688
Short name T377
Test name
Test status
Simulation time 41033593 ps
CPU time 0.9 seconds
Started Jul 12 05:44:29 PM PDT 24
Finished Jul 12 05:44:32 PM PDT 24
Peak memory 196496 kb
Host smart-68164452-637d-4e81-a270-d5aa612c9d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858786688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1858786688
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2784838319
Short name T126
Test name
Test status
Simulation time 361383374 ps
CPU time 8.23 seconds
Started Jul 12 05:44:28 PM PDT 24
Finished Jul 12 05:44:39 PM PDT 24
Peak memory 197380 kb
Host smart-df23b881-52fe-4d22-af7e-ca34aa527be6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784838319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2784838319
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1049337139
Short name T713
Test name
Test status
Simulation time 89027885 ps
CPU time 0.63 seconds
Started Jul 12 05:44:27 PM PDT 24
Finished Jul 12 05:44:29 PM PDT 24
Peak memory 195032 kb
Host smart-2313d18b-00da-4c87-95e2-4fe45d6e6e98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049337139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1049337139
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3741453621
Short name T380
Test name
Test status
Simulation time 204538964 ps
CPU time 0.88 seconds
Started Jul 12 05:44:26 PM PDT 24
Finished Jul 12 05:44:28 PM PDT 24
Peak memory 197260 kb
Host smart-a39e8e7a-e345-452e-9dd5-b5149a67656e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741453621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3741453621
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.4190182973
Short name T640
Test name
Test status
Simulation time 31018936 ps
CPU time 1.24 seconds
Started Jul 12 05:44:32 PM PDT 24
Finished Jul 12 05:44:35 PM PDT 24
Peak memory 197916 kb
Host smart-8c54a158-1f7f-4ac2-bc48-57007a5b0cc4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190182973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.4190182973
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2477130071
Short name T597
Test name
Test status
Simulation time 475868246 ps
CPU time 1.98 seconds
Started Jul 12 05:44:33 PM PDT 24
Finished Jul 12 05:44:36 PM PDT 24
Peak memory 197848 kb
Host smart-57d8ae13-0362-4da4-bd70-12df1e1da4f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477130071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2477130071
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2488563524
Short name T266
Test name
Test status
Simulation time 41148601 ps
CPU time 0.84 seconds
Started Jul 12 05:44:35 PM PDT 24
Finished Jul 12 05:44:38 PM PDT 24
Peak memory 196652 kb
Host smart-336dbf1e-0f57-4796-a640-e535a1a5e280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488563524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2488563524
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3543089908
Short name T153
Test name
Test status
Simulation time 221779945 ps
CPU time 1.22 seconds
Started Jul 12 05:44:31 PM PDT 24
Finished Jul 12 05:44:35 PM PDT 24
Peak memory 197964 kb
Host smart-5f87fa1a-8e13-46c5-9acd-fa0701d45f47
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543089908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3543089908
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3923808960
Short name T312
Test name
Test status
Simulation time 493255245 ps
CPU time 3.37 seconds
Started Jul 12 05:44:32 PM PDT 24
Finished Jul 12 05:44:37 PM PDT 24
Peak memory 198748 kb
Host smart-bfb92d2f-1d05-4aa9-8ff7-039346a10274
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923808960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3923808960
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1972008447
Short name T187
Test name
Test status
Simulation time 167529877 ps
CPU time 1.5 seconds
Started Jul 12 05:44:25 PM PDT 24
Finished Jul 12 05:44:28 PM PDT 24
Peak memory 198504 kb
Host smart-98a2e439-44bd-4d63-81b8-d68673e0ea89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972008447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1972008447
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2903027014
Short name T232
Test name
Test status
Simulation time 164015677 ps
CPU time 1.1 seconds
Started Jul 12 05:44:26 PM PDT 24
Finished Jul 12 05:44:29 PM PDT 24
Peak memory 196128 kb
Host smart-27080f26-335d-47d7-9ca3-45024d77df24
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903027014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2903027014
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.852490470
Short name T176
Test name
Test status
Simulation time 9613147361 ps
CPU time 36.82 seconds
Started Jul 12 05:44:28 PM PDT 24
Finished Jul 12 05:45:07 PM PDT 24
Peak memory 198812 kb
Host smart-879eea5c-e79a-4293-ac1c-87aa2a7e8fbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852490470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.852490470
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3283662294
Short name T206
Test name
Test status
Simulation time 15301070 ps
CPU time 0.59 seconds
Started Jul 12 05:44:29 PM PDT 24
Finished Jul 12 05:44:32 PM PDT 24
Peak memory 195364 kb
Host smart-4dd7249a-9a85-4e7a-9f07-66ef6a3a87b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283662294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3283662294
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.329154430
Short name T257
Test name
Test status
Simulation time 49407077 ps
CPU time 0.94 seconds
Started Jul 12 05:44:27 PM PDT 24
Finished Jul 12 05:44:29 PM PDT 24
Peak memory 197164 kb
Host smart-e353f3d8-6622-41a2-8c5c-4c3d3932e7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329154430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.329154430
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1411775605
Short name T356
Test name
Test status
Simulation time 609287756 ps
CPU time 7.01 seconds
Started Jul 12 05:44:29 PM PDT 24
Finished Jul 12 05:44:38 PM PDT 24
Peak memory 196964 kb
Host smart-2bd317af-f490-44a1-bead-1eae7c3b4d2e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411775605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1411775605
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1423812755
Short name T590
Test name
Test status
Simulation time 60105245 ps
CPU time 0.94 seconds
Started Jul 12 05:44:34 PM PDT 24
Finished Jul 12 05:44:36 PM PDT 24
Peak memory 198532 kb
Host smart-99dbad11-5d0c-4601-844b-dc0da3728f1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423812755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1423812755
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3681477662
Short name T603
Test name
Test status
Simulation time 125622158 ps
CPU time 1 seconds
Started Jul 12 05:44:32 PM PDT 24
Finished Jul 12 05:44:35 PM PDT 24
Peak memory 196872 kb
Host smart-b0d0629d-de63-49b3-91df-eed1bd61e5e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681477662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3681477662
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2062002193
Short name T177
Test name
Test status
Simulation time 363816120 ps
CPU time 2.1 seconds
Started Jul 12 05:44:33 PM PDT 24
Finished Jul 12 05:44:37 PM PDT 24
Peak memory 198696 kb
Host smart-35741c20-28c6-460c-9443-b81cfb869b27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062002193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2062002193
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3819216892
Short name T537
Test name
Test status
Simulation time 77726480 ps
CPU time 0.69 seconds
Started Jul 12 05:44:28 PM PDT 24
Finished Jul 12 05:44:31 PM PDT 24
Peak memory 194820 kb
Host smart-247da80d-4082-4c34-89a8-19902da749f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819216892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3819216892
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3658357280
Short name T691
Test name
Test status
Simulation time 118026010 ps
CPU time 0.72 seconds
Started Jul 12 05:44:33 PM PDT 24
Finished Jul 12 05:44:35 PM PDT 24
Peak memory 196748 kb
Host smart-8197f444-6d75-4df1-9d1a-a6e896aed5f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658357280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3658357280
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3654447086
Short name T10
Test name
Test status
Simulation time 1804501353 ps
CPU time 6.44 seconds
Started Jul 12 05:45:01 PM PDT 24
Finished Jul 12 05:45:10 PM PDT 24
Peak memory 198620 kb
Host smart-9fccaca5-5fd5-4852-8dfc-4ccc175e581b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654447086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.3654447086
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.4022054949
Short name T200
Test name
Test status
Simulation time 274525298 ps
CPU time 1.04 seconds
Started Jul 12 05:44:29 PM PDT 24
Finished Jul 12 05:44:32 PM PDT 24
Peak memory 196476 kb
Host smart-99073a95-2444-46ee-879d-15cb25f932e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022054949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.4022054949
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2002267120
Short name T690
Test name
Test status
Simulation time 35956087 ps
CPU time 0.89 seconds
Started Jul 12 05:44:29 PM PDT 24
Finished Jul 12 05:44:33 PM PDT 24
Peak memory 196800 kb
Host smart-1dda52cb-9c59-43cb-9a42-0e9673db8fbc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002267120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2002267120
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.566438207
Short name T584
Test name
Test status
Simulation time 23577353740 ps
CPU time 143.17 seconds
Started Jul 12 05:44:31 PM PDT 24
Finished Jul 12 05:46:56 PM PDT 24
Peak memory 198768 kb
Host smart-99c94691-a695-4ded-93a5-27b7935e1a9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566438207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.g
pio_stress_all.566438207
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2371429177
Short name T236
Test name
Test status
Simulation time 12225201 ps
CPU time 0.56 seconds
Started Jul 12 05:44:38 PM PDT 24
Finished Jul 12 05:44:39 PM PDT 24
Peak memory 194636 kb
Host smart-f0c997ff-2f64-4606-888b-b13968cbdd66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371429177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2371429177
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3927688396
Short name T367
Test name
Test status
Simulation time 21455796 ps
CPU time 0.71 seconds
Started Jul 12 05:44:30 PM PDT 24
Finished Jul 12 05:44:33 PM PDT 24
Peak memory 196628 kb
Host smart-a3aa5631-83d5-44c0-9004-26357ec52542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927688396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3927688396
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.4153130340
Short name T420
Test name
Test status
Simulation time 1627384472 ps
CPU time 20.21 seconds
Started Jul 12 05:44:31 PM PDT 24
Finished Jul 12 05:44:53 PM PDT 24
Peak memory 196200 kb
Host smart-56d7d9ca-d72a-4faa-bab1-94d7ebf86170
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153130340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.4153130340
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.534162113
Short name T512
Test name
Test status
Simulation time 471774339 ps
CPU time 1.07 seconds
Started Jul 12 05:44:37 PM PDT 24
Finished Jul 12 05:44:39 PM PDT 24
Peak memory 198908 kb
Host smart-c0741701-6883-4c2d-87c0-ab15fab6889f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534162113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.534162113
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1338900972
Short name T290
Test name
Test status
Simulation time 61113734 ps
CPU time 1.02 seconds
Started Jul 12 05:44:32 PM PDT 24
Finished Jul 12 05:44:35 PM PDT 24
Peak memory 197024 kb
Host smart-965a98f1-ba0f-418a-96da-f86418f623fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338900972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1338900972
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.4259949269
Short name T629
Test name
Test status
Simulation time 108072705 ps
CPU time 2.33 seconds
Started Jul 12 05:44:30 PM PDT 24
Finished Jul 12 05:44:34 PM PDT 24
Peak memory 198700 kb
Host smart-f8b6651a-747f-4730-bd51-8af9cbba3596
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259949269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.4259949269
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.355670178
Short name T462
Test name
Test status
Simulation time 266294830 ps
CPU time 2.66 seconds
Started Jul 12 05:44:30 PM PDT 24
Finished Jul 12 05:44:34 PM PDT 24
Peak memory 197792 kb
Host smart-209e95f8-f631-4cc7-8a12-b7e036cef21d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355670178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
355670178
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.501732059
Short name T171
Test name
Test status
Simulation time 76911349 ps
CPU time 1.01 seconds
Started Jul 12 05:44:28 PM PDT 24
Finished Jul 12 05:44:31 PM PDT 24
Peak memory 197072 kb
Host smart-8e062649-fdd2-4a73-b2b9-b5538463b79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501732059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.501732059
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1175533784
Short name T558
Test name
Test status
Simulation time 185471260 ps
CPU time 1.11 seconds
Started Jul 12 05:44:29 PM PDT 24
Finished Jul 12 05:44:32 PM PDT 24
Peak memory 197528 kb
Host smart-3fd90bb8-766f-46b6-8403-e590c911c261
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175533784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1175533784
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3464691368
Short name T697
Test name
Test status
Simulation time 543256318 ps
CPU time 2.06 seconds
Started Jul 12 05:44:35 PM PDT 24
Finished Jul 12 05:44:39 PM PDT 24
Peak memory 198564 kb
Host smart-968686a8-7832-40cb-a63b-7890ab7510d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464691368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3464691368
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2895510429
Short name T524
Test name
Test status
Simulation time 53662298 ps
CPU time 1.2 seconds
Started Jul 12 05:44:32 PM PDT 24
Finished Jul 12 05:44:35 PM PDT 24
Peak memory 196332 kb
Host smart-3bc063c9-e271-443b-bb4f-6915dc2a11b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895510429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2895510429
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.782828102
Short name T453
Test name
Test status
Simulation time 194334556 ps
CPU time 1.31 seconds
Started Jul 12 05:44:32 PM PDT 24
Finished Jul 12 05:44:35 PM PDT 24
Peak memory 197204 kb
Host smart-3fec7ba4-da3d-455d-a1cb-ed9861e4c082
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782828102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.782828102
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2731741612
Short name T278
Test name
Test status
Simulation time 2117642945 ps
CPU time 52.32 seconds
Started Jul 12 05:44:40 PM PDT 24
Finished Jul 12 05:45:33 PM PDT 24
Peak memory 198816 kb
Host smart-0d819b61-959c-4ea9-b55f-7174c13a9210
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731741612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2731741612
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.375991442
Short name T33
Test name
Test status
Simulation time 150031105122 ps
CPU time 736.31 seconds
Started Jul 12 05:44:34 PM PDT 24
Finished Jul 12 05:56:52 PM PDT 24
Peak memory 198736 kb
Host smart-367c02c9-0ec9-4083-a2e0-f1146bd5fe52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=375991442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.375991442
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3568583730
Short name T172
Test name
Test status
Simulation time 14117594 ps
CPU time 0.59 seconds
Started Jul 12 05:44:33 PM PDT 24
Finished Jul 12 05:44:35 PM PDT 24
Peak memory 194856 kb
Host smart-dc31d678-ec4f-4a75-b1e3-d8f95e5286df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568583730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3568583730
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1771481530
Short name T653
Test name
Test status
Simulation time 86075720 ps
CPU time 0.6 seconds
Started Jul 12 05:44:37 PM PDT 24
Finished Jul 12 05:44:38 PM PDT 24
Peak memory 194416 kb
Host smart-3c656a12-34a4-4165-b0b8-6b3b2cbbd3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771481530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1771481530
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.756662679
Short name T623
Test name
Test status
Simulation time 827315994 ps
CPU time 10.5 seconds
Started Jul 12 05:44:34 PM PDT 24
Finished Jul 12 05:44:46 PM PDT 24
Peak memory 197496 kb
Host smart-ec5ba8a9-f9e4-4ef7-b188-782db4923d3f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756662679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.756662679
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1487898209
Short name T77
Test name
Test status
Simulation time 48702022 ps
CPU time 0.73 seconds
Started Jul 12 05:44:36 PM PDT 24
Finished Jul 12 05:44:38 PM PDT 24
Peak memory 195384 kb
Host smart-1d67f1eb-b1c9-41ed-bb46-dd4da25d47a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487898209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1487898209
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2986569171
Short name T146
Test name
Test status
Simulation time 116279218 ps
CPU time 0.95 seconds
Started Jul 12 05:44:33 PM PDT 24
Finished Jul 12 05:44:35 PM PDT 24
Peak memory 196436 kb
Host smart-375ee83a-e202-4f78-83b6-6c634344334d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986569171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2986569171
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2094921496
Short name T427
Test name
Test status
Simulation time 343187713 ps
CPU time 3.76 seconds
Started Jul 12 05:44:38 PM PDT 24
Finished Jul 12 05:44:43 PM PDT 24
Peak memory 198640 kb
Host smart-67b3c67c-8b36-4149-b3c3-9d47fa984d71
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094921496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2094921496
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3393035722
Short name T210
Test name
Test status
Simulation time 134305024 ps
CPU time 2.1 seconds
Started Jul 12 05:44:35 PM PDT 24
Finished Jul 12 05:44:39 PM PDT 24
Peak memory 197764 kb
Host smart-588d263d-cd82-4422-972e-091a91e61d81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393035722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3393035722
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2382189125
Short name T273
Test name
Test status
Simulation time 96391100 ps
CPU time 1.03 seconds
Started Jul 12 05:44:36 PM PDT 24
Finished Jul 12 05:44:39 PM PDT 24
Peak memory 196492 kb
Host smart-01d6ecc6-21a5-446d-a86e-ae0384d21d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382189125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2382189125
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1359645903
Short name T442
Test name
Test status
Simulation time 54811167 ps
CPU time 1.12 seconds
Started Jul 12 05:44:34 PM PDT 24
Finished Jul 12 05:44:37 PM PDT 24
Peak memory 197276 kb
Host smart-6f3ba392-7732-4d7f-85d0-a430fc421182
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359645903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1359645903
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2662481157
Short name T708
Test name
Test status
Simulation time 92985399 ps
CPU time 3.97 seconds
Started Jul 12 05:44:38 PM PDT 24
Finished Jul 12 05:44:43 PM PDT 24
Peak memory 198560 kb
Host smart-e94bda22-8c57-4fbe-b3bb-83966b82a7b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662481157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2662481157
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1776682842
Short name T115
Test name
Test status
Simulation time 144104159 ps
CPU time 1.45 seconds
Started Jul 12 05:44:38 PM PDT 24
Finished Jul 12 05:44:40 PM PDT 24
Peak memory 196868 kb
Host smart-5aa5a3f9-ee0e-450f-9455-847ea97af30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776682842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1776682842
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3806440013
Short name T614
Test name
Test status
Simulation time 479312248 ps
CPU time 1.17 seconds
Started Jul 12 05:44:35 PM PDT 24
Finished Jul 12 05:44:38 PM PDT 24
Peak memory 197172 kb
Host smart-cece11cc-a19c-4f19-b11e-dcbc26416631
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806440013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3806440013
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2229898898
Short name T664
Test name
Test status
Simulation time 15366276161 ps
CPU time 184.73 seconds
Started Jul 12 05:44:42 PM PDT 24
Finished Jul 12 05:47:48 PM PDT 24
Peak memory 198692 kb
Host smart-12fef095-ed0c-4e5e-b332-28dee8f4b40a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229898898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2229898898
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.539690980
Short name T677
Test name
Test status
Simulation time 1315668919948 ps
CPU time 1936.23 seconds
Started Jul 12 05:44:37 PM PDT 24
Finished Jul 12 06:16:55 PM PDT 24
Peak memory 207132 kb
Host smart-04768a71-6812-46f9-8401-c4cffe32bee0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=539690980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.539690980
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3569454169
Short name T346
Test name
Test status
Simulation time 13443531 ps
CPU time 0.57 seconds
Started Jul 12 05:43:24 PM PDT 24
Finished Jul 12 05:43:26 PM PDT 24
Peak memory 195336 kb
Host smart-e0e4bc5b-d984-4383-b71c-84ff54f04a9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569454169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3569454169
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1272350840
Short name T425
Test name
Test status
Simulation time 15834485 ps
CPU time 0.64 seconds
Started Jul 12 05:43:19 PM PDT 24
Finished Jul 12 05:43:21 PM PDT 24
Peak memory 194752 kb
Host smart-5ff52299-46da-4b21-849a-f781391a85c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272350840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1272350840
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.2480492083
Short name T585
Test name
Test status
Simulation time 329043768 ps
CPU time 11.68 seconds
Started Jul 12 05:43:17 PM PDT 24
Finished Jul 12 05:43:30 PM PDT 24
Peak memory 196104 kb
Host smart-048ac41d-2cf0-40d9-820f-290d5a76c58b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480492083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.2480492083
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2145967895
Short name T610
Test name
Test status
Simulation time 53519922 ps
CPU time 0.92 seconds
Started Jul 12 05:43:18 PM PDT 24
Finished Jul 12 05:43:21 PM PDT 24
Peak memory 198472 kb
Host smart-d7941613-7b9a-4f38-b206-a2b627b92e3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145967895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2145967895
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3345906038
Short name T693
Test name
Test status
Simulation time 18198349 ps
CPU time 0.68 seconds
Started Jul 12 05:43:22 PM PDT 24
Finished Jul 12 05:43:24 PM PDT 24
Peak memory 194764 kb
Host smart-e2539506-f723-4d3c-9dce-d439e1a0faf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345906038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3345906038
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.166655877
Short name T429
Test name
Test status
Simulation time 303020564 ps
CPU time 3.39 seconds
Started Jul 12 05:43:21 PM PDT 24
Finished Jul 12 05:43:26 PM PDT 24
Peak memory 198648 kb
Host smart-99c42c85-1232-471f-b733-3f893bc78b5c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166655877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.166655877
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1744680995
Short name T357
Test name
Test status
Simulation time 339266598 ps
CPU time 2.54 seconds
Started Jul 12 05:43:22 PM PDT 24
Finished Jul 12 05:43:26 PM PDT 24
Peak memory 197948 kb
Host smart-cece02f5-5201-4165-9c24-924fb7dc9b38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744680995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1744680995
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2721600972
Short name T602
Test name
Test status
Simulation time 275073997 ps
CPU time 0.86 seconds
Started Jul 12 05:43:17 PM PDT 24
Finished Jul 12 05:43:18 PM PDT 24
Peak memory 196520 kb
Host smart-366ebfa6-e929-4599-8547-4372cd43e19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721600972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2721600972
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.4130860427
Short name T30
Test name
Test status
Simulation time 85533414 ps
CPU time 1.06 seconds
Started Jul 12 05:43:22 PM PDT 24
Finished Jul 12 05:43:24 PM PDT 24
Peak memory 196640 kb
Host smart-fa606ae9-7de3-4716-b70d-59d787839561
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130860427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.4130860427
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3616307360
Short name T446
Test name
Test status
Simulation time 445879590 ps
CPU time 5.18 seconds
Started Jul 12 05:43:17 PM PDT 24
Finished Jul 12 05:43:23 PM PDT 24
Peak memory 198616 kb
Host smart-6f6af474-a01c-4951-bb17-a9b23bc54228
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616307360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3616307360
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.338942527
Short name T50
Test name
Test status
Simulation time 201581556 ps
CPU time 0.83 seconds
Started Jul 12 05:43:19 PM PDT 24
Finished Jul 12 05:43:21 PM PDT 24
Peak memory 214228 kb
Host smart-2299fbe0-05c7-49c9-b6e4-50f301ddc5a7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338942527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.338942527
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.684719418
Short name T593
Test name
Test status
Simulation time 224058334 ps
CPU time 1.26 seconds
Started Jul 12 05:43:20 PM PDT 24
Finished Jul 12 05:43:22 PM PDT 24
Peak memory 197500 kb
Host smart-db874f1b-d043-4434-8980-f0f7b324fdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684719418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.684719418
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1585042293
Short name T373
Test name
Test status
Simulation time 49888428 ps
CPU time 1.1 seconds
Started Jul 12 05:43:17 PM PDT 24
Finished Jul 12 05:43:19 PM PDT 24
Peak memory 196376 kb
Host smart-50a4dc80-a1b1-4175-b1b2-b352296439be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585042293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1585042293
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.4248784425
Short name T158
Test name
Test status
Simulation time 11916638819 ps
CPU time 142.81 seconds
Started Jul 12 05:43:17 PM PDT 24
Finished Jul 12 05:45:40 PM PDT 24
Peak memory 198788 kb
Host smart-df8b3258-d745-4458-bc8d-980621a101f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248784425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.4248784425
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2450288797
Short name T598
Test name
Test status
Simulation time 23297865 ps
CPU time 0.57 seconds
Started Jul 12 05:44:40 PM PDT 24
Finished Jul 12 05:44:42 PM PDT 24
Peak memory 195244 kb
Host smart-b5474c73-8491-4ab5-b369-2aadd89149ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450288797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2450288797
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1620755118
Short name T326
Test name
Test status
Simulation time 22248768 ps
CPU time 0.76 seconds
Started Jul 12 05:44:38 PM PDT 24
Finished Jul 12 05:44:40 PM PDT 24
Peak memory 195892 kb
Host smart-69b48fa0-abbb-4ae4-93e5-af7e3ba6caf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620755118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1620755118
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2951660075
Short name T666
Test name
Test status
Simulation time 365838079 ps
CPU time 13.09 seconds
Started Jul 12 05:44:38 PM PDT 24
Finished Jul 12 05:44:53 PM PDT 24
Peak memory 197692 kb
Host smart-0046e89c-f91d-4442-b855-5ee9e02878a4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951660075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2951660075
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2745652864
Short name T14
Test name
Test status
Simulation time 114121520 ps
CPU time 0.69 seconds
Started Jul 12 05:44:38 PM PDT 24
Finished Jul 12 05:44:40 PM PDT 24
Peak memory 196040 kb
Host smart-58381844-b109-4155-a7bd-1949e807e60b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745652864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2745652864
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2185255493
Short name T300
Test name
Test status
Simulation time 52597384 ps
CPU time 0.86 seconds
Started Jul 12 05:44:37 PM PDT 24
Finished Jul 12 05:44:39 PM PDT 24
Peak memory 196972 kb
Host smart-79142563-2f46-4ef0-9aa0-62318ad793db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185255493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2185255493
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2249838318
Short name T135
Test name
Test status
Simulation time 59379786 ps
CPU time 2.22 seconds
Started Jul 12 05:44:41 PM PDT 24
Finished Jul 12 05:44:45 PM PDT 24
Peak memory 198712 kb
Host smart-06b8d28c-037e-4258-adfb-dc0b1b1179a0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249838318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2249838318
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2447082818
Short name T217
Test name
Test status
Simulation time 124478364 ps
CPU time 3.53 seconds
Started Jul 12 05:44:38 PM PDT 24
Finished Jul 12 05:44:43 PM PDT 24
Peak memory 198740 kb
Host smart-3029d4a8-1de7-477f-9d53-e8e7f443e9dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447082818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2447082818
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1917674698
Short name T216
Test name
Test status
Simulation time 59212199 ps
CPU time 1.31 seconds
Started Jul 12 05:44:41 PM PDT 24
Finished Jul 12 05:44:44 PM PDT 24
Peak memory 198632 kb
Host smart-5ecbdc68-6f0a-40c7-b4f4-35fed4b648cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917674698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1917674698
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2258852280
Short name T560
Test name
Test status
Simulation time 63604917 ps
CPU time 0.8 seconds
Started Jul 12 05:44:41 PM PDT 24
Finished Jul 12 05:44:43 PM PDT 24
Peak memory 195996 kb
Host smart-778e0825-27a6-4bc5-a584-5624f6319cdb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258852280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2258852280
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2913388336
Short name T164
Test name
Test status
Simulation time 1768234883 ps
CPU time 4.69 seconds
Started Jul 12 05:44:42 PM PDT 24
Finished Jul 12 05:44:48 PM PDT 24
Peak memory 198620 kb
Host smart-cddeffd8-fd77-4959-ad76-5b98fcd5f41d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913388336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2913388336
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.521270331
Short name T183
Test name
Test status
Simulation time 82693274 ps
CPU time 1.3 seconds
Started Jul 12 05:44:36 PM PDT 24
Finished Jul 12 05:44:39 PM PDT 24
Peak memory 197448 kb
Host smart-75df2eb3-5239-4d5f-83da-2eaa5f355954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521270331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.521270331
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3897382084
Short name T332
Test name
Test status
Simulation time 72529911 ps
CPU time 0.98 seconds
Started Jul 12 05:44:41 PM PDT 24
Finished Jul 12 05:44:43 PM PDT 24
Peak memory 196828 kb
Host smart-fd2dcd57-1bb1-4369-9bc3-6e481fd649a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897382084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3897382084
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.82865010
Short name T650
Test name
Test status
Simulation time 4447938708 ps
CPU time 24.86 seconds
Started Jul 12 05:44:42 PM PDT 24
Finished Jul 12 05:45:09 PM PDT 24
Peak memory 198700 kb
Host smart-868f7b9a-08a2-471b-8ff1-1688eeb7eb8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82865010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gp
io_stress_all.82865010
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3154857977
Short name T493
Test name
Test status
Simulation time 11263786 ps
CPU time 0.6 seconds
Started Jul 12 05:44:42 PM PDT 24
Finished Jul 12 05:44:44 PM PDT 24
Peak memory 194872 kb
Host smart-5dd1627c-5e31-4ab7-9746-270b133f58a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154857977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3154857977
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.681814980
Short name T409
Test name
Test status
Simulation time 52406142 ps
CPU time 0.91 seconds
Started Jul 12 05:44:40 PM PDT 24
Finished Jul 12 05:44:42 PM PDT 24
Peak memory 197300 kb
Host smart-47729d96-da3f-4872-a89f-2930af397338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681814980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.681814980
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1974630585
Short name T682
Test name
Test status
Simulation time 6144154527 ps
CPU time 28.56 seconds
Started Jul 12 05:44:42 PM PDT 24
Finished Jul 12 05:45:12 PM PDT 24
Peak memory 197600 kb
Host smart-68ad2e42-0140-44b0-86ea-67947cfa967f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974630585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1974630585
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3793275607
Short name T231
Test name
Test status
Simulation time 185599960 ps
CPU time 0.77 seconds
Started Jul 12 05:44:41 PM PDT 24
Finished Jul 12 05:44:43 PM PDT 24
Peak memory 196444 kb
Host smart-dbf42119-f73a-40d1-bb0f-fdec8b33c88f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793275607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3793275607
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3095076610
Short name T481
Test name
Test status
Simulation time 928462918 ps
CPU time 1.37 seconds
Started Jul 12 05:44:40 PM PDT 24
Finished Jul 12 05:44:43 PM PDT 24
Peak memory 197824 kb
Host smart-b4e8dcdb-26f6-4d6a-8fd3-06c3ef82ab1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095076610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3095076610
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.4267191192
Short name T148
Test name
Test status
Simulation time 509797410 ps
CPU time 3.46 seconds
Started Jul 12 05:44:41 PM PDT 24
Finished Jul 12 05:44:46 PM PDT 24
Peak memory 197128 kb
Host smart-6e3b6687-8e16-4e87-a803-7f75e83d4211
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267191192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.4267191192
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2139184162
Short name T484
Test name
Test status
Simulation time 82652507 ps
CPU time 1.14 seconds
Started Jul 12 05:44:40 PM PDT 24
Finished Jul 12 05:44:42 PM PDT 24
Peak memory 196836 kb
Host smart-0493a158-749f-433e-9be3-9d3cbb323dd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139184162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2139184162
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1301313564
Short name T70
Test name
Test status
Simulation time 34523358 ps
CPU time 1.05 seconds
Started Jul 12 05:44:39 PM PDT 24
Finished Jul 12 05:44:42 PM PDT 24
Peak memory 196480 kb
Host smart-ca59fdf8-bb46-48a5-8cd3-f5e401c89408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301313564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1301313564
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2622596583
Short name T564
Test name
Test status
Simulation time 56349949 ps
CPU time 1.04 seconds
Started Jul 12 05:44:39 PM PDT 24
Finished Jul 12 05:44:42 PM PDT 24
Peak memory 196488 kb
Host smart-855a4158-475e-4fb8-b281-2fd6a4fc2c77
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622596583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2622596583
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1830653567
Short name T674
Test name
Test status
Simulation time 451087748 ps
CPU time 5.22 seconds
Started Jul 12 05:44:40 PM PDT 24
Finished Jul 12 05:44:46 PM PDT 24
Peak memory 198640 kb
Host smart-43247b9f-d1af-4c5b-80a2-73006f4211e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830653567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1830653567
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.179632177
Short name T168
Test name
Test status
Simulation time 79543429 ps
CPU time 1.04 seconds
Started Jul 12 05:44:38 PM PDT 24
Finished Jul 12 05:44:41 PM PDT 24
Peak memory 196484 kb
Host smart-8ac589bb-6aee-465d-940f-92507e075722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179632177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.179632177
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3597529003
Short name T422
Test name
Test status
Simulation time 180709398 ps
CPU time 0.87 seconds
Started Jul 12 05:44:39 PM PDT 24
Finished Jul 12 05:44:41 PM PDT 24
Peak memory 197120 kb
Host smart-c430607e-f1ae-4a5e-9b03-37c77602660d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597529003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3597529003
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.4050597635
Short name T531
Test name
Test status
Simulation time 138118857217 ps
CPU time 178.98 seconds
Started Jul 12 05:44:42 PM PDT 24
Finished Jul 12 05:47:42 PM PDT 24
Peak memory 198800 kb
Host smart-3f9e7c14-bce4-448f-8b21-8afb8523acdf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050597635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.4050597635
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.1145496716
Short name T536
Test name
Test status
Simulation time 63123695664 ps
CPU time 394.93 seconds
Started Jul 12 05:44:43 PM PDT 24
Finished Jul 12 05:51:19 PM PDT 24
Peak memory 198900 kb
Host smart-d0f4b724-dfe5-46b9-b6a0-3f7072e85492
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1145496716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.1145496716
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1675812435
Short name T156
Test name
Test status
Simulation time 35372891 ps
CPU time 0.55 seconds
Started Jul 12 05:44:43 PM PDT 24
Finished Jul 12 05:44:45 PM PDT 24
Peak memory 195360 kb
Host smart-b44ee8b5-f4e6-4b47-9352-fd54c954591e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675812435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1675812435
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1250246248
Short name T622
Test name
Test status
Simulation time 132756999 ps
CPU time 0.76 seconds
Started Jul 12 05:44:47 PM PDT 24
Finished Jul 12 05:44:49 PM PDT 24
Peak memory 195856 kb
Host smart-28d610de-7a3f-4bc2-b3d7-61eaa220421f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250246248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1250246248
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2560613767
Short name T295
Test name
Test status
Simulation time 3515760619 ps
CPU time 20.69 seconds
Started Jul 12 05:44:50 PM PDT 24
Finished Jul 12 05:45:12 PM PDT 24
Peak memory 197240 kb
Host smart-38891e43-9b60-4ae2-8a46-3dde622c3ed1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560613767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2560613767
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1435706778
Short name T119
Test name
Test status
Simulation time 150319687 ps
CPU time 0.75 seconds
Started Jul 12 05:44:43 PM PDT 24
Finished Jul 12 05:44:45 PM PDT 24
Peak memory 197140 kb
Host smart-704057ff-02fe-4797-8ac0-56d3fc5db7db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435706778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1435706778
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.667948722
Short name T600
Test name
Test status
Simulation time 497529077 ps
CPU time 1.15 seconds
Started Jul 12 05:44:45 PM PDT 24
Finished Jul 12 05:44:47 PM PDT 24
Peak memory 196704 kb
Host smart-cc9c8309-004d-4d52-b251-c9c2828a03e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667948722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.667948722
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3414711346
Short name T194
Test name
Test status
Simulation time 798943691 ps
CPU time 2.82 seconds
Started Jul 12 05:44:44 PM PDT 24
Finished Jul 12 05:44:48 PM PDT 24
Peak memory 198660 kb
Host smart-8cb7fb3c-c79a-4f08-9654-3b2c5f0904f4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414711346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3414711346
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3429883477
Short name T620
Test name
Test status
Simulation time 118790412 ps
CPU time 3.4 seconds
Started Jul 12 05:44:44 PM PDT 24
Finished Jul 12 05:44:48 PM PDT 24
Peak memory 197748 kb
Host smart-80ea8aba-51bb-48a7-9e3f-d87561db0afe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429883477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3429883477
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.456008617
Short name T441
Test name
Test status
Simulation time 166697307 ps
CPU time 1.02 seconds
Started Jul 12 05:44:44 PM PDT 24
Finished Jul 12 05:44:46 PM PDT 24
Peak memory 196888 kb
Host smart-3b87e820-ec47-460d-a2ef-4d7799f00133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456008617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.456008617
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2103364051
Short name T372
Test name
Test status
Simulation time 98842486 ps
CPU time 1.05 seconds
Started Jul 12 05:44:41 PM PDT 24
Finished Jul 12 05:44:44 PM PDT 24
Peak memory 196412 kb
Host smart-fa71274f-e722-4fea-849b-6adc19ad9e07
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103364051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2103364051
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2434734857
Short name T260
Test name
Test status
Simulation time 507369694 ps
CPU time 2.21 seconds
Started Jul 12 05:44:43 PM PDT 24
Finished Jul 12 05:44:46 PM PDT 24
Peak memory 198640 kb
Host smart-dd4a0d52-8fa1-4776-b2b1-6f9e8267218a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434734857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2434734857
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2717294669
Short name T247
Test name
Test status
Simulation time 40823369 ps
CPU time 0.84 seconds
Started Jul 12 05:44:44 PM PDT 24
Finished Jul 12 05:44:46 PM PDT 24
Peak memory 196784 kb
Host smart-0400eaa6-0c27-4da0-b0f6-0b146ab03577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717294669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2717294669
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3305504865
Short name T252
Test name
Test status
Simulation time 73160977 ps
CPU time 1.16 seconds
Started Jul 12 05:44:43 PM PDT 24
Finished Jul 12 05:44:46 PM PDT 24
Peak memory 197500 kb
Host smart-daf7cfeb-d74a-4538-a705-7f0eb74536f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305504865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3305504865
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.2112166836
Short name T4
Test name
Test status
Simulation time 32019232581 ps
CPU time 91.86 seconds
Started Jul 12 05:44:42 PM PDT 24
Finished Jul 12 05:46:16 PM PDT 24
Peak memory 198716 kb
Host smart-6589193e-0f79-4f03-ae7f-2344bb1846db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112166836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.2112166836
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.724491281
Short name T391
Test name
Test status
Simulation time 132336016998 ps
CPU time 1548.9 seconds
Started Jul 12 05:44:43 PM PDT 24
Finished Jul 12 06:10:34 PM PDT 24
Peak memory 198868 kb
Host smart-7ca88a2a-d5c2-46d5-a83d-ecc4da2c63ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=724491281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.724491281
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.4098246572
Short name T208
Test name
Test status
Simulation time 10458739 ps
CPU time 0.6 seconds
Started Jul 12 05:44:48 PM PDT 24
Finished Jul 12 05:44:50 PM PDT 24
Peak memory 195336 kb
Host smart-32e71e89-6e52-4c9c-8aa7-586756c4b478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098246572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.4098246572
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.857168058
Short name T572
Test name
Test status
Simulation time 144961123 ps
CPU time 0.68 seconds
Started Jul 12 05:44:46 PM PDT 24
Finished Jul 12 05:44:48 PM PDT 24
Peak memory 195800 kb
Host smart-cedf8b19-1232-4954-b1e3-2d1a347377df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857168058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.857168058
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1444385275
Short name T352
Test name
Test status
Simulation time 807966888 ps
CPU time 22.54 seconds
Started Jul 12 05:44:48 PM PDT 24
Finished Jul 12 05:45:12 PM PDT 24
Peak memory 197368 kb
Host smart-a634260a-c614-4d46-9674-7af7889efdc3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444385275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1444385275
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3708073476
Short name T364
Test name
Test status
Simulation time 21079774 ps
CPU time 0.64 seconds
Started Jul 12 05:44:47 PM PDT 24
Finished Jul 12 05:44:49 PM PDT 24
Peak memory 194996 kb
Host smart-d8355c4b-1670-4ceb-aeef-7411e436d59e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708073476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3708073476
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3739550981
Short name T353
Test name
Test status
Simulation time 32737215 ps
CPU time 0.65 seconds
Started Jul 12 05:44:50 PM PDT 24
Finished Jul 12 05:44:51 PM PDT 24
Peak memory 195636 kb
Host smart-b4a3466a-1bbb-487f-bb4b-83b3522cb670
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739550981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3739550981
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.614700484
Short name T17
Test name
Test status
Simulation time 384805622 ps
CPU time 3.76 seconds
Started Jul 12 05:44:47 PM PDT 24
Finished Jul 12 05:44:52 PM PDT 24
Peak memory 198504 kb
Host smart-68a3b73e-772a-4920-808a-388e138c545c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614700484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.gpio_intr_with_filter_rand_intr_event.614700484
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.143582938
Short name T161
Test name
Test status
Simulation time 471112134 ps
CPU time 3.09 seconds
Started Jul 12 05:44:51 PM PDT 24
Finished Jul 12 05:44:55 PM PDT 24
Peak memory 196432 kb
Host smart-681e5d7e-55df-45df-8fea-dfc5232e2263
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143582938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
143582938
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1958879536
Short name T627
Test name
Test status
Simulation time 123338796 ps
CPU time 1.1 seconds
Started Jul 12 05:44:51 PM PDT 24
Finished Jul 12 05:44:54 PM PDT 24
Peak memory 196712 kb
Host smart-a513cebd-3e5e-4a43-b9b3-cfaa1bd96a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958879536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1958879536
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1610909146
Short name T311
Test name
Test status
Simulation time 51249788 ps
CPU time 0.73 seconds
Started Jul 12 05:44:49 PM PDT 24
Finished Jul 12 05:44:51 PM PDT 24
Peak memory 195984 kb
Host smart-0f3ee166-de6f-4a45-88a9-1445e583f1a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610909146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1610909146
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2264037116
Short name T494
Test name
Test status
Simulation time 229830646 ps
CPU time 3.37 seconds
Started Jul 12 05:44:49 PM PDT 24
Finished Jul 12 05:44:54 PM PDT 24
Peak memory 198648 kb
Host smart-f58c4c1b-30bb-4832-9ba4-fbc46de0d097
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264037116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2264037116
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3663282645
Short name T71
Test name
Test status
Simulation time 230642955 ps
CPU time 1.29 seconds
Started Jul 12 05:44:42 PM PDT 24
Finished Jul 12 05:44:45 PM PDT 24
Peak memory 197212 kb
Host smart-6b9c1720-ba7f-4af0-8a2b-84dcba013d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663282645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3663282645
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.4293451372
Short name T565
Test name
Test status
Simulation time 142383998 ps
CPU time 0.89 seconds
Started Jul 12 05:44:42 PM PDT 24
Finished Jul 12 05:44:44 PM PDT 24
Peak memory 196784 kb
Host smart-d5dace69-475a-4a7e-85a6-76fa7c9f3855
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293451372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.4293451372
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.2678639851
Short name T288
Test name
Test status
Simulation time 7913239920 ps
CPU time 111.01 seconds
Started Jul 12 05:44:47 PM PDT 24
Finished Jul 12 05:46:38 PM PDT 24
Peak memory 198692 kb
Host smart-ed5edeac-d0ab-48d8-9108-1d287e15774a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678639851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.2678639851
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.840086788
Short name T41
Test name
Test status
Simulation time 21221301 ps
CPU time 0.58 seconds
Started Jul 12 06:09:55 PM PDT 24
Finished Jul 12 06:11:39 PM PDT 24
Peak memory 195360 kb
Host smart-1b4329b7-f787-4918-a001-0dd2ba21bf66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840086788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.840086788
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2154735422
Short name T645
Test name
Test status
Simulation time 47555321 ps
CPU time 0.63 seconds
Started Jul 12 05:44:48 PM PDT 24
Finished Jul 12 05:44:50 PM PDT 24
Peak memory 194732 kb
Host smart-87f603c0-00d1-40eb-b364-2eba5f0fc2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154735422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2154735422
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3126541174
Short name T632
Test name
Test status
Simulation time 264592551 ps
CPU time 13.47 seconds
Started Jul 12 05:44:51 PM PDT 24
Finished Jul 12 05:45:06 PM PDT 24
Peak memory 197452 kb
Host smart-637f5747-28da-4dcf-ab13-06c16d1493fa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126541174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3126541174
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3311628133
Short name T439
Test name
Test status
Simulation time 214328021 ps
CPU time 0.83 seconds
Started Jul 12 05:44:48 PM PDT 24
Finished Jul 12 05:44:50 PM PDT 24
Peak memory 197260 kb
Host smart-49a40e28-506f-4e48-934b-c442d2f3224c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311628133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3311628133
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3243776978
Short name T314
Test name
Test status
Simulation time 149181124 ps
CPU time 0.84 seconds
Started Jul 12 05:44:47 PM PDT 24
Finished Jul 12 05:44:49 PM PDT 24
Peak memory 196316 kb
Host smart-72e17e1c-5dec-4cc5-80f5-ef1666b0f826
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243776978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3243776978
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.282407030
Short name T211
Test name
Test status
Simulation time 52158324 ps
CPU time 1.99 seconds
Started Jul 12 05:44:49 PM PDT 24
Finished Jul 12 05:44:52 PM PDT 24
Peak memory 198488 kb
Host smart-cfb0ee39-4f77-4f91-a7e5-f054fd6445a5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282407030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.gpio_intr_with_filter_rand_intr_event.282407030
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1473877582
Short name T681
Test name
Test status
Simulation time 146301355 ps
CPU time 1.78 seconds
Started Jul 12 05:44:49 PM PDT 24
Finished Jul 12 05:44:52 PM PDT 24
Peak memory 197468 kb
Host smart-5e0a3d1e-7a4d-457d-9f9a-e8ddbf04e7c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473877582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1473877582
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.545872900
Short name T543
Test name
Test status
Simulation time 351481368 ps
CPU time 0.86 seconds
Started Jul 12 05:44:52 PM PDT 24
Finished Jul 12 05:44:54 PM PDT 24
Peak memory 197948 kb
Host smart-be4b28d0-1fb7-4191-b73b-e787f12ae36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545872900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.545872900
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3595569995
Short name T644
Test name
Test status
Simulation time 110879928 ps
CPU time 1.17 seconds
Started Jul 12 05:44:49 PM PDT 24
Finished Jul 12 05:44:51 PM PDT 24
Peak memory 198728 kb
Host smart-aa4788f9-61bb-4eb0-9f4f-28e1edaf47a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595569995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3595569995
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2991522949
Short name T299
Test name
Test status
Simulation time 677675964 ps
CPU time 3.02 seconds
Started Jul 12 05:44:51 PM PDT 24
Finished Jul 12 05:44:56 PM PDT 24
Peak memory 198524 kb
Host smart-918614fe-55f6-4998-b0cb-d956343322be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991522949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2991522949
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1859521704
Short name T663
Test name
Test status
Simulation time 37002511 ps
CPU time 1.08 seconds
Started Jul 12 05:44:49 PM PDT 24
Finished Jul 12 05:44:51 PM PDT 24
Peak memory 197400 kb
Host smart-e1006f6d-7f91-48d6-8f3c-ba9cbab25600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859521704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1859521704
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.1730912636
Short name T528
Test name
Test status
Simulation time 78376058 ps
CPU time 1.26 seconds
Started Jul 12 05:44:49 PM PDT 24
Finished Jul 12 05:44:52 PM PDT 24
Peak memory 196224 kb
Host smart-b07369da-921d-40ab-894e-900b43f024d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730912636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.1730912636
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.518201737
Short name T258
Test name
Test status
Simulation time 4335567419 ps
CPU time 120.15 seconds
Started Jul 12 05:44:49 PM PDT 24
Finished Jul 12 05:46:51 PM PDT 24
Peak memory 198992 kb
Host smart-8690a1a6-753e-46d8-b104-17a90cf371a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518201737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.518201737
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.2862115198
Short name T60
Test name
Test status
Simulation time 66328215821 ps
CPU time 967.2 seconds
Started Jul 12 06:21:37 PM PDT 24
Finished Jul 12 06:37:45 PM PDT 24
Peak memory 198864 kb
Host smart-fd7a09f8-6a9c-40b4-a131-75238400e269
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2862115198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.2862115198
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3811748548
Short name T279
Test name
Test status
Simulation time 35218921 ps
CPU time 0.59 seconds
Started Jul 12 05:44:50 PM PDT 24
Finished Jul 12 05:44:52 PM PDT 24
Peak memory 194660 kb
Host smart-fc8882c5-659e-4340-b2e8-49f39073c92c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811748548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3811748548
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1121595812
Short name T347
Test name
Test status
Simulation time 57906850 ps
CPU time 0.84 seconds
Started Jul 12 05:44:47 PM PDT 24
Finished Jul 12 05:44:49 PM PDT 24
Peak memory 196588 kb
Host smart-035f1c93-2275-41d8-ab79-c6be68700175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121595812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1121595812
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3860260664
Short name T322
Test name
Test status
Simulation time 1270281099 ps
CPU time 20.52 seconds
Started Jul 12 05:44:48 PM PDT 24
Finished Jul 12 05:45:10 PM PDT 24
Peak memory 197620 kb
Host smart-4dad09a4-c3c5-4a71-bb83-b5970801fc41
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860260664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3860260664
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2817507888
Short name T571
Test name
Test status
Simulation time 57653717 ps
CPU time 0.88 seconds
Started Jul 12 05:44:52 PM PDT 24
Finished Jul 12 05:44:54 PM PDT 24
Peak memory 196544 kb
Host smart-22628dd5-7950-4b38-ad9f-f5a618460193
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817507888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2817507888
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.718920944
Short name T430
Test name
Test status
Simulation time 43809002 ps
CPU time 1.21 seconds
Started Jul 12 05:44:48 PM PDT 24
Finished Jul 12 05:44:50 PM PDT 24
Peak memory 197312 kb
Host smart-5e62bbd7-a030-4408-b05c-07d9f6bff399
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718920944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.718920944
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3997192023
Short name T245
Test name
Test status
Simulation time 256394704 ps
CPU time 2.86 seconds
Started Jul 12 05:44:48 PM PDT 24
Finished Jul 12 05:44:52 PM PDT 24
Peak memory 198644 kb
Host smart-c3f8512b-b482-4f78-b494-94f81251d83b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997192023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3997192023
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1899640704
Short name T150
Test name
Test status
Simulation time 105564500 ps
CPU time 1.32 seconds
Started Jul 12 05:44:46 PM PDT 24
Finished Jul 12 05:44:48 PM PDT 24
Peak memory 198240 kb
Host smart-f5527396-c499-4465-bb20-10e302aaf851
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899640704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1899640704
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1083087551
Short name T336
Test name
Test status
Simulation time 234692421 ps
CPU time 1.17 seconds
Started Jul 12 05:44:46 PM PDT 24
Finished Jul 12 05:44:48 PM PDT 24
Peak memory 196464 kb
Host smart-2bfa8ce6-66d9-4f2c-b828-5f7fff653820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083087551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1083087551
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3520726855
Short name T19
Test name
Test status
Simulation time 219680964 ps
CPU time 1.27 seconds
Started Jul 12 05:44:49 PM PDT 24
Finished Jul 12 05:44:52 PM PDT 24
Peak memory 197692 kb
Host smart-096bda70-1a13-45eb-813e-5e638dc433c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520726855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3520726855
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3505080572
Short name T117
Test name
Test status
Simulation time 212409068 ps
CPU time 3.4 seconds
Started Jul 12 05:44:52 PM PDT 24
Finished Jul 12 05:44:56 PM PDT 24
Peak memory 198588 kb
Host smart-c2fe5aca-b07c-436f-82f3-0f4ab261faa2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505080572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3505080572
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3292375119
Short name T490
Test name
Test status
Simulation time 53877041 ps
CPU time 1.44 seconds
Started Jul 12 05:56:47 PM PDT 24
Finished Jul 12 05:56:49 PM PDT 24
Peak memory 197508 kb
Host smart-486bbe29-b9d9-4b33-a7b6-78e56edae278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292375119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3292375119
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2994652184
Short name T281
Test name
Test status
Simulation time 87164470 ps
CPU time 1.41 seconds
Started Jul 12 05:44:48 PM PDT 24
Finished Jul 12 05:44:51 PM PDT 24
Peak memory 198616 kb
Host smart-7acdf244-af90-4dd3-9a64-a8a4f7136ffa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994652184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2994652184
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.750527902
Short name T554
Test name
Test status
Simulation time 23155300816 ps
CPU time 163.37 seconds
Started Jul 12 05:44:49 PM PDT 24
Finished Jul 12 05:47:34 PM PDT 24
Peak memory 199044 kb
Host smart-6a902b85-f001-4113-8252-09e179a60c2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750527902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.750527902
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.3853914169
Short name T65
Test name
Test status
Simulation time 120273316757 ps
CPU time 288.36 seconds
Started Jul 12 05:44:46 PM PDT 24
Finished Jul 12 05:49:35 PM PDT 24
Peak memory 198924 kb
Host smart-9588b679-102d-4483-8d61-72d09f1801ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3853914169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.3853914169
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2804061529
Short name T239
Test name
Test status
Simulation time 30509127 ps
CPU time 0.58 seconds
Started Jul 12 05:44:54 PM PDT 24
Finished Jul 12 05:44:57 PM PDT 24
Peak memory 194584 kb
Host smart-c8d7c717-f27f-4d01-b8fd-d2aa513cb68e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804061529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2804061529
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1514323566
Short name T58
Test name
Test status
Simulation time 43158407 ps
CPU time 0.92 seconds
Started Jul 12 05:44:54 PM PDT 24
Finished Jul 12 05:44:58 PM PDT 24
Peak memory 197980 kb
Host smart-873b187a-be0b-4e9c-9eaf-798dcf70faa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514323566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1514323566
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1953493585
Short name T507
Test name
Test status
Simulation time 698702239 ps
CPU time 4.98 seconds
Started Jul 12 05:44:58 PM PDT 24
Finished Jul 12 05:45:06 PM PDT 24
Peak memory 196624 kb
Host smart-c735ffbf-ddf4-4f54-a7d4-9a823f3645a5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953493585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1953493585
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.755965602
Short name T625
Test name
Test status
Simulation time 85824971 ps
CPU time 0.66 seconds
Started Jul 12 05:44:54 PM PDT 24
Finished Jul 12 05:44:57 PM PDT 24
Peak memory 195068 kb
Host smart-5b941122-6cfd-4834-811c-de481b2820a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755965602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.755965602
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.172211970
Short name T546
Test name
Test status
Simulation time 42626849 ps
CPU time 1.17 seconds
Started Jul 12 05:44:58 PM PDT 24
Finished Jul 12 05:45:02 PM PDT 24
Peak memory 196416 kb
Host smart-a2fdfeb4-165d-4925-a1c5-430601033c4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172211970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.172211970
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.4062584983
Short name T251
Test name
Test status
Simulation time 319207154 ps
CPU time 3.28 seconds
Started Jul 12 05:44:53 PM PDT 24
Finished Jul 12 05:44:58 PM PDT 24
Peak memory 198768 kb
Host smart-c988c1b9-c0ac-43de-b230-2b876f489f3e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062584983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.4062584983
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.201053986
Short name T469
Test name
Test status
Simulation time 188596904 ps
CPU time 3.43 seconds
Started Jul 12 05:44:57 PM PDT 24
Finished Jul 12 05:45:03 PM PDT 24
Peak memory 198608 kb
Host smart-60c921a3-21e0-4ee5-8fd2-176e1a899b5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201053986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
201053986
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.4133878454
Short name T167
Test name
Test status
Simulation time 98101117 ps
CPU time 1.16 seconds
Started Jul 12 05:44:59 PM PDT 24
Finished Jul 12 05:45:02 PM PDT 24
Peak memory 196800 kb
Host smart-955a9b4f-97bb-4fc4-88b9-87b7ce1ec771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133878454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.4133878454
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1250261584
Short name T185
Test name
Test status
Simulation time 53194559 ps
CPU time 1.28 seconds
Started Jul 12 05:44:52 PM PDT 24
Finished Jul 12 05:44:55 PM PDT 24
Peak memory 198760 kb
Host smart-dac8e6de-e461-49d1-9225-6d8f78e75a68
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250261584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1250261584
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1879142733
Short name T243
Test name
Test status
Simulation time 530591977 ps
CPU time 6.45 seconds
Started Jul 12 05:44:53 PM PDT 24
Finished Jul 12 05:45:01 PM PDT 24
Peak memory 198580 kb
Host smart-1e3a5f12-bf6e-41e4-bc9d-83c9e2877874
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879142733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1879142733
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.4239595210
Short name T516
Test name
Test status
Simulation time 185917437 ps
CPU time 0.91 seconds
Started Jul 12 05:44:53 PM PDT 24
Finished Jul 12 05:44:57 PM PDT 24
Peak memory 195932 kb
Host smart-5b1d6a48-23c5-4676-a69f-dcc247282825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239595210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.4239595210
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.823109427
Short name T15
Test name
Test status
Simulation time 56357880 ps
CPU time 1.04 seconds
Started Jul 12 05:44:50 PM PDT 24
Finished Jul 12 05:44:53 PM PDT 24
Peak memory 196364 kb
Host smart-2642be91-0983-4047-b4d4-277d236e4353
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823109427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.823109427
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.4242813897
Short name T628
Test name
Test status
Simulation time 2122609464 ps
CPU time 56.52 seconds
Started Jul 12 05:44:58 PM PDT 24
Finished Jul 12 05:45:57 PM PDT 24
Peak memory 198708 kb
Host smart-76d6661d-b8aa-4324-b683-531745169d2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242813897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.4242813897
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.2144152178
Short name T64
Test name
Test status
Simulation time 13910713342 ps
CPU time 78.96 seconds
Started Jul 12 05:44:56 PM PDT 24
Finished Jul 12 05:46:19 PM PDT 24
Peak memory 198904 kb
Host smart-68ad50f3-3434-47e4-8091-3407000087f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2144152178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.2144152178
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1278968937
Short name T213
Test name
Test status
Simulation time 46155271 ps
CPU time 0.58 seconds
Started Jul 12 05:44:54 PM PDT 24
Finished Jul 12 05:44:56 PM PDT 24
Peak memory 195328 kb
Host smart-536f7c95-84d5-4162-935a-606bcd3753b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278968937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1278968937
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1869198901
Short name T54
Test name
Test status
Simulation time 96990851 ps
CPU time 0.71 seconds
Started Jul 12 05:44:54 PM PDT 24
Finished Jul 12 05:44:58 PM PDT 24
Peak memory 194736 kb
Host smart-6a058251-ff4f-4c51-9b13-4b078a69a93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869198901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1869198901
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.150769495
Short name T283
Test name
Test status
Simulation time 1548331732 ps
CPU time 19.49 seconds
Started Jul 12 05:44:52 PM PDT 24
Finished Jul 12 05:45:13 PM PDT 24
Peak memory 197620 kb
Host smart-a8aff2ed-8fd5-45c2-bd08-db94e32698f7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150769495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.150769495
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1398858759
Short name T431
Test name
Test status
Simulation time 373300622 ps
CPU time 0.75 seconds
Started Jul 12 05:44:53 PM PDT 24
Finished Jul 12 05:44:55 PM PDT 24
Peak memory 195336 kb
Host smart-a9feecef-8838-4fb6-9c7a-046c4fd4e1e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398858759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1398858759
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2783487515
Short name T604
Test name
Test status
Simulation time 80547603 ps
CPU time 0.7 seconds
Started Jul 12 05:44:56 PM PDT 24
Finished Jul 12 05:45:01 PM PDT 24
Peak memory 194912 kb
Host smart-957aa531-064c-4fb3-b0b6-4a1ccc70d494
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783487515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2783487515
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.625581545
Short name T122
Test name
Test status
Simulation time 327504500 ps
CPU time 3.39 seconds
Started Jul 12 05:44:55 PM PDT 24
Finished Jul 12 05:45:01 PM PDT 24
Peak memory 198652 kb
Host smart-dca59e9a-42d8-4b1d-9ace-eb432ab29652
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625581545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.625581545
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3198595615
Short name T561
Test name
Test status
Simulation time 1490350687 ps
CPU time 3.27 seconds
Started Jul 12 05:44:55 PM PDT 24
Finished Jul 12 05:45:02 PM PDT 24
Peak memory 197816 kb
Host smart-1ad76523-ed3b-4f74-9ac2-2e8bfeae5a2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198595615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3198595615
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2324138497
Short name T181
Test name
Test status
Simulation time 41726277 ps
CPU time 0.92 seconds
Started Jul 12 05:44:58 PM PDT 24
Finished Jul 12 05:45:02 PM PDT 24
Peak memory 196492 kb
Host smart-6eb217c9-40cc-4f1d-bb4e-044a081fbe67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324138497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2324138497
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1243703195
Short name T582
Test name
Test status
Simulation time 92807465 ps
CPU time 1.23 seconds
Started Jul 12 05:44:58 PM PDT 24
Finished Jul 12 05:45:02 PM PDT 24
Peak memory 197280 kb
Host smart-6e5b5ed3-6b79-4fb1-82d8-2afc04b8d9e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243703195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1243703195
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2069578213
Short name T500
Test name
Test status
Simulation time 3539016989 ps
CPU time 2.54 seconds
Started Jul 12 05:44:54 PM PDT 24
Finished Jul 12 05:45:00 PM PDT 24
Peak memory 198664 kb
Host smart-0da21d6f-39ba-499b-923f-4431ad2e8ec4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069578213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2069578213
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.4112859165
Short name T13
Test name
Test status
Simulation time 481633489 ps
CPU time 1.03 seconds
Started Jul 12 05:44:55 PM PDT 24
Finished Jul 12 05:45:00 PM PDT 24
Peak memory 196544 kb
Host smart-1344dcfe-1b14-4860-a699-e037d33ecc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112859165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.4112859165
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3076204056
Short name T337
Test name
Test status
Simulation time 70270529 ps
CPU time 0.95 seconds
Started Jul 12 05:44:58 PM PDT 24
Finished Jul 12 05:45:02 PM PDT 24
Peak memory 196472 kb
Host smart-60862c6b-4209-4ce3-9685-a56bfaab5125
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076204056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3076204056
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3083362016
Short name T123
Test name
Test status
Simulation time 5809210979 ps
CPU time 151.14 seconds
Started Jul 12 05:44:54 PM PDT 24
Finished Jul 12 05:47:28 PM PDT 24
Peak memory 198812 kb
Host smart-4af64d86-4597-4f18-aa16-0c9eba8dfc0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083362016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3083362016
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.4002414613
Short name T32
Test name
Test status
Simulation time 13942670048 ps
CPU time 319.82 seconds
Started Jul 12 05:44:54 PM PDT 24
Finished Jul 12 05:50:17 PM PDT 24
Peak memory 199144 kb
Host smart-5c04b23d-c766-417b-af90-3d38c32c6e0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4002414613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.4002414613
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2364542204
Short name T53
Test name
Test status
Simulation time 13521687 ps
CPU time 0.64 seconds
Started Jul 12 05:45:00 PM PDT 24
Finished Jul 12 05:45:03 PM PDT 24
Peak memory 194180 kb
Host smart-52f4138e-6bde-4cb2-9101-57b3aa64f1bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364542204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2364542204
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2207798560
Short name T416
Test name
Test status
Simulation time 25173802 ps
CPU time 0.83 seconds
Started Jul 12 05:44:57 PM PDT 24
Finished Jul 12 05:45:01 PM PDT 24
Peak memory 195848 kb
Host smart-fbb4c4b9-9191-435b-8b0b-83912f067af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207798560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2207798560
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.29867898
Short name T472
Test name
Test status
Simulation time 982957788 ps
CPU time 25.69 seconds
Started Jul 12 05:45:02 PM PDT 24
Finished Jul 12 05:45:29 PM PDT 24
Peak memory 197636 kb
Host smart-0e199232-2cc6-41b4-8d76-0fa64432e741
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29867898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stress
.29867898
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1009430203
Short name T141
Test name
Test status
Simulation time 65385417 ps
CPU time 1.01 seconds
Started Jul 12 05:45:02 PM PDT 24
Finished Jul 12 05:45:05 PM PDT 24
Peak memory 197312 kb
Host smart-b3183bfb-3354-478f-8a79-260508047a5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009430203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1009430203
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3142660347
Short name T154
Test name
Test status
Simulation time 24637679 ps
CPU time 0.86 seconds
Started Jul 12 05:44:55 PM PDT 24
Finished Jul 12 05:44:59 PM PDT 24
Peak memory 197128 kb
Host smart-90c25db5-098d-43fa-9964-517fdfe5413c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142660347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3142660347
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.415327430
Short name T111
Test name
Test status
Simulation time 81615369 ps
CPU time 3.22 seconds
Started Jul 12 05:44:53 PM PDT 24
Finished Jul 12 05:44:58 PM PDT 24
Peak memory 198776 kb
Host smart-a90e9e80-731f-4107-bf79-9aea4b261c19
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415327430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.415327430
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2396676979
Short name T250
Test name
Test status
Simulation time 153737802 ps
CPU time 3.3 seconds
Started Jul 12 05:44:55 PM PDT 24
Finished Jul 12 05:45:02 PM PDT 24
Peak memory 198668 kb
Host smart-05447bca-b378-4ddf-bc30-a89208ac4bfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396676979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2396676979
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2115092973
Short name T228
Test name
Test status
Simulation time 208190482 ps
CPU time 1.27 seconds
Started Jul 12 05:44:56 PM PDT 24
Finished Jul 12 05:45:00 PM PDT 24
Peak memory 196684 kb
Host smart-d20af549-0836-402c-bf52-de2a4704975a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115092973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2115092973
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2937054294
Short name T28
Test name
Test status
Simulation time 31847164 ps
CPU time 0.76 seconds
Started Jul 12 05:44:54 PM PDT 24
Finished Jul 12 05:44:58 PM PDT 24
Peak memory 195952 kb
Host smart-0db9d812-3b19-4f6a-a620-19ff17edd0e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937054294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.2937054294
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.151219627
Short name T383
Test name
Test status
Simulation time 478095269 ps
CPU time 3.79 seconds
Started Jul 12 05:44:58 PM PDT 24
Finished Jul 12 05:45:04 PM PDT 24
Peak memory 198584 kb
Host smart-be9d88a8-609c-40ab-b2e5-06e2a5c6f689
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151219627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.151219627
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1585400592
Short name T592
Test name
Test status
Simulation time 68964385 ps
CPU time 1.34 seconds
Started Jul 12 05:44:53 PM PDT 24
Finished Jul 12 05:44:57 PM PDT 24
Peak memory 197492 kb
Host smart-4c1b37c4-ad2c-43c3-bbea-9ba1c3e66e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585400592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1585400592
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.334632394
Short name T685
Test name
Test status
Simulation time 70306173 ps
CPU time 1.36 seconds
Started Jul 12 05:44:52 PM PDT 24
Finished Jul 12 05:44:55 PM PDT 24
Peak memory 198492 kb
Host smart-6af96174-6db5-4fc1-894e-461981a5d42c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334632394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.334632394
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.636829262
Short name T227
Test name
Test status
Simulation time 10821158262 ps
CPU time 214.03 seconds
Started Jul 12 05:45:02 PM PDT 24
Finished Jul 12 05:48:38 PM PDT 24
Peak memory 198740 kb
Host smart-87bd57fe-cbc7-480e-8068-ad50ec1deca2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636829262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.636829262
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.762249180
Short name T62
Test name
Test status
Simulation time 59409469634 ps
CPU time 1743.11 seconds
Started Jul 12 05:45:00 PM PDT 24
Finished Jul 12 06:14:05 PM PDT 24
Peak memory 198836 kb
Host smart-eee11dcf-ba19-408d-9d7e-d28daf4640b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=762249180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.762249180
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2078065003
Short name T619
Test name
Test status
Simulation time 26059607 ps
CPU time 0.56 seconds
Started Jul 12 05:44:59 PM PDT 24
Finished Jul 12 05:45:02 PM PDT 24
Peak memory 194860 kb
Host smart-1b8990cf-5dca-4ba7-8188-2a9d83e3a74e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078065003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2078065003
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2146225564
Short name T488
Test name
Test status
Simulation time 332653539 ps
CPU time 0.87 seconds
Started Jul 12 05:45:01 PM PDT 24
Finished Jul 12 05:45:04 PM PDT 24
Peak memory 197208 kb
Host smart-68ac6a3b-d076-4a44-8033-e1887a0a3c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146225564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2146225564
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3436709587
Short name T170
Test name
Test status
Simulation time 143540584 ps
CPU time 7.06 seconds
Started Jul 12 05:45:01 PM PDT 24
Finished Jul 12 05:45:10 PM PDT 24
Peak memory 196836 kb
Host smart-5feea906-e53b-4201-8cf4-efb3c2da80cc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436709587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3436709587
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3953949607
Short name T529
Test name
Test status
Simulation time 172436587 ps
CPU time 1.12 seconds
Started Jul 12 05:45:02 PM PDT 24
Finished Jul 12 05:45:05 PM PDT 24
Peak memory 197040 kb
Host smart-270827cb-a6e7-471c-b84f-41423332d17c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953949607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3953949607
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.4205890218
Short name T465
Test name
Test status
Simulation time 202508127 ps
CPU time 0.95 seconds
Started Jul 12 05:45:00 PM PDT 24
Finished Jul 12 05:45:03 PM PDT 24
Peak memory 196460 kb
Host smart-18c122a1-8f17-4c76-92ed-8c12fc3a59b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205890218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.4205890218
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.886166741
Short name T56
Test name
Test status
Simulation time 44165617 ps
CPU time 0.99 seconds
Started Jul 12 05:45:03 PM PDT 24
Finished Jul 12 05:45:05 PM PDT 24
Peak memory 196792 kb
Host smart-d14522ab-b2f1-4eb0-b8e4-2a9e410e7be9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886166741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.886166741
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.4036255911
Short name T136
Test name
Test status
Simulation time 144786364 ps
CPU time 3.33 seconds
Started Jul 12 05:45:00 PM PDT 24
Finished Jul 12 05:45:06 PM PDT 24
Peak memory 198680 kb
Host smart-4fd411f5-1ead-4e43-a109-d143cb6ccb7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036255911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.4036255911
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3399269881
Short name T155
Test name
Test status
Simulation time 113976831 ps
CPU time 1.06 seconds
Started Jul 12 05:44:59 PM PDT 24
Finished Jul 12 05:45:02 PM PDT 24
Peak memory 196692 kb
Host smart-a07807a1-fba3-443b-8b88-daf8c43bcb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399269881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3399269881
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2082932548
Short name T335
Test name
Test status
Simulation time 35948386 ps
CPU time 1.22 seconds
Started Jul 12 05:45:01 PM PDT 24
Finished Jul 12 05:45:05 PM PDT 24
Peak memory 197620 kb
Host smart-24df7412-e566-4d4e-befc-0cdd56d697fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082932548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2082932548
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2811561970
Short name T8
Test name
Test status
Simulation time 201501775 ps
CPU time 3.21 seconds
Started Jul 12 05:44:58 PM PDT 24
Finished Jul 12 05:45:04 PM PDT 24
Peak memory 198400 kb
Host smart-1962bf3c-a077-4989-a12a-81f43923d3f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811561970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2811561970
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1099097043
Short name T388
Test name
Test status
Simulation time 71744596 ps
CPU time 0.75 seconds
Started Jul 12 05:45:01 PM PDT 24
Finished Jul 12 05:45:04 PM PDT 24
Peak memory 195748 kb
Host smart-457035d1-f929-4f8e-b069-aabc039795bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099097043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1099097043
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.807337256
Short name T144
Test name
Test status
Simulation time 136699815 ps
CPU time 0.99 seconds
Started Jul 12 05:44:58 PM PDT 24
Finished Jul 12 05:45:02 PM PDT 24
Peak memory 196256 kb
Host smart-de82a5b9-c868-4d0d-9834-3be39953c3ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807337256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.807337256
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3582044087
Short name T553
Test name
Test status
Simulation time 11630551596 ps
CPU time 73 seconds
Started Jul 12 05:45:02 PM PDT 24
Finished Jul 12 05:46:17 PM PDT 24
Peak memory 199044 kb
Host smart-2d93ad2d-8d40-4a32-9267-1f8eac043f69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582044087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3582044087
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3044861440
Short name T40
Test name
Test status
Simulation time 18431505 ps
CPU time 0.58 seconds
Started Jul 12 05:43:25 PM PDT 24
Finished Jul 12 05:43:27 PM PDT 24
Peak memory 194648 kb
Host smart-65f11d33-2e71-4030-872c-92703f803c22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044861440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3044861440
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1002022071
Short name T555
Test name
Test status
Simulation time 135642004 ps
CPU time 0.8 seconds
Started Jul 12 05:43:22 PM PDT 24
Finished Jul 12 05:43:23 PM PDT 24
Peak memory 195836 kb
Host smart-c7f406fa-9487-48bc-b4bd-329e44cc7a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002022071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1002022071
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1131427001
Short name T67
Test name
Test status
Simulation time 2804654737 ps
CPU time 20.6 seconds
Started Jul 12 05:43:22 PM PDT 24
Finished Jul 12 05:43:44 PM PDT 24
Peak memory 197168 kb
Host smart-543f41e9-b6a1-41ed-88e9-f061be05ab01
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131427001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1131427001
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2065619459
Short name T522
Test name
Test status
Simulation time 92129018 ps
CPU time 0.75 seconds
Started Jul 12 05:43:25 PM PDT 24
Finished Jul 12 05:43:26 PM PDT 24
Peak memory 195588 kb
Host smart-30e3777a-10a4-4feb-9cc8-dff89dd3fe94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065619459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2065619459
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3021628154
Short name T133
Test name
Test status
Simulation time 101740660 ps
CPU time 1.36 seconds
Started Jul 12 05:43:21 PM PDT 24
Finished Jul 12 05:43:24 PM PDT 24
Peak memory 197384 kb
Host smart-f5123e3f-d4e9-4296-b29e-a8dd87cb8557
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021628154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3021628154
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.993479725
Short name T186
Test name
Test status
Simulation time 56312360 ps
CPU time 1.95 seconds
Started Jul 12 05:43:26 PM PDT 24
Finished Jul 12 05:43:29 PM PDT 24
Peak memory 198660 kb
Host smart-f9e75391-12df-42bc-8300-a1fa2440fbd5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993479725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.993479725
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.4172440846
Short name T672
Test name
Test status
Simulation time 738334272 ps
CPU time 3.47 seconds
Started Jul 12 05:43:25 PM PDT 24
Finished Jul 12 05:43:29 PM PDT 24
Peak memory 197816 kb
Host smart-cb690480-d0d6-4611-ad71-ee51d86fa567
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172440846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
4172440846
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1765762433
Short name T455
Test name
Test status
Simulation time 164094279 ps
CPU time 1.07 seconds
Started Jul 12 05:43:21 PM PDT 24
Finished Jul 12 05:43:24 PM PDT 24
Peak memory 197080 kb
Host smart-2af4aa5e-60d2-45f4-a847-b1be1e291f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765762433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1765762433
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.515863898
Short name T586
Test name
Test status
Simulation time 76007224 ps
CPU time 1.4 seconds
Started Jul 12 05:43:24 PM PDT 24
Finished Jul 12 05:43:27 PM PDT 24
Peak memory 197668 kb
Host smart-a5c91a90-7eef-42bd-b4f5-3657f2295425
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515863898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.515863898
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2620410823
Short name T647
Test name
Test status
Simulation time 65005677 ps
CPU time 2.83 seconds
Started Jul 12 05:43:21 PM PDT 24
Finished Jul 12 05:43:24 PM PDT 24
Peak memory 198548 kb
Host smart-5e14a896-5a75-4475-9c3c-2ee770d6088e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620410823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2620410823
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3917689080
Short name T39
Test name
Test status
Simulation time 212390602 ps
CPU time 0.76 seconds
Started Jul 12 05:43:23 PM PDT 24
Finished Jul 12 05:43:25 PM PDT 24
Peak memory 215092 kb
Host smart-a50f1815-cad9-4246-a1e3-31e918aa415c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917689080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3917689080
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3747177967
Short name T618
Test name
Test status
Simulation time 300962533 ps
CPU time 0.85 seconds
Started Jul 12 05:43:24 PM PDT 24
Finished Jul 12 05:43:26 PM PDT 24
Peak memory 195980 kb
Host smart-abda7b1b-2f56-47e4-bdcc-eb3bc06d60a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747177967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3747177967
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.349171930
Short name T143
Test name
Test status
Simulation time 42084359 ps
CPU time 1.21 seconds
Started Jul 12 05:43:22 PM PDT 24
Finished Jul 12 05:43:24 PM PDT 24
Peak memory 197248 kb
Host smart-2dd95dc0-b23e-4fe7-ab47-ac96370712dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349171930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.349171930
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.83670639
Short name T6
Test name
Test status
Simulation time 8793693541 ps
CPU time 102.14 seconds
Started Jul 12 05:43:22 PM PDT 24
Finished Jul 12 05:45:05 PM PDT 24
Peak memory 198796 kb
Host smart-82a6961b-a499-4567-8a43-2915ebe0b922
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83670639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpi
o_stress_all.83670639
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2076015902
Short name T426
Test name
Test status
Simulation time 13978204 ps
CPU time 0.58 seconds
Started Jul 12 05:45:12 PM PDT 24
Finished Jul 12 05:45:13 PM PDT 24
Peak memory 195332 kb
Host smart-66df905d-7291-4d3a-b6d1-89db10544cc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076015902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2076015902
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2007644765
Short name T532
Test name
Test status
Simulation time 197410351 ps
CPU time 1 seconds
Started Jul 12 05:45:05 PM PDT 24
Finished Jul 12 05:45:07 PM PDT 24
Peak memory 196648 kb
Host smart-fcc0d001-3f36-4a73-af51-a498f28c3181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007644765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2007644765
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1949876437
Short name T27
Test name
Test status
Simulation time 470517476 ps
CPU time 14.56 seconds
Started Jul 12 05:45:08 PM PDT 24
Finished Jul 12 05:45:23 PM PDT 24
Peak memory 196872 kb
Host smart-35bc8b04-e8dc-49eb-9a0f-f48746aa4385
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949876437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1949876437
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2348161410
Short name T305
Test name
Test status
Simulation time 36344758 ps
CPU time 0.63 seconds
Started Jul 12 05:45:07 PM PDT 24
Finished Jul 12 05:45:08 PM PDT 24
Peak memory 195052 kb
Host smart-fd5b7110-d75f-4f1f-b473-04984b1d248a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348161410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2348161410
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1242913860
Short name T468
Test name
Test status
Simulation time 200641003 ps
CPU time 1.05 seconds
Started Jul 12 05:45:02 PM PDT 24
Finished Jul 12 05:45:05 PM PDT 24
Peak memory 197444 kb
Host smart-c80a7dce-fde2-4240-aea4-58e8cc2294e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242913860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1242913860
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1690876546
Short name T360
Test name
Test status
Simulation time 291934563 ps
CPU time 2.22 seconds
Started Jul 12 05:45:07 PM PDT 24
Finished Jul 12 05:45:09 PM PDT 24
Peak memory 197012 kb
Host smart-ec69e018-aed8-437e-bab6-dbdd8a56d4a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690876546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1690876546
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2970101081
Short name T535
Test name
Test status
Simulation time 1471929077 ps
CPU time 1.71 seconds
Started Jul 12 05:45:08 PM PDT 24
Finished Jul 12 05:45:10 PM PDT 24
Peak memory 196752 kb
Host smart-cf3148f9-504d-4164-9f9c-8883940d0818
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970101081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2970101081
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1801797603
Short name T386
Test name
Test status
Simulation time 22563247 ps
CPU time 0.89 seconds
Started Jul 12 05:45:02 PM PDT 24
Finished Jul 12 05:45:05 PM PDT 24
Peak memory 197436 kb
Host smart-381ebc14-3180-4b66-aeb0-9ad0fc7c36b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801797603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1801797603
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.396386059
Short name T527
Test name
Test status
Simulation time 40296737 ps
CPU time 0.92 seconds
Started Jul 12 05:45:04 PM PDT 24
Finished Jul 12 05:45:06 PM PDT 24
Peak memory 196676 kb
Host smart-0e39eba6-5ffd-4572-9dbd-ebf10ad673bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396386059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.396386059
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2610410116
Short name T2
Test name
Test status
Simulation time 848896513 ps
CPU time 2.53 seconds
Started Jul 12 05:45:08 PM PDT 24
Finished Jul 12 05:45:12 PM PDT 24
Peak memory 197100 kb
Host smart-5e3bf70c-3ce2-4695-ab93-01a848c8a3b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610410116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2610410116
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.843363616
Short name T678
Test name
Test status
Simulation time 50011197 ps
CPU time 1.08 seconds
Started Jul 12 05:45:04 PM PDT 24
Finished Jul 12 05:45:06 PM PDT 24
Peak memory 196456 kb
Host smart-321e81a4-f3ad-4640-850a-26c0fcff69fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843363616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.843363616
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2151510692
Short name T363
Test name
Test status
Simulation time 185107247 ps
CPU time 1.3 seconds
Started Jul 12 05:45:02 PM PDT 24
Finished Jul 12 05:45:05 PM PDT 24
Peak memory 197496 kb
Host smart-ef287459-1389-435c-be5d-15170ebd5744
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151510692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2151510692
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3533088831
Short name T316
Test name
Test status
Simulation time 12620150809 ps
CPU time 63.65 seconds
Started Jul 12 05:45:08 PM PDT 24
Finished Jul 12 05:46:12 PM PDT 24
Peak memory 198792 kb
Host smart-00f78ea3-8f68-4d4e-ba05-953433b41ff6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533088831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3533088831
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3052386783
Short name T395
Test name
Test status
Simulation time 30173237 ps
CPU time 0.55 seconds
Started Jul 12 05:45:08 PM PDT 24
Finished Jul 12 05:45:09 PM PDT 24
Peak memory 195340 kb
Host smart-3f50b74b-8a0e-4e63-8502-4e7bd806531b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052386783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3052386783
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2133757239
Short name T379
Test name
Test status
Simulation time 94179060 ps
CPU time 0.89 seconds
Started Jul 12 05:45:09 PM PDT 24
Finished Jul 12 05:45:10 PM PDT 24
Peak memory 197160 kb
Host smart-3c4ae9d5-12bb-4dbd-9dbf-a0b827e2ab92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133757239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2133757239
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.842830994
Short name T503
Test name
Test status
Simulation time 908453772 ps
CPU time 27.36 seconds
Started Jul 12 05:45:07 PM PDT 24
Finished Jul 12 05:45:35 PM PDT 24
Peak memory 197416 kb
Host smart-3e0dc44f-27ea-4a6a-b15a-70908b25585d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842830994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.842830994
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3941741776
Short name T670
Test name
Test status
Simulation time 497183467 ps
CPU time 0.97 seconds
Started Jul 12 05:45:07 PM PDT 24
Finished Jul 12 05:45:09 PM PDT 24
Peak memory 197296 kb
Host smart-220a430f-79a9-453b-b4a1-cbc026a12e22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941741776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3941741776
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3774711477
Short name T234
Test name
Test status
Simulation time 40676637 ps
CPU time 0.73 seconds
Started Jul 12 05:45:07 PM PDT 24
Finished Jul 12 05:45:08 PM PDT 24
Peak memory 195664 kb
Host smart-f2db7754-7710-4306-bf21-264b45310e7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774711477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3774711477
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1080138205
Short name T399
Test name
Test status
Simulation time 66117533 ps
CPU time 0.98 seconds
Started Jul 12 05:45:08 PM PDT 24
Finished Jul 12 05:45:10 PM PDT 24
Peak memory 196792 kb
Host smart-38c2455f-8b1e-4d27-959a-bd51718c563c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080138205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1080138205
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.827985415
Short name T188
Test name
Test status
Simulation time 160885435 ps
CPU time 2.51 seconds
Started Jul 12 05:46:04 PM PDT 24
Finished Jul 12 05:46:08 PM PDT 24
Peak memory 198704 kb
Host smart-787cc2c1-9552-4e4c-b955-fa72368c57d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827985415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
827985415
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.130255335
Short name T595
Test name
Test status
Simulation time 25962230 ps
CPU time 0.81 seconds
Started Jul 12 05:45:08 PM PDT 24
Finished Jul 12 05:45:10 PM PDT 24
Peak memory 196000 kb
Host smart-fd809fae-ff03-4474-9ff5-e44f2ec71284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130255335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.130255335
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1570017810
Short name T626
Test name
Test status
Simulation time 38671927 ps
CPU time 0.7 seconds
Started Jul 12 05:45:10 PM PDT 24
Finished Jul 12 05:45:12 PM PDT 24
Peak memory 194892 kb
Host smart-45adc272-39a9-46e6-911a-78f31df897aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570017810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1570017810
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2028060410
Short name T204
Test name
Test status
Simulation time 170194374 ps
CPU time 5.77 seconds
Started Jul 12 05:45:07 PM PDT 24
Finished Jul 12 05:45:13 PM PDT 24
Peak memory 198560 kb
Host smart-4e9b72f8-4777-4ebb-a551-81f610c58f62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028060410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2028060410
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.828207810
Short name T18
Test name
Test status
Simulation time 196644601 ps
CPU time 0.99 seconds
Started Jul 12 05:45:08 PM PDT 24
Finished Jul 12 05:45:09 PM PDT 24
Peak memory 196408 kb
Host smart-7b7654b9-2b2a-4a19-9b35-4cc74ddd9ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828207810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.828207810
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3759666902
Short name T112
Test name
Test status
Simulation time 77100390 ps
CPU time 0.85 seconds
Started Jul 12 05:45:09 PM PDT 24
Finished Jul 12 05:45:11 PM PDT 24
Peak memory 195852 kb
Host smart-68fdc00c-160c-4287-8d26-64a540a7b109
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759666902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3759666902
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1758490863
Short name T412
Test name
Test status
Simulation time 6106908737 ps
CPU time 151.63 seconds
Started Jul 12 05:45:10 PM PDT 24
Finished Jul 12 05:47:43 PM PDT 24
Peak memory 198836 kb
Host smart-afecab1f-af6d-4bd7-8f21-1a34326b3433
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758490863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1758490863
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.85943904
Short name T325
Test name
Test status
Simulation time 116783755 ps
CPU time 0.57 seconds
Started Jul 12 05:45:23 PM PDT 24
Finished Jul 12 05:45:25 PM PDT 24
Peak memory 194888 kb
Host smart-5bfad59d-0af6-4bb4-991d-456cc0acba2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85943904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.85943904
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2639410939
Short name T233
Test name
Test status
Simulation time 73383639 ps
CPU time 0.88 seconds
Started Jul 12 05:45:09 PM PDT 24
Finished Jul 12 05:45:12 PM PDT 24
Peak memory 197224 kb
Host smart-32c0ec45-e70f-4b28-8577-af18e89f8e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639410939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2639410939
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.673407851
Short name T338
Test name
Test status
Simulation time 793416106 ps
CPU time 23.61 seconds
Started Jul 12 05:45:08 PM PDT 24
Finished Jul 12 05:45:32 PM PDT 24
Peak memory 196944 kb
Host smart-3c7329a3-1628-4948-b57e-6040aae958db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673407851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stres
s.673407851
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.395748145
Short name T557
Test name
Test status
Simulation time 42573524 ps
CPU time 0.74 seconds
Started Jul 12 05:45:18 PM PDT 24
Finished Jul 12 05:45:19 PM PDT 24
Peak memory 197116 kb
Host smart-ee952937-f030-47da-a033-cff8ed98e767
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395748145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.395748145
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.440879609
Short name T433
Test name
Test status
Simulation time 70608399 ps
CPU time 1.01 seconds
Started Jul 12 05:45:06 PM PDT 24
Finished Jul 12 05:45:08 PM PDT 24
Peak memory 196676 kb
Host smart-fc08e080-96e3-4df9-b8c3-1da8d6474156
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440879609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.440879609
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2780954429
Short name T648
Test name
Test status
Simulation time 18380863 ps
CPU time 0.87 seconds
Started Jul 12 05:45:10 PM PDT 24
Finished Jul 12 05:45:12 PM PDT 24
Peak memory 196784 kb
Host smart-97ac57f2-29f5-42ec-aee5-89665e8407a6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780954429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2780954429
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1065864217
Short name T470
Test name
Test status
Simulation time 192462579 ps
CPU time 2.93 seconds
Started Jul 12 05:45:10 PM PDT 24
Finished Jul 12 05:45:14 PM PDT 24
Peak memory 198728 kb
Host smart-3df41cdf-c874-4b18-b634-604a06adb079
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065864217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1065864217
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3093425006
Short name T131
Test name
Test status
Simulation time 558584093 ps
CPU time 1.25 seconds
Started Jul 12 05:45:10 PM PDT 24
Finished Jul 12 05:45:13 PM PDT 24
Peak memory 196504 kb
Host smart-ea13829f-5931-470a-aa54-b04648426999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093425006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3093425006
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1170336687
Short name T362
Test name
Test status
Simulation time 67329552 ps
CPU time 0.9 seconds
Started Jul 12 05:45:09 PM PDT 24
Finished Jul 12 05:45:11 PM PDT 24
Peak memory 198196 kb
Host smart-d002b8ec-2f66-42c1-a025-d5a90b9b45fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170336687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1170336687
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1285243930
Short name T608
Test name
Test status
Simulation time 612538313 ps
CPU time 5.14 seconds
Started Jul 12 05:45:07 PM PDT 24
Finished Jul 12 05:45:13 PM PDT 24
Peak memory 198644 kb
Host smart-50366591-7745-4d0f-8042-dcc37b4b2e6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285243930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1285243930
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2129756538
Short name T342
Test name
Test status
Simulation time 67221720 ps
CPU time 1.17 seconds
Started Jul 12 05:45:08 PM PDT 24
Finished Jul 12 05:45:11 PM PDT 24
Peak memory 197188 kb
Host smart-a139c700-964a-4e03-9904-7ddfd2a02568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129756538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2129756538
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1098883915
Short name T169
Test name
Test status
Simulation time 167057697 ps
CPU time 1.22 seconds
Started Jul 12 05:45:09 PM PDT 24
Finished Jul 12 05:45:11 PM PDT 24
Peak memory 196208 kb
Host smart-8afeb2da-1265-4818-9713-d6729ef639e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098883915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1098883915
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3127737333
Short name T138
Test name
Test status
Simulation time 47281778582 ps
CPU time 159.97 seconds
Started Jul 12 05:45:17 PM PDT 24
Finished Jul 12 05:47:58 PM PDT 24
Peak memory 198712 kb
Host smart-9cb9c7be-f3bd-4a72-b210-29f9fb8ee8a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127737333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3127737333
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2677910031
Short name T80
Test name
Test status
Simulation time 146060414949 ps
CPU time 1781.31 seconds
Started Jul 12 05:45:16 PM PDT 24
Finished Jul 12 06:14:58 PM PDT 24
Peak memory 198812 kb
Host smart-f407d556-292c-4cb8-b3bf-8fbd43855fc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2677910031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2677910031
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.479945417
Short name T715
Test name
Test status
Simulation time 13532309 ps
CPU time 0.58 seconds
Started Jul 12 05:45:22 PM PDT 24
Finished Jul 12 05:45:24 PM PDT 24
Peak memory 195516 kb
Host smart-0e5ec840-0af8-49e5-ad14-8ce44110e6c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479945417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.479945417
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.852678356
Short name T646
Test name
Test status
Simulation time 393419181 ps
CPU time 0.88 seconds
Started Jul 12 05:45:21 PM PDT 24
Finished Jul 12 05:45:23 PM PDT 24
Peak memory 196236 kb
Host smart-3a95dc90-aa99-46f3-b574-b218634e706c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852678356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.852678356
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1752365071
Short name T323
Test name
Test status
Simulation time 651715882 ps
CPU time 22.59 seconds
Started Jul 12 05:45:20 PM PDT 24
Finished Jul 12 05:45:44 PM PDT 24
Peak memory 197600 kb
Host smart-5844f5ba-53d1-4c50-ae78-6fdb2dc2a2df
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752365071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1752365071
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.723046996
Short name T359
Test name
Test status
Simulation time 187022188 ps
CPU time 0.82 seconds
Started Jul 12 05:45:15 PM PDT 24
Finished Jul 12 05:45:16 PM PDT 24
Peak memory 196512 kb
Host smart-ca852554-6c09-45dd-a857-5218c7ead1a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723046996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.723046996
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2266180685
Short name T73
Test name
Test status
Simulation time 42517462 ps
CPU time 0.87 seconds
Started Jul 12 05:45:23 PM PDT 24
Finished Jul 12 05:45:25 PM PDT 24
Peak memory 197872 kb
Host smart-8e45eeaa-b374-4334-a1a8-8dee7b9cdd7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266180685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2266180685
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2771268047
Short name T137
Test name
Test status
Simulation time 24289198 ps
CPU time 1.03 seconds
Started Jul 12 05:45:15 PM PDT 24
Finished Jul 12 05:45:17 PM PDT 24
Peak memory 196868 kb
Host smart-76890c97-a98d-424e-ae5c-fd62721c252a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771268047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2771268047
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3033902707
Short name T321
Test name
Test status
Simulation time 35917400 ps
CPU time 1.16 seconds
Started Jul 12 05:45:17 PM PDT 24
Finished Jul 12 05:45:19 PM PDT 24
Peak memory 198020 kb
Host smart-5c24c9c5-bb64-4d4c-b6c6-84c75f7d6049
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033902707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3033902707
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2904250616
Short name T502
Test name
Test status
Simulation time 29338162 ps
CPU time 0.63 seconds
Started Jul 12 05:45:20 PM PDT 24
Finished Jul 12 05:45:22 PM PDT 24
Peak memory 194860 kb
Host smart-274cbb34-541b-44d1-b2f2-47b93ab4a561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904250616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2904250616
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.4113403055
Short name T129
Test name
Test status
Simulation time 158765111 ps
CPU time 1 seconds
Started Jul 12 05:45:15 PM PDT 24
Finished Jul 12 05:45:17 PM PDT 24
Peak memory 196556 kb
Host smart-8c390fe2-1c90-4e31-86da-d18fa1bf74d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113403055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.4113403055
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2534713687
Short name T408
Test name
Test status
Simulation time 136753614 ps
CPU time 3.21 seconds
Started Jul 12 05:45:15 PM PDT 24
Finished Jul 12 05:45:18 PM PDT 24
Peak memory 198600 kb
Host smart-2dbd3777-3570-4cf8-8195-eb4b138da66e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534713687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2534713687
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.4198353155
Short name T434
Test name
Test status
Simulation time 917316940 ps
CPU time 1.34 seconds
Started Jul 12 05:45:20 PM PDT 24
Finished Jul 12 05:45:22 PM PDT 24
Peak memory 196184 kb
Host smart-ab91be60-7509-49ae-9be5-923385cdf80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198353155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.4198353155
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1917786076
Short name T707
Test name
Test status
Simulation time 64451136 ps
CPU time 1.09 seconds
Started Jul 12 05:45:17 PM PDT 24
Finished Jul 12 05:45:18 PM PDT 24
Peak memory 197108 kb
Host smart-e0a4e836-2f17-4ef4-b8f5-517a11ac5a65
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917786076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1917786076
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.268011840
Short name T573
Test name
Test status
Simulation time 19746164500 ps
CPU time 25.49 seconds
Started Jul 12 05:45:16 PM PDT 24
Finished Jul 12 05:45:42 PM PDT 24
Peak memory 198792 kb
Host smart-d4602bc7-8b30-4d18-9476-cd80d2315620
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268011840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.268011840
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.1455357145
Short name T421
Test name
Test status
Simulation time 19109888768 ps
CPU time 573.24 seconds
Started Jul 12 05:45:17 PM PDT 24
Finished Jul 12 05:54:51 PM PDT 24
Peak memory 198788 kb
Host smart-b87a112e-54f9-4dfd-8445-016c781bcf96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1455357145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.1455357145
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2409882104
Short name T74
Test name
Test status
Simulation time 14729633 ps
CPU time 0.66 seconds
Started Jul 12 05:45:20 PM PDT 24
Finished Jul 12 05:45:21 PM PDT 24
Peak memory 195320 kb
Host smart-bc3ea09c-eba6-47a2-8796-8ff5abbf4427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409882104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2409882104
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3458877419
Short name T223
Test name
Test status
Simulation time 99005308 ps
CPU time 0.87 seconds
Started Jul 12 05:45:20 PM PDT 24
Finished Jul 12 05:45:21 PM PDT 24
Peak memory 197692 kb
Host smart-23565df6-b5ce-4730-801a-ac97c3232e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458877419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3458877419
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1473433671
Short name T701
Test name
Test status
Simulation time 287635472 ps
CPU time 10.25 seconds
Started Jul 12 05:45:17 PM PDT 24
Finished Jul 12 05:45:28 PM PDT 24
Peak memory 197648 kb
Host smart-413be0bf-801a-4609-b7cf-1eaa8d0ac223
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473433671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1473433671
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3210206384
Short name T460
Test name
Test status
Simulation time 82908074 ps
CPU time 1.12 seconds
Started Jul 12 05:45:17 PM PDT 24
Finished Jul 12 05:45:19 PM PDT 24
Peak memory 198696 kb
Host smart-8774be5e-3281-4d15-a609-1ac2e8bc3297
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210206384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3210206384
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.229196404
Short name T116
Test name
Test status
Simulation time 80139471 ps
CPU time 0.86 seconds
Started Jul 12 05:45:21 PM PDT 24
Finished Jul 12 05:45:23 PM PDT 24
Peak memory 196044 kb
Host smart-a0646383-9a04-4e25-86aa-8a647acd4d64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229196404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.229196404
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2420968269
Short name T222
Test name
Test status
Simulation time 312665831 ps
CPU time 3.48 seconds
Started Jul 12 05:45:16 PM PDT 24
Finished Jul 12 05:45:20 PM PDT 24
Peak memory 198656 kb
Host smart-98fe9412-acfa-4b7d-b547-dd52153ff2ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420968269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2420968269
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.819011275
Short name T318
Test name
Test status
Simulation time 89021116 ps
CPU time 2.13 seconds
Started Jul 12 05:45:16 PM PDT 24
Finished Jul 12 05:45:19 PM PDT 24
Peak memory 198564 kb
Host smart-6073dcc1-d2e4-4eb4-8945-2bfd2a264b3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819011275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
819011275
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1057936961
Short name T75
Test name
Test status
Simulation time 72635191 ps
CPU time 1.02 seconds
Started Jul 12 05:45:20 PM PDT 24
Finished Jul 12 05:45:21 PM PDT 24
Peak memory 196624 kb
Host smart-18865753-42f2-452e-b00c-c9f057464708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057936961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1057936961
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1789269743
Short name T501
Test name
Test status
Simulation time 42103379 ps
CPU time 1.13 seconds
Started Jul 12 05:45:22 PM PDT 24
Finished Jul 12 05:45:24 PM PDT 24
Peak memory 197668 kb
Host smart-481db1f8-599e-4ada-a2d2-831fa5149616
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789269743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1789269743
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3861053376
Short name T275
Test name
Test status
Simulation time 223968621 ps
CPU time 2.81 seconds
Started Jul 12 05:45:21 PM PDT 24
Finished Jul 12 05:45:25 PM PDT 24
Peak memory 198624 kb
Host smart-2c1c4b7d-3cbc-4911-b88c-122a948ecd09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861053376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3861053376
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3718512849
Short name T202
Test name
Test status
Simulation time 84753376 ps
CPU time 1.47 seconds
Started Jul 12 05:45:15 PM PDT 24
Finished Jul 12 05:45:18 PM PDT 24
Peak memory 197388 kb
Host smart-12401315-093a-44a4-9821-26cea88e8010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718512849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3718512849
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2414862485
Short name T569
Test name
Test status
Simulation time 121504567 ps
CPU time 0.96 seconds
Started Jul 12 05:45:25 PM PDT 24
Finished Jul 12 05:45:27 PM PDT 24
Peak memory 196720 kb
Host smart-f44c1def-6811-4e61-9a0b-9743f4189593
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414862485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2414862485
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.771400368
Short name T550
Test name
Test status
Simulation time 8158941249 ps
CPU time 51.48 seconds
Started Jul 12 05:45:14 PM PDT 24
Finished Jul 12 05:46:06 PM PDT 24
Peak memory 198776 kb
Host smart-2e57cb88-26fa-4e07-9e29-44dbe38ec16b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771400368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.771400368
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.430655466
Short name T642
Test name
Test status
Simulation time 15274652 ps
CPU time 0.58 seconds
Started Jul 12 05:45:22 PM PDT 24
Finished Jul 12 05:45:23 PM PDT 24
Peak memory 194652 kb
Host smart-f75338db-3414-4859-aa46-761142eb1f90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430655466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.430655466
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1024742891
Short name T489
Test name
Test status
Simulation time 104451394 ps
CPU time 0.99 seconds
Started Jul 12 05:45:24 PM PDT 24
Finished Jul 12 05:45:26 PM PDT 24
Peak memory 196596 kb
Host smart-a7532bc3-1f56-4c03-9bf5-09bdc7fbf5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024742891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1024742891
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2193619478
Short name T659
Test name
Test status
Simulation time 1169982748 ps
CPU time 19.84 seconds
Started Jul 12 05:45:20 PM PDT 24
Finished Jul 12 05:45:42 PM PDT 24
Peak memory 197128 kb
Host smart-52108d08-41a2-4de7-a244-afcfda80f2e8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193619478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2193619478
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2602864532
Short name T478
Test name
Test status
Simulation time 79489252 ps
CPU time 0.64 seconds
Started Jul 12 05:45:25 PM PDT 24
Finished Jul 12 05:45:26 PM PDT 24
Peak memory 195852 kb
Host smart-ced8ba31-f61c-4e46-a769-1bef71019f07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602864532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2602864532
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.902424999
Short name T482
Test name
Test status
Simulation time 85493799 ps
CPU time 1.46 seconds
Started Jul 12 05:45:17 PM PDT 24
Finished Jul 12 05:45:19 PM PDT 24
Peak memory 197204 kb
Host smart-15660ed6-3618-4722-95b3-1515ae31d0c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902424999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.902424999
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1231645080
Short name T229
Test name
Test status
Simulation time 239968660 ps
CPU time 2.61 seconds
Started Jul 12 05:45:21 PM PDT 24
Finished Jul 12 05:45:24 PM PDT 24
Peak memory 197336 kb
Host smart-67bcc2fc-ff06-463e-b284-d89842720774
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231645080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1231645080
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.4174859613
Short name T253
Test name
Test status
Simulation time 182370373 ps
CPU time 1.38 seconds
Started Jul 12 05:45:19 PM PDT 24
Finished Jul 12 05:45:21 PM PDT 24
Peak memory 196640 kb
Host smart-ce369de5-30f6-49c1-bbbb-e7a3fab8815f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174859613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.4174859613
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1162189399
Short name T612
Test name
Test status
Simulation time 59234631 ps
CPU time 1.29 seconds
Started Jul 12 05:45:24 PM PDT 24
Finished Jul 12 05:45:26 PM PDT 24
Peak memory 198640 kb
Host smart-5417cd76-9d48-4fa4-8ea1-f5ee835b5e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162189399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1162189399
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.15199824
Short name T463
Test name
Test status
Simulation time 287133316 ps
CPU time 0.96 seconds
Started Jul 12 05:45:21 PM PDT 24
Finished Jul 12 05:45:23 PM PDT 24
Peak memory 196548 kb
Host smart-a6739cc0-c78b-445e-ad21-bfb6082e9145
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15199824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup_
pulldown.15199824
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1629912720
Short name T698
Test name
Test status
Simulation time 4490008177 ps
CPU time 3.7 seconds
Started Jul 12 05:45:22 PM PDT 24
Finished Jul 12 05:45:27 PM PDT 24
Peak memory 198564 kb
Host smart-17c86230-106c-4d61-8f63-2a56ba8aa3f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629912720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1629912720
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1078364041
Short name T385
Test name
Test status
Simulation time 65179134 ps
CPU time 1.14 seconds
Started Jul 12 05:45:18 PM PDT 24
Finished Jul 12 05:45:20 PM PDT 24
Peak memory 196992 kb
Host smart-21347e39-d700-44b0-9c9a-1b7c2ca32763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078364041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1078364041
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2030613771
Short name T255
Test name
Test status
Simulation time 106477630 ps
CPU time 0.75 seconds
Started Jul 12 05:45:17 PM PDT 24
Finished Jul 12 05:45:18 PM PDT 24
Peak memory 195784 kb
Host smart-a236976c-07bc-42b6-bc77-976d73fe3e01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030613771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2030613771
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2563542327
Short name T435
Test name
Test status
Simulation time 40699947123 ps
CPU time 101.09 seconds
Started Jul 12 05:45:29 PM PDT 24
Finished Jul 12 05:47:11 PM PDT 24
Peak memory 198756 kb
Host smart-97bda5d1-c746-4236-b520-f001a9263cb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563542327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2563542327
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.796713308
Short name T59
Test name
Test status
Simulation time 295611634086 ps
CPU time 1819.45 seconds
Started Jul 12 05:45:29 PM PDT 24
Finished Jul 12 06:15:51 PM PDT 24
Peak memory 198936 kb
Host smart-21339bf0-1454-4af9-9334-a1e965e01146
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=796713308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.796713308
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.3108853246
Short name T285
Test name
Test status
Simulation time 13077664 ps
CPU time 0.57 seconds
Started Jul 12 05:45:22 PM PDT 24
Finished Jul 12 05:45:23 PM PDT 24
Peak memory 194660 kb
Host smart-db597e33-d67a-4c96-a183-2b7aee9b438f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108853246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3108853246
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2037965912
Short name T566
Test name
Test status
Simulation time 116315907 ps
CPU time 0.69 seconds
Started Jul 12 05:45:26 PM PDT 24
Finished Jul 12 05:45:27 PM PDT 24
Peak memory 194636 kb
Host smart-e79285a2-8d1e-4ec4-8946-3ec2dc0e11e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037965912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2037965912
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2421200086
Short name T320
Test name
Test status
Simulation time 753413937 ps
CPU time 18.45 seconds
Started Jul 12 05:45:26 PM PDT 24
Finished Jul 12 05:45:45 PM PDT 24
Peak memory 197688 kb
Host smart-152c81e1-36a8-4016-9f00-6d114a6158df
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421200086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2421200086
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.1710161384
Short name T673
Test name
Test status
Simulation time 30944033 ps
CPU time 0.76 seconds
Started Jul 12 05:45:21 PM PDT 24
Finished Jul 12 05:45:23 PM PDT 24
Peak memory 197116 kb
Host smart-f5e95007-1ae0-45e3-8bd9-48925652a81d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710161384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.1710161384
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.926826289
Short name T487
Test name
Test status
Simulation time 142573361 ps
CPU time 1.04 seconds
Started Jul 12 05:45:27 PM PDT 24
Finished Jul 12 05:45:29 PM PDT 24
Peak memory 197312 kb
Host smart-1ae0b8d3-47c4-4ffd-9289-c1554645d080
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926826289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.926826289
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1508480672
Short name T149
Test name
Test status
Simulation time 309228964 ps
CPU time 2.96 seconds
Started Jul 12 05:45:24 PM PDT 24
Finished Jul 12 05:45:28 PM PDT 24
Peak memory 198544 kb
Host smart-353e1fe3-17cd-4376-a7a7-e7747befab7c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508480672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1508480672
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1534665678
Short name T548
Test name
Test status
Simulation time 273057341 ps
CPU time 2.23 seconds
Started Jul 12 05:45:30 PM PDT 24
Finished Jul 12 05:45:34 PM PDT 24
Peak memory 197884 kb
Host smart-5dee156e-cdef-4e78-8352-7a4e2c85a596
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534665678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1534665678
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3185539550
Short name T296
Test name
Test status
Simulation time 34602093 ps
CPU time 1.2 seconds
Started Jul 12 05:45:28 PM PDT 24
Finished Jul 12 05:45:31 PM PDT 24
Peak memory 197856 kb
Host smart-ed7d6c15-856d-4b57-8f8a-a47b900c96c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185539550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3185539550
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.868415994
Short name T142
Test name
Test status
Simulation time 96773902 ps
CPU time 0.85 seconds
Started Jul 12 05:45:21 PM PDT 24
Finished Jul 12 05:45:23 PM PDT 24
Peak memory 197792 kb
Host smart-ae2b7478-b4bd-41c3-9fba-5208e14a7fd1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868415994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup
_pulldown.868415994
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.841163138
Short name T539
Test name
Test status
Simulation time 58093115 ps
CPU time 2.21 seconds
Started Jul 12 05:45:25 PM PDT 24
Finished Jul 12 05:45:28 PM PDT 24
Peak memory 198896 kb
Host smart-a6919bac-7886-43e5-9f2d-499acd9cfdb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841163138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran
dom_long_reg_writes_reg_reads.841163138
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2286612471
Short name T594
Test name
Test status
Simulation time 126787723 ps
CPU time 0.93 seconds
Started Jul 12 05:45:26 PM PDT 24
Finished Jul 12 05:45:28 PM PDT 24
Peak memory 195916 kb
Host smart-fb109b4c-d0d7-41c0-a7d9-584e41e1c343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286612471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2286612471
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.580238493
Short name T249
Test name
Test status
Simulation time 436553141 ps
CPU time 1.22 seconds
Started Jul 12 05:45:29 PM PDT 24
Finished Jul 12 05:45:32 PM PDT 24
Peak memory 196232 kb
Host smart-5ef15918-9b56-43e2-b6cd-96947c4982c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580238493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.580238493
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1889135385
Short name T514
Test name
Test status
Simulation time 13561367786 ps
CPU time 143.3 seconds
Started Jul 12 05:45:23 PM PDT 24
Finished Jul 12 05:47:48 PM PDT 24
Peak memory 198744 kb
Host smart-71ea7076-5760-41ab-9c79-9b873ef37891
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889135385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1889135385
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2023368102
Short name T237
Test name
Test status
Simulation time 14554708 ps
CPU time 0.56 seconds
Started Jul 12 05:45:22 PM PDT 24
Finished Jul 12 05:45:24 PM PDT 24
Peak memory 194480 kb
Host smart-0a876964-4cce-4b41-9330-1772ede1fb73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023368102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2023368102
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3448669384
Short name T552
Test name
Test status
Simulation time 161816689 ps
CPU time 0.89 seconds
Started Jul 12 05:45:27 PM PDT 24
Finished Jul 12 05:45:29 PM PDT 24
Peak memory 198072 kb
Host smart-4a91def6-8e61-48b0-a2e7-0c7e4102745b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448669384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3448669384
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3028405302
Short name T419
Test name
Test status
Simulation time 646585898 ps
CPU time 8.77 seconds
Started Jul 12 05:45:28 PM PDT 24
Finished Jul 12 05:45:39 PM PDT 24
Peak memory 197292 kb
Host smart-dac9ed1a-9a20-4852-8f62-255c5f09e774
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028405302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3028405302
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3722388683
Short name T545
Test name
Test status
Simulation time 86375219 ps
CPU time 1.01 seconds
Started Jul 12 05:45:23 PM PDT 24
Finished Jul 12 05:45:25 PM PDT 24
Peak memory 196792 kb
Host smart-5b49503c-b681-463d-ad1f-138e3ae7e1d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722388683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3722388683
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1677149478
Short name T324
Test name
Test status
Simulation time 48162658 ps
CPU time 1.43 seconds
Started Jul 12 05:45:55 PM PDT 24
Finished Jul 12 05:45:58 PM PDT 24
Peak memory 196484 kb
Host smart-41850f13-2303-4a9b-b6a0-dca3b62a61cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677149478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1677149478
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.4149811936
Short name T256
Test name
Test status
Simulation time 76632744 ps
CPU time 1.08 seconds
Started Jul 12 05:45:22 PM PDT 24
Finished Jul 12 05:45:24 PM PDT 24
Peak memory 197300 kb
Host smart-cc0908d7-1f88-4ab5-9b37-ff4464853a7d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149811936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.4149811936
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2915160952
Short name T197
Test name
Test status
Simulation time 128585122 ps
CPU time 1.75 seconds
Started Jul 12 05:45:28 PM PDT 24
Finished Jul 12 05:45:32 PM PDT 24
Peak memory 197440 kb
Host smart-18d7c45f-65c2-4dec-be6c-4d22c47445b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915160952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2915160952
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2565982886
Short name T444
Test name
Test status
Simulation time 64439030 ps
CPU time 0.78 seconds
Started Jul 12 05:45:21 PM PDT 24
Finished Jul 12 05:45:23 PM PDT 24
Peak memory 197228 kb
Host smart-1f2ba2e1-f95d-441d-a667-a2a32ac635c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565982886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2565982886
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3395584913
Short name T280
Test name
Test status
Simulation time 96082999 ps
CPU time 1.08 seconds
Started Jul 12 05:45:28 PM PDT 24
Finished Jul 12 05:45:30 PM PDT 24
Peak memory 196820 kb
Host smart-8f0a34bf-5e4e-4214-9e03-2840d647c10d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395584913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3395584913
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2834953695
Short name T477
Test name
Test status
Simulation time 50006499 ps
CPU time 1.24 seconds
Started Jul 12 05:45:22 PM PDT 24
Finished Jul 12 05:45:24 PM PDT 24
Peak memory 197324 kb
Host smart-d7a3740e-a261-4af2-bfdf-5f53af07bcb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834953695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2834953695
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2933545910
Short name T66
Test name
Test status
Simulation time 28523658 ps
CPU time 0.89 seconds
Started Jul 12 05:45:28 PM PDT 24
Finished Jul 12 05:45:30 PM PDT 24
Peak memory 195472 kb
Host smart-bace27f0-8dd0-42e9-9543-aeb4b58181c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933545910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2933545910
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.4265960212
Short name T580
Test name
Test status
Simulation time 111927807 ps
CPU time 0.93 seconds
Started Jul 12 05:45:25 PM PDT 24
Finished Jul 12 05:45:27 PM PDT 24
Peak memory 197648 kb
Host smart-303b60c0-12bb-48ff-9cb4-3e1646422b2d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265960212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.4265960212
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3360681200
Short name T368
Test name
Test status
Simulation time 13599121800 ps
CPU time 194.88 seconds
Started Jul 12 05:45:23 PM PDT 24
Finished Jul 12 05:48:39 PM PDT 24
Peak memory 198776 kb
Host smart-86ddda10-0207-440e-a54f-d87cf09aa200
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360681200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3360681200
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2453400799
Short name T246
Test name
Test status
Simulation time 53315185 ps
CPU time 0.58 seconds
Started Jul 12 05:45:25 PM PDT 24
Finished Jul 12 05:45:26 PM PDT 24
Peak memory 194632 kb
Host smart-fb0f73e8-39cb-428f-a4d7-df6d42461912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453400799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2453400799
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2877810419
Short name T520
Test name
Test status
Simulation time 18458615 ps
CPU time 0.65 seconds
Started Jul 12 05:45:23 PM PDT 24
Finished Jul 12 05:45:25 PM PDT 24
Peak memory 194640 kb
Host smart-019f646f-f247-4c0e-ad5d-ef6996d1dc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877810419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2877810419
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.213030879
Short name T633
Test name
Test status
Simulation time 255513462 ps
CPU time 6.56 seconds
Started Jul 12 05:45:28 PM PDT 24
Finished Jul 12 05:45:36 PM PDT 24
Peak memory 198624 kb
Host smart-15bec21e-a81b-41d5-b77a-f9f35b8ffe77
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213030879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.213030879
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.693875552
Short name T125
Test name
Test status
Simulation time 62391309 ps
CPU time 1.03 seconds
Started Jul 12 05:45:30 PM PDT 24
Finished Jul 12 05:45:32 PM PDT 24
Peak memory 197232 kb
Host smart-3dac6bc0-499a-47c9-95c8-701156167f2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693875552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.693875552
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3595049333
Short name T230
Test name
Test status
Simulation time 81144345 ps
CPU time 1.36 seconds
Started Jul 12 05:45:29 PM PDT 24
Finished Jul 12 05:45:32 PM PDT 24
Peak memory 197196 kb
Host smart-ba27e120-d88b-47cf-82d2-6bd1f8ab6e03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595049333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3595049333
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1950519097
Short name T611
Test name
Test status
Simulation time 25394233 ps
CPU time 1.07 seconds
Started Jul 12 05:45:28 PM PDT 24
Finished Jul 12 05:45:31 PM PDT 24
Peak memory 197628 kb
Host smart-e87bed9d-75f7-41c3-ba58-4d32ba6287ed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950519097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1950519097
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2203222894
Short name T224
Test name
Test status
Simulation time 556084939 ps
CPU time 2.7 seconds
Started Jul 12 05:45:28 PM PDT 24
Finished Jul 12 05:45:32 PM PDT 24
Peak memory 196240 kb
Host smart-8d6e156f-c22b-4c32-b10d-8cb2f64bb71c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203222894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2203222894
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2652829405
Short name T456
Test name
Test status
Simulation time 33608234 ps
CPU time 1.14 seconds
Started Jul 12 05:45:24 PM PDT 24
Finished Jul 12 05:45:26 PM PDT 24
Peak memory 196696 kb
Host smart-985030c4-7da3-4b9d-ba8b-f66f0f36e5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652829405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2652829405
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2478403403
Short name T443
Test name
Test status
Simulation time 66021070 ps
CPU time 1.42 seconds
Started Jul 12 05:45:27 PM PDT 24
Finished Jul 12 05:45:29 PM PDT 24
Peak memory 197692 kb
Host smart-be65ac93-f8a1-4871-b7ff-ff01d4ce50d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478403403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2478403403
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3841948423
Short name T254
Test name
Test status
Simulation time 247853315 ps
CPU time 2.8 seconds
Started Jul 12 05:45:28 PM PDT 24
Finished Jul 12 05:45:32 PM PDT 24
Peak memory 198572 kb
Host smart-ffc96a42-5dc1-4b9a-bce2-2724ca35ebe4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841948423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3841948423
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1829312334
Short name T51
Test name
Test status
Simulation time 312042177 ps
CPU time 1.47 seconds
Started Jul 12 05:45:26 PM PDT 24
Finished Jul 12 05:45:29 PM PDT 24
Peak memory 196180 kb
Host smart-bc618944-0381-47f1-b02a-404e7f4b5e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829312334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1829312334
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2113799912
Short name T652
Test name
Test status
Simulation time 53069478 ps
CPU time 0.78 seconds
Started Jul 12 05:45:28 PM PDT 24
Finished Jul 12 05:45:30 PM PDT 24
Peak memory 195940 kb
Host smart-0cdb2747-336c-4704-b8a9-b76828038fba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113799912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2113799912
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2716820136
Short name T479
Test name
Test status
Simulation time 3401940297 ps
CPU time 39.82 seconds
Started Jul 12 05:45:27 PM PDT 24
Finished Jul 12 05:46:07 PM PDT 24
Peak memory 198680 kb
Host smart-9fad8a05-b64e-4869-804c-ed50c51cc240
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716820136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2716820136
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3433902335
Short name T42
Test name
Test status
Simulation time 46748954 ps
CPU time 0.58 seconds
Started Jul 12 05:45:33 PM PDT 24
Finished Jul 12 05:45:35 PM PDT 24
Peak memory 194540 kb
Host smart-20307f17-4fa1-440a-9974-a64147015a5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433902335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3433902335
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1416139366
Short name T576
Test name
Test status
Simulation time 16379718 ps
CPU time 0.62 seconds
Started Jul 12 05:45:32 PM PDT 24
Finished Jul 12 05:45:34 PM PDT 24
Peak memory 194576 kb
Host smart-de0a876d-399d-4b2c-b5fb-d23230c4bd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416139366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1416139366
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1045965566
Short name T474
Test name
Test status
Simulation time 487903731 ps
CPU time 14.16 seconds
Started Jul 12 05:45:33 PM PDT 24
Finished Jul 12 05:45:50 PM PDT 24
Peak memory 197564 kb
Host smart-caa0c824-6c08-4293-b0e2-fe8e0b7dac9f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045965566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1045965566
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3446734604
Short name T657
Test name
Test status
Simulation time 341656383 ps
CPU time 0.95 seconds
Started Jul 12 05:45:29 PM PDT 24
Finished Jul 12 05:45:32 PM PDT 24
Peak memory 197804 kb
Host smart-9fe89040-8cec-41b1-b2f1-21668cfb81bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446734604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3446734604
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3657796932
Short name T641
Test name
Test status
Simulation time 50647093 ps
CPU time 1.05 seconds
Started Jul 12 05:45:33 PM PDT 24
Finished Jul 12 05:45:36 PM PDT 24
Peak memory 196764 kb
Host smart-cd02b3ad-013e-4c89-8a54-376b73546062
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657796932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3657796932
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1849077979
Short name T287
Test name
Test status
Simulation time 95546335 ps
CPU time 3.96 seconds
Started Jul 12 05:45:30 PM PDT 24
Finished Jul 12 05:45:36 PM PDT 24
Peak memory 198736 kb
Host smart-97bfe1cd-fd4e-447c-b67e-6bbdae81966c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849077979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1849077979
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.4254232406
Short name T376
Test name
Test status
Simulation time 298089308 ps
CPU time 2.87 seconds
Started Jul 12 05:45:30 PM PDT 24
Finished Jul 12 05:45:35 PM PDT 24
Peak memory 196480 kb
Host smart-506fbc17-5c3c-4458-8972-dfacb73563f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254232406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.4254232406
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1750532398
Short name T12
Test name
Test status
Simulation time 205230606 ps
CPU time 1.2 seconds
Started Jul 12 05:45:30 PM PDT 24
Finished Jul 12 05:45:33 PM PDT 24
Peak memory 196500 kb
Host smart-99fdd38f-d24b-4dcf-9c75-bfacf9a0920b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750532398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1750532398
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1337057621
Short name T180
Test name
Test status
Simulation time 55180329 ps
CPU time 0.74 seconds
Started Jul 12 05:45:31 PM PDT 24
Finished Jul 12 05:45:33 PM PDT 24
Peak memory 196104 kb
Host smart-b8bed405-a016-4f23-9bd4-e110946e3e31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337057621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1337057621
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.199713897
Short name T79
Test name
Test status
Simulation time 428608130 ps
CPU time 4.76 seconds
Started Jul 12 05:45:29 PM PDT 24
Finished Jul 12 05:45:36 PM PDT 24
Peak memory 198640 kb
Host smart-5c23e90c-db78-43fe-96e7-765b63e9d777
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199713897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.199713897
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3819518983
Short name T179
Test name
Test status
Simulation time 27114673 ps
CPU time 0.89 seconds
Started Jul 12 05:45:31 PM PDT 24
Finished Jul 12 05:45:33 PM PDT 24
Peak memory 196312 kb
Host smart-02203547-92ac-4663-8aed-15e1a76f22a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819518983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3819518983
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2741120887
Short name T72
Test name
Test status
Simulation time 215454210 ps
CPU time 1.21 seconds
Started Jul 12 05:45:32 PM PDT 24
Finished Jul 12 05:45:35 PM PDT 24
Peak memory 198568 kb
Host smart-4ac11c2e-67e8-40e2-bf8a-19256f346978
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741120887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2741120887
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1026363807
Short name T7
Test name
Test status
Simulation time 17661004937 ps
CPU time 111.13 seconds
Started Jul 12 05:45:34 PM PDT 24
Finished Jul 12 05:47:27 PM PDT 24
Peak memory 198716 kb
Host smart-5af88703-4a6e-4613-a30c-e1d80f626384
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026363807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1026363807
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.3334336227
Short name T31
Test name
Test status
Simulation time 78541836511 ps
CPU time 1349.99 seconds
Started Jul 12 05:45:31 PM PDT 24
Finished Jul 12 06:08:03 PM PDT 24
Peak memory 198892 kb
Host smart-e315dedf-7f32-4677-9581-fc5f250261d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3334336227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.3334336227
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.707841454
Short name T330
Test name
Test status
Simulation time 74121348 ps
CPU time 0.57 seconds
Started Jul 12 05:43:28 PM PDT 24
Finished Jul 12 05:43:30 PM PDT 24
Peak memory 194668 kb
Host smart-7bd8e8a8-d302-4f81-97a0-c90743d4f8b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707841454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.707841454
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1192275447
Short name T706
Test name
Test status
Simulation time 56973218 ps
CPU time 0.64 seconds
Started Jul 12 05:43:25 PM PDT 24
Finished Jul 12 05:43:26 PM PDT 24
Peak memory 195348 kb
Host smart-c3a56f74-a964-4667-bbaa-6d3fe31e1d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192275447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1192275447
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1146294330
Short name T327
Test name
Test status
Simulation time 614578596 ps
CPU time 22.23 seconds
Started Jul 12 05:43:29 PM PDT 24
Finished Jul 12 05:43:52 PM PDT 24
Peak memory 198632 kb
Host smart-598b368e-5107-4a62-8ffe-6d87d1650031
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146294330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1146294330
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3250493665
Short name T671
Test name
Test status
Simulation time 162508357 ps
CPU time 0.82 seconds
Started Jul 12 05:43:33 PM PDT 24
Finished Jul 12 05:43:35 PM PDT 24
Peak memory 196460 kb
Host smart-57e7c01e-0173-4b63-afab-8dfbbeb9a131
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250493665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3250493665
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2151882032
Short name T270
Test name
Test status
Simulation time 487829314 ps
CPU time 1.31 seconds
Started Jul 12 05:43:30 PM PDT 24
Finished Jul 12 05:43:31 PM PDT 24
Peak memory 198676 kb
Host smart-b76c3736-770d-4714-9491-a777d15a7101
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151882032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2151882032
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2816589214
Short name T599
Test name
Test status
Simulation time 69183719 ps
CPU time 2.72 seconds
Started Jul 12 05:43:36 PM PDT 24
Finished Jul 12 05:43:39 PM PDT 24
Peak memory 198712 kb
Host smart-0dc11722-db7a-437f-8c2c-9b07ec53d26b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816589214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2816589214
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3048496401
Short name T173
Test name
Test status
Simulation time 72396731 ps
CPU time 1.6 seconds
Started Jul 12 05:43:33 PM PDT 24
Finished Jul 12 05:43:36 PM PDT 24
Peak memory 197028 kb
Host smart-5dc1619b-5a61-480a-80d9-1b2c08339c94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048496401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3048496401
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2256946968
Short name T21
Test name
Test status
Simulation time 38481122 ps
CPU time 0.58 seconds
Started Jul 12 05:43:23 PM PDT 24
Finished Jul 12 05:43:25 PM PDT 24
Peak memory 194840 kb
Host smart-25676fbe-71df-4db2-9c1f-754fa8d2fbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256946968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2256946968
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3495242621
Short name T556
Test name
Test status
Simulation time 57027052 ps
CPU time 0.69 seconds
Started Jul 12 05:43:23 PM PDT 24
Finished Jul 12 05:43:25 PM PDT 24
Peak memory 195552 kb
Host smart-806716e0-4e6d-4bfa-b6c6-441e503746cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495242621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3495242621
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.4064938833
Short name T130
Test name
Test status
Simulation time 303022531 ps
CPU time 2.08 seconds
Started Jul 12 05:43:33 PM PDT 24
Finished Jul 12 05:43:36 PM PDT 24
Peak memory 198608 kb
Host smart-47f3a1d6-27b8-4191-a135-24f897220a12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064938833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.4064938833
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1311558117
Short name T382
Test name
Test status
Simulation time 74206753 ps
CPU time 1.22 seconds
Started Jul 12 05:43:23 PM PDT 24
Finished Jul 12 05:43:25 PM PDT 24
Peak memory 196276 kb
Host smart-0dcaff5b-19c7-4479-90b0-b7ab7f42f072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311558117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1311558117
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2830690962
Short name T601
Test name
Test status
Simulation time 95874140 ps
CPU time 1.43 seconds
Started Jul 12 05:43:22 PM PDT 24
Finished Jul 12 05:43:25 PM PDT 24
Peak memory 196152 kb
Host smart-6014b1e9-5278-401f-85cf-ca9a1cadc62c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830690962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2830690962
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.983489794
Short name T269
Test name
Test status
Simulation time 75393254997 ps
CPU time 97.08 seconds
Started Jul 12 05:43:30 PM PDT 24
Finished Jul 12 05:45:08 PM PDT 24
Peak memory 198820 kb
Host smart-5d981a76-1d9d-4e64-9ae8-f8c4b51997e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983489794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gp
io_stress_all.983489794
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2453172661
Short name T437
Test name
Test status
Simulation time 18899913 ps
CPU time 0.57 seconds
Started Jul 12 05:43:31 PM PDT 24
Finished Jul 12 05:43:33 PM PDT 24
Peak memory 194624 kb
Host smart-803a55f7-000c-4648-b343-7b3619954cd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453172661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2453172661
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3604169617
Short name T354
Test name
Test status
Simulation time 61047934 ps
CPU time 0.84 seconds
Started Jul 12 05:43:30 PM PDT 24
Finished Jul 12 05:43:32 PM PDT 24
Peak memory 197124 kb
Host smart-bf53fb94-10fe-41d6-9b29-932b3a036a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604169617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3604169617
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.815970634
Short name T351
Test name
Test status
Simulation time 325094264 ps
CPU time 12.45 seconds
Started Jul 12 05:43:30 PM PDT 24
Finished Jul 12 05:43:43 PM PDT 24
Peak memory 197484 kb
Host smart-0874b188-bb14-4478-bd2e-6e1568b4400b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815970634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.815970634
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3348538773
Short name T615
Test name
Test status
Simulation time 69281051 ps
CPU time 0.71 seconds
Started Jul 12 05:43:33 PM PDT 24
Finished Jul 12 05:43:35 PM PDT 24
Peak memory 195356 kb
Host smart-945662be-26a1-452e-a571-75e8db69ce00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348538773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3348538773
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.520850855
Short name T563
Test name
Test status
Simulation time 63522962 ps
CPU time 1.16 seconds
Started Jul 12 05:43:31 PM PDT 24
Finished Jul 12 05:43:34 PM PDT 24
Peak memory 196776 kb
Host smart-57adf614-5571-44a9-a6e9-458510aab458
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520850855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.520850855
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2743228221
Short name T688
Test name
Test status
Simulation time 280786282 ps
CPU time 2.85 seconds
Started Jul 12 05:43:33 PM PDT 24
Finished Jul 12 05:43:37 PM PDT 24
Peak memory 198668 kb
Host smart-9d34b292-0cfe-4663-b941-3620b82cd6cc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743228221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2743228221
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.4246184931
Short name T259
Test name
Test status
Simulation time 85830696 ps
CPU time 1.15 seconds
Started Jul 12 05:43:31 PM PDT 24
Finished Jul 12 05:43:33 PM PDT 24
Peak memory 196124 kb
Host smart-655b2907-5e16-48c5-91c1-a572d776ccb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246184931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
4246184931
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2835460051
Short name T540
Test name
Test status
Simulation time 28725152 ps
CPU time 0.77 seconds
Started Jul 12 05:43:32 PM PDT 24
Finished Jul 12 05:43:34 PM PDT 24
Peak memory 196056 kb
Host smart-eb7b1ddc-fab4-4b61-b516-2ef7d9acf19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835460051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2835460051
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.49883636
Short name T298
Test name
Test status
Simulation time 55950873 ps
CPU time 0.76 seconds
Started Jul 12 05:43:32 PM PDT 24
Finished Jul 12 05:43:34 PM PDT 24
Peak memory 196024 kb
Host smart-7faeba66-ad73-433b-9e71-77620a4a1e44
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49883636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_p
ulldown.49883636
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1674323254
Short name T284
Test name
Test status
Simulation time 228720249 ps
CPU time 1.83 seconds
Started Jul 12 05:43:29 PM PDT 24
Finished Jul 12 05:43:31 PM PDT 24
Peak memory 198668 kb
Host smart-6f1772e7-796f-414a-bfec-b4e386501242
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674323254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1674323254
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1030803647
Short name T689
Test name
Test status
Simulation time 36496346 ps
CPU time 1.05 seconds
Started Jul 12 05:43:33 PM PDT 24
Finished Jul 12 05:43:35 PM PDT 24
Peak memory 197212 kb
Host smart-4f191b12-e011-41ad-a75e-e798c2d11a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030803647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1030803647
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.494925875
Short name T577
Test name
Test status
Simulation time 65253579 ps
CPU time 1.15 seconds
Started Jul 12 05:43:29 PM PDT 24
Finished Jul 12 05:43:31 PM PDT 24
Peak memory 196472 kb
Host smart-4945b2f7-1561-4ff7-a3ae-35f35c6a694a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494925875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.494925875
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2161094616
Short name T609
Test name
Test status
Simulation time 42868505 ps
CPU time 0.6 seconds
Started Jul 12 05:43:41 PM PDT 24
Finished Jul 12 05:43:43 PM PDT 24
Peak memory 194348 kb
Host smart-96e48c0c-aef3-42de-a46d-b8beb05cce29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161094616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2161094616
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.854544029
Short name T381
Test name
Test status
Simulation time 116075952 ps
CPU time 0.87 seconds
Started Jul 12 05:43:27 PM PDT 24
Finished Jul 12 05:43:29 PM PDT 24
Peak memory 197056 kb
Host smart-bbf5919d-1bf3-4e80-9c0f-0e4cee49337e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854544029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.854544029
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2617882989
Short name T205
Test name
Test status
Simulation time 474837487 ps
CPU time 16.61 seconds
Started Jul 12 05:43:32 PM PDT 24
Finished Jul 12 05:43:50 PM PDT 24
Peak memory 198644 kb
Host smart-a1e8ccb2-2e32-419c-8802-46aeb0bb6b9b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617882989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2617882989
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.4058871914
Short name T589
Test name
Test status
Simulation time 36895261 ps
CPU time 1.12 seconds
Started Jul 12 05:43:29 PM PDT 24
Finished Jul 12 05:43:31 PM PDT 24
Peak memory 196716 kb
Host smart-0cba1858-be74-46b4-953c-1108bd853cf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058871914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.4058871914
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1740584812
Short name T712
Test name
Test status
Simulation time 178487072 ps
CPU time 1.25 seconds
Started Jul 12 05:43:32 PM PDT 24
Finished Jul 12 05:43:34 PM PDT 24
Peak memory 198696 kb
Host smart-70da108e-5f18-4bef-b2d6-3933456e361a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740584812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1740584812
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3178541187
Short name T649
Test name
Test status
Simulation time 59277303 ps
CPU time 1.33 seconds
Started Jul 12 05:43:30 PM PDT 24
Finished Jul 12 05:43:32 PM PDT 24
Peak memory 197148 kb
Host smart-d09cef3f-318c-4d5e-9fd0-b44f9aba8c9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178541187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3178541187
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1986479328
Short name T396
Test name
Test status
Simulation time 66498189 ps
CPU time 1.29 seconds
Started Jul 12 05:43:33 PM PDT 24
Finished Jul 12 05:43:35 PM PDT 24
Peak memory 197288 kb
Host smart-828abdc0-e753-4a25-a229-b1684caf37fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986479328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1986479328
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3884841813
Short name T704
Test name
Test status
Simulation time 22341290 ps
CPU time 0.65 seconds
Started Jul 12 05:43:31 PM PDT 24
Finished Jul 12 05:43:33 PM PDT 24
Peak memory 194896 kb
Host smart-bc00f2db-9c42-4ba2-9791-155f4f4d38c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884841813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3884841813
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.4285552358
Short name T684
Test name
Test status
Simulation time 451458380 ps
CPU time 4.72 seconds
Started Jul 12 05:43:34 PM PDT 24
Finished Jul 12 05:43:40 PM PDT 24
Peak memory 198604 kb
Host smart-e2ba4710-aefa-498c-abfb-5dbb64a0b1e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285552358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.4285552358
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1079505220
Short name T398
Test name
Test status
Simulation time 30928528 ps
CPU time 0.67 seconds
Started Jul 12 05:43:31 PM PDT 24
Finished Jul 12 05:43:32 PM PDT 24
Peak memory 195480 kb
Host smart-62d7d1ef-7af7-4c33-bbc3-3e1d3028870c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079505220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1079505220
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2636308524
Short name T358
Test name
Test status
Simulation time 278493719 ps
CPU time 0.89 seconds
Started Jul 12 05:43:33 PM PDT 24
Finished Jul 12 05:43:35 PM PDT 24
Peak memory 196052 kb
Host smart-e57bffec-f9aa-42fb-82b3-d621e9006d2e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636308524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2636308524
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.382585034
Short name T370
Test name
Test status
Simulation time 56896265052 ps
CPU time 213.94 seconds
Started Jul 12 05:43:34 PM PDT 24
Finished Jul 12 05:47:09 PM PDT 24
Peak memory 198760 kb
Host smart-da977e99-8d7c-49e8-b8d7-298f89fb007c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382585034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.382585034
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1432170251
Short name T218
Test name
Test status
Simulation time 38931346 ps
CPU time 0.57 seconds
Started Jul 12 05:43:38 PM PDT 24
Finished Jul 12 05:43:40 PM PDT 24
Peak memory 194828 kb
Host smart-f8333389-ca13-443a-94da-6b602949da10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432170251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1432170251
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2464888554
Short name T369
Test name
Test status
Simulation time 40339820 ps
CPU time 0.77 seconds
Started Jul 12 05:43:41 PM PDT 24
Finished Jul 12 05:43:43 PM PDT 24
Peak memory 195932 kb
Host smart-9ec9d712-fe31-4385-9429-42cb660dc06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464888554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2464888554
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2997796794
Short name T78
Test name
Test status
Simulation time 412748468 ps
CPU time 13.87 seconds
Started Jul 12 05:43:45 PM PDT 24
Finished Jul 12 05:44:00 PM PDT 24
Peak memory 197280 kb
Host smart-0528bb75-9dbc-408b-b840-d6a5cdf9bd1d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997796794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2997796794
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2939903356
Short name T570
Test name
Test status
Simulation time 210013174 ps
CPU time 0.8 seconds
Started Jul 12 05:43:40 PM PDT 24
Finished Jul 12 05:43:43 PM PDT 24
Peak memory 196684 kb
Host smart-5e6391c9-12fa-414c-aed0-be81df4fd3c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939903356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2939903356
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3730554463
Short name T331
Test name
Test status
Simulation time 111932364 ps
CPU time 1.03 seconds
Started Jul 12 05:43:38 PM PDT 24
Finished Jul 12 05:43:41 PM PDT 24
Peak memory 196788 kb
Host smart-28d8aa2d-0f4d-4a4d-8be8-9e6d445778fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730554463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3730554463
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1835489910
Short name T499
Test name
Test status
Simulation time 110615018 ps
CPU time 2.3 seconds
Started Jul 12 05:43:45 PM PDT 24
Finished Jul 12 05:43:49 PM PDT 24
Peak memory 198812 kb
Host smart-6528600a-7a17-4b21-8cc7-f00912b6a267
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835489910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1835489910
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1750928588
Short name T624
Test name
Test status
Simulation time 80040207 ps
CPU time 1.93 seconds
Started Jul 12 05:43:41 PM PDT 24
Finished Jul 12 05:43:44 PM PDT 24
Peak memory 196692 kb
Host smart-ceec0bc5-fd26-4096-b89d-891b0ec590c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750928588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1750928588
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2702330908
Short name T313
Test name
Test status
Simulation time 26870712 ps
CPU time 0.78 seconds
Started Jul 12 05:43:42 PM PDT 24
Finished Jul 12 05:43:44 PM PDT 24
Peak memory 196348 kb
Host smart-f25255fc-7fbb-48e0-b93d-36d05bc1d08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702330908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2702330908
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1528433203
Short name T349
Test name
Test status
Simulation time 33118862 ps
CPU time 1.17 seconds
Started Jul 12 05:43:37 PM PDT 24
Finished Jul 12 05:43:39 PM PDT 24
Peak memory 198604 kb
Host smart-98e7fd03-7e9c-4e0b-9583-a345f7dea12f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528433203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1528433203
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.362731811
Short name T68
Test name
Test status
Simulation time 87745987 ps
CPU time 3.98 seconds
Started Jul 12 05:43:38 PM PDT 24
Finished Jul 12 05:43:44 PM PDT 24
Peak memory 198656 kb
Host smart-a5b04df4-cef4-42ea-96d3-6c3572777469
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362731811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.362731811
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1169139440
Short name T637
Test name
Test status
Simulation time 820069992 ps
CPU time 1.38 seconds
Started Jul 12 05:43:37 PM PDT 24
Finished Jul 12 05:43:39 PM PDT 24
Peak memory 198504 kb
Host smart-4fbd4c27-e2ac-4244-8acb-31e36e3e9993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169139440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1169139440
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1876945040
Short name T451
Test name
Test status
Simulation time 33795362 ps
CPU time 1.08 seconds
Started Jul 12 05:43:43 PM PDT 24
Finished Jul 12 05:43:45 PM PDT 24
Peak memory 197284 kb
Host smart-fe267077-a893-433a-9747-36803815960e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876945040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1876945040
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.964003788
Short name T307
Test name
Test status
Simulation time 18836804098 ps
CPU time 27.97 seconds
Started Jul 12 05:43:37 PM PDT 24
Finished Jul 12 05:44:06 PM PDT 24
Peak memory 198712 kb
Host smart-d1ffb652-99d8-4b19-9e69-10816f75d149
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964003788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.964003788
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.624786961
Short name T339
Test name
Test status
Simulation time 17764759 ps
CPU time 0.58 seconds
Started Jul 12 05:43:36 PM PDT 24
Finished Jul 12 05:43:37 PM PDT 24
Peak memory 195556 kb
Host smart-750b280b-d946-4358-bcc3-0dd6df8471ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624786961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.624786961
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2634263529
Short name T480
Test name
Test status
Simulation time 464471899 ps
CPU time 0.84 seconds
Started Jul 12 05:43:38 PM PDT 24
Finished Jul 12 05:43:40 PM PDT 24
Peak memory 197800 kb
Host smart-4cd9f5b4-5372-4cb4-94cd-14995f9b5976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634263529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2634263529
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.231716079
Short name T355
Test name
Test status
Simulation time 828408900 ps
CPU time 23.2 seconds
Started Jul 12 05:43:42 PM PDT 24
Finished Jul 12 05:44:06 PM PDT 24
Peak memory 198456 kb
Host smart-4e9f915b-c0d8-4522-8e4c-c8329a83e222
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231716079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress
.231716079
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2786881396
Short name T709
Test name
Test status
Simulation time 59939407 ps
CPU time 0.78 seconds
Started Jul 12 05:43:39 PM PDT 24
Finished Jul 12 05:43:41 PM PDT 24
Peak memory 197376 kb
Host smart-db1b3bdc-45e5-434e-8e7f-525735d8b034
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786881396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2786881396
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.325839653
Short name T414
Test name
Test status
Simulation time 29230170 ps
CPU time 0.7 seconds
Started Jul 12 05:43:37 PM PDT 24
Finished Jul 12 05:43:38 PM PDT 24
Peak memory 195640 kb
Host smart-8fd45824-d4cc-4ca9-9a8b-f437c284d7b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325839653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.325839653
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1042320279
Short name T621
Test name
Test status
Simulation time 125689998 ps
CPU time 2.61 seconds
Started Jul 12 05:43:45 PM PDT 24
Finished Jul 12 05:43:49 PM PDT 24
Peak memory 198768 kb
Host smart-8bb0aabb-2d6a-4d09-a56a-5ca184fe0925
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042320279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1042320279
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3414022668
Short name T491
Test name
Test status
Simulation time 126296321 ps
CPU time 3.58 seconds
Started Jul 12 05:43:40 PM PDT 24
Finished Jul 12 05:43:45 PM PDT 24
Peak memory 196512 kb
Host smart-22c747e7-b69c-41b4-ade9-76b38b44695b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414022668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3414022668
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1758509505
Short name T418
Test name
Test status
Simulation time 59769406 ps
CPU time 0.9 seconds
Started Jul 12 05:43:38 PM PDT 24
Finished Jul 12 05:43:40 PM PDT 24
Peak memory 197260 kb
Host smart-5ab3c69e-fc1b-4fa1-a6c1-b6a5190e2ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758509505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1758509505
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3838035046
Short name T692
Test name
Test status
Simulation time 34684155 ps
CPU time 0.88 seconds
Started Jul 12 05:43:43 PM PDT 24
Finished Jul 12 05:43:45 PM PDT 24
Peak memory 196104 kb
Host smart-24683647-19d2-41a5-968d-0b89c5b39fa6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838035046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3838035046
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.809373174
Short name T5
Test name
Test status
Simulation time 6091396776 ps
CPU time 6.14 seconds
Started Jul 12 05:43:38 PM PDT 24
Finished Jul 12 05:43:45 PM PDT 24
Peak memory 198580 kb
Host smart-9b550fda-8b53-42f2-b956-b2b2e6baaead
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809373174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.809373174
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3523193773
Short name T16
Test name
Test status
Simulation time 84174659 ps
CPU time 1.35 seconds
Started Jul 12 05:43:44 PM PDT 24
Finished Jul 12 05:43:46 PM PDT 24
Peak memory 198744 kb
Host smart-98e70e3c-73b3-4077-8506-f7d9d8bbcf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523193773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3523193773
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2584780245
Short name T134
Test name
Test status
Simulation time 198133841 ps
CPU time 0.94 seconds
Started Jul 12 05:43:39 PM PDT 24
Finished Jul 12 05:43:42 PM PDT 24
Peak memory 196088 kb
Host smart-cddb08f2-cd7b-4744-8eeb-abdb240d5dbb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584780245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2584780245
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2551788946
Short name T277
Test name
Test status
Simulation time 4932853743 ps
CPU time 69.01 seconds
Started Jul 12 05:43:36 PM PDT 24
Finished Jul 12 05:44:45 PM PDT 24
Peak memory 198768 kb
Host smart-8df4b1ab-cd0a-4e7a-afce-74c461b0ac27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551788946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2551788946
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1752126887
Short name T846
Test name
Test status
Simulation time 74244576 ps
CPU time 1.38 seconds
Started Jul 12 05:42:52 PM PDT 24
Finished Jul 12 05:42:55 PM PDT 24
Peak memory 197332 kb
Host smart-7ebe12ab-f75d-496b-9622-b5c2e4dc9024
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1752126887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1752126887
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3336050620
Short name T853
Test name
Test status
Simulation time 95141452 ps
CPU time 0.96 seconds
Started Jul 12 05:42:50 PM PDT 24
Finished Jul 12 05:42:52 PM PDT 24
Peak memory 197052 kb
Host smart-62f02ab3-f462-4772-a72c-2249d4d1cb7d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336050620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3336050620
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3003740350
Short name T845
Test name
Test status
Simulation time 104949932 ps
CPU time 0.86 seconds
Started Jul 12 05:42:53 PM PDT 24
Finished Jul 12 05:42:55 PM PDT 24
Peak memory 196476 kb
Host smart-03d45881-6feb-4386-8580-7e74c435b33a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3003740350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3003740350
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.235614258
Short name T871
Test name
Test status
Simulation time 48170588 ps
CPU time 1.01 seconds
Started Jul 12 05:42:48 PM PDT 24
Finished Jul 12 05:42:50 PM PDT 24
Peak memory 196920 kb
Host smart-cb7687db-0c89-4909-83de-05516da8afd8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235614258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.235614258
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1534082842
Short name T876
Test name
Test status
Simulation time 44039230 ps
CPU time 1.32 seconds
Started Jul 12 05:42:51 PM PDT 24
Finished Jul 12 05:42:53 PM PDT 24
Peak memory 198396 kb
Host smart-56b2ffc5-9039-4c6f-a35e-e3710936e12b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1534082842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1534082842
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3652536391
Short name T906
Test name
Test status
Simulation time 84119806 ps
CPU time 1 seconds
Started Jul 12 05:42:50 PM PDT 24
Finished Jul 12 05:42:52 PM PDT 24
Peak memory 196056 kb
Host smart-a630b8a3-ef96-448d-aca7-e08382f0b476
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652536391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3652536391
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3799389922
Short name T888
Test name
Test status
Simulation time 208217389 ps
CPU time 1.09 seconds
Started Jul 12 05:42:51 PM PDT 24
Finished Jul 12 05:42:53 PM PDT 24
Peak memory 197116 kb
Host smart-c84fb6eb-70ab-4920-bf35-545bfa55458a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3799389922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3799389922
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1943536134
Short name T890
Test name
Test status
Simulation time 41373094 ps
CPU time 1.16 seconds
Started Jul 12 05:42:47 PM PDT 24
Finished Jul 12 05:42:50 PM PDT 24
Peak memory 198428 kb
Host smart-63606bfa-790f-4a16-8fe2-562d2d91249b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943536134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1943536134
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3617299972
Short name T932
Test name
Test status
Simulation time 494339785 ps
CPU time 0.89 seconds
Started Jul 12 05:42:53 PM PDT 24
Finished Jul 12 05:42:56 PM PDT 24
Peak memory 196764 kb
Host smart-566b82d2-90e5-4521-856e-05feb1e2dfc3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3617299972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3617299972
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.113120716
Short name T855
Test name
Test status
Simulation time 449729634 ps
CPU time 0.86 seconds
Started Jul 12 05:42:49 PM PDT 24
Finished Jul 12 05:42:51 PM PDT 24
Peak memory 195804 kb
Host smart-f57de1d2-3b86-43da-8a39-c72991efd4e5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113120716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.113120716
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.152070194
Short name T852
Test name
Test status
Simulation time 429410845 ps
CPU time 1.02 seconds
Started Jul 12 05:42:50 PM PDT 24
Finished Jul 12 05:42:53 PM PDT 24
Peak memory 196960 kb
Host smart-dd912afa-d3ec-4bf2-b74f-8a2a4e2f7076
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=152070194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.152070194
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.889475042
Short name T920
Test name
Test status
Simulation time 287361942 ps
CPU time 1.43 seconds
Started Jul 12 05:42:53 PM PDT 24
Finished Jul 12 05:42:56 PM PDT 24
Peak memory 197204 kb
Host smart-9c78de7f-c718-4937-8159-71e59717d033
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889475042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.889475042
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3691968310
Short name T940
Test name
Test status
Simulation time 219676958 ps
CPU time 1.14 seconds
Started Jul 12 05:42:52 PM PDT 24
Finished Jul 12 05:42:54 PM PDT 24
Peak memory 196956 kb
Host smart-84c0b826-20f9-431f-8032-61f3c42af27c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3691968310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3691968310
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3749446049
Short name T867
Test name
Test status
Simulation time 57531584 ps
CPU time 1.11 seconds
Started Jul 12 05:42:53 PM PDT 24
Finished Jul 12 05:42:55 PM PDT 24
Peak memory 196304 kb
Host smart-a55bd248-24e1-42fe-a328-5124829970a5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749446049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3749446049
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1118333213
Short name T854
Test name
Test status
Simulation time 87797678 ps
CPU time 1.18 seconds
Started Jul 12 05:42:51 PM PDT 24
Finished Jul 12 05:42:53 PM PDT 24
Peak memory 197104 kb
Host smart-924d062d-1ec7-4a61-a73d-91a1688d221e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1118333213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1118333213
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4137325827
Short name T899
Test name
Test status
Simulation time 31930851 ps
CPU time 1.13 seconds
Started Jul 12 05:42:56 PM PDT 24
Finished Jul 12 05:42:58 PM PDT 24
Peak memory 196972 kb
Host smart-69d29836-cfc8-4439-9be3-ae9937da09ce
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137325827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4137325827
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2611911480
Short name T847
Test name
Test status
Simulation time 112542085 ps
CPU time 1.09 seconds
Started Jul 12 05:42:53 PM PDT 24
Finished Jul 12 05:42:56 PM PDT 24
Peak memory 196880 kb
Host smart-fa1b972f-6c45-4b55-a709-7f546c4a7009
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2611911480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2611911480
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.110909917
Short name T902
Test name
Test status
Simulation time 91041221 ps
CPU time 0.86 seconds
Started Jul 12 05:42:54 PM PDT 24
Finished Jul 12 05:42:56 PM PDT 24
Peak memory 196960 kb
Host smart-73372648-3789-4343-bed5-2d0148a34e9e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110909917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.110909917
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2883972262
Short name T927
Test name
Test status
Simulation time 31663455 ps
CPU time 0.87 seconds
Started Jul 12 05:42:54 PM PDT 24
Finished Jul 12 05:42:56 PM PDT 24
Peak memory 195780 kb
Host smart-830dd6b6-e48a-4db7-84b2-66d4e095e9b3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2883972262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2883972262
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4006182085
Short name T874
Test name
Test status
Simulation time 86089832 ps
CPU time 1.42 seconds
Started Jul 12 05:42:55 PM PDT 24
Finished Jul 12 05:42:58 PM PDT 24
Peak memory 197012 kb
Host smart-b0fbe490-7070-4040-97d7-0b48099b5340
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006182085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4006182085
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2949180749
Short name T933
Test name
Test status
Simulation time 86753157 ps
CPU time 1.46 seconds
Started Jul 12 05:42:56 PM PDT 24
Finished Jul 12 05:42:59 PM PDT 24
Peak memory 198440 kb
Host smart-16a2af62-8038-4327-a728-ee87936626f4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2949180749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2949180749
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3749955296
Short name T879
Test name
Test status
Simulation time 54203040 ps
CPU time 1.39 seconds
Started Jul 12 05:42:54 PM PDT 24
Finished Jul 12 05:42:57 PM PDT 24
Peak memory 197108 kb
Host smart-eaf5931b-615e-4210-8154-4d25801e80ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749955296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3749955296
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.365013734
Short name T929
Test name
Test status
Simulation time 95966111 ps
CPU time 1.43 seconds
Started Jul 12 05:42:54 PM PDT 24
Finished Jul 12 05:42:58 PM PDT 24
Peak memory 197008 kb
Host smart-1706838e-d134-498e-b115-12e4a04e4239
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=365013734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.365013734
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.74550739
Short name T901
Test name
Test status
Simulation time 258804561 ps
CPU time 0.87 seconds
Started Jul 12 05:42:54 PM PDT 24
Finished Jul 12 05:42:57 PM PDT 24
Peak memory 196900 kb
Host smart-5e236cad-2c46-40a8-8d63-199f6e58eefb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74550739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.74550739
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3933311999
Short name T939
Test name
Test status
Simulation time 90221304 ps
CPU time 1.15 seconds
Started Jul 12 05:42:53 PM PDT 24
Finished Jul 12 05:42:55 PM PDT 24
Peak memory 197172 kb
Host smart-4e9901b3-3680-4400-b1d8-2692750de1bb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3933311999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3933311999
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3375364090
Short name T877
Test name
Test status
Simulation time 76596094 ps
CPU time 1.35 seconds
Started Jul 12 05:42:49 PM PDT 24
Finished Jul 12 05:42:52 PM PDT 24
Peak memory 197360 kb
Host smart-d2ff61a6-03d8-4344-882d-27689308730e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375364090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3375364090
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1302665523
Short name T844
Test name
Test status
Simulation time 62281612 ps
CPU time 1.06 seconds
Started Jul 12 05:42:55 PM PDT 24
Finished Jul 12 05:42:58 PM PDT 24
Peak memory 197204 kb
Host smart-5606196b-967c-4b67-93ca-420acbce08d5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1302665523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1302665523
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1823124138
Short name T849
Test name
Test status
Simulation time 85072828 ps
CPU time 1.06 seconds
Started Jul 12 05:42:51 PM PDT 24
Finished Jul 12 05:42:54 PM PDT 24
Peak memory 196924 kb
Host smart-7c528d6d-f3af-461a-a66b-fa6486f01a6c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823124138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1823124138
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1653273900
Short name T910
Test name
Test status
Simulation time 85762668 ps
CPU time 0.98 seconds
Started Jul 12 05:42:54 PM PDT 24
Finished Jul 12 05:42:57 PM PDT 24
Peak memory 196924 kb
Host smart-a3348248-f468-4e46-87a1-3652872322be
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1653273900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1653273900
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3373925964
Short name T916
Test name
Test status
Simulation time 101313019 ps
CPU time 1.02 seconds
Started Jul 12 05:42:53 PM PDT 24
Finished Jul 12 05:42:55 PM PDT 24
Peak memory 196860 kb
Host smart-d3259e6d-7fd0-46a3-8137-718b096d3829
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373925964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3373925964
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2830254430
Short name T937
Test name
Test status
Simulation time 124338653 ps
CPU time 1.02 seconds
Started Jul 12 05:42:54 PM PDT 24
Finished Jul 12 05:42:57 PM PDT 24
Peak memory 197000 kb
Host smart-3e87fd00-cfdd-4a6a-81a5-09326320c161
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2830254430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2830254430
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.118444989
Short name T881
Test name
Test status
Simulation time 195889003 ps
CPU time 1.24 seconds
Started Jul 12 05:42:55 PM PDT 24
Finished Jul 12 05:42:58 PM PDT 24
Peak memory 197040 kb
Host smart-7a395da0-8f36-4dde-b523-36c461fa0382
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118444989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.118444989
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.783237019
Short name T873
Test name
Test status
Simulation time 60053339 ps
CPU time 1.19 seconds
Started Jul 12 05:42:54 PM PDT 24
Finished Jul 12 05:42:56 PM PDT 24
Peak memory 197212 kb
Host smart-1eb839ea-6c00-4b95-a101-e105fef89ea4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=783237019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.783237019
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1280786297
Short name T903
Test name
Test status
Simulation time 277910254 ps
CPU time 1.08 seconds
Started Jul 12 05:42:57 PM PDT 24
Finished Jul 12 05:42:59 PM PDT 24
Peak memory 197240 kb
Host smart-0467362e-504f-4786-8a49-befca2e8545c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280786297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1280786297
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3752807196
Short name T887
Test name
Test status
Simulation time 491891170 ps
CPU time 1.15 seconds
Started Jul 12 05:42:54 PM PDT 24
Finished Jul 12 05:42:57 PM PDT 24
Peak memory 196976 kb
Host smart-912f267a-d35e-4181-a5ba-4f99e889d625
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3752807196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3752807196
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.990538353
Short name T941
Test name
Test status
Simulation time 76856454 ps
CPU time 1.47 seconds
Started Jul 12 05:42:54 PM PDT 24
Finished Jul 12 05:42:56 PM PDT 24
Peak memory 197280 kb
Host smart-67905306-ab43-44ce-9d62-8e74ce3b129b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990538353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.990538353
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1552846986
Short name T880
Test name
Test status
Simulation time 37230882 ps
CPU time 1.2 seconds
Started Jul 12 05:42:53 PM PDT 24
Finished Jul 12 05:42:56 PM PDT 24
Peak memory 197920 kb
Host smart-28b6026e-d064-44d0-ac91-e26b05aae3d6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1552846986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1552846986
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1744314211
Short name T869
Test name
Test status
Simulation time 163405262 ps
CPU time 1.37 seconds
Started Jul 12 05:42:54 PM PDT 24
Finished Jul 12 05:42:57 PM PDT 24
Peak memory 197100 kb
Host smart-09917bb4-4450-4136-bbbe-a287d4a4e7ae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744314211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1744314211
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.828691149
Short name T922
Test name
Test status
Simulation time 30282836 ps
CPU time 0.98 seconds
Started Jul 12 05:42:52 PM PDT 24
Finished Jul 12 05:42:54 PM PDT 24
Peak memory 196852 kb
Host smart-c921d8d4-718b-48a1-9ac6-85ebb3ead3ad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=828691149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.828691149
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.673783975
Short name T858
Test name
Test status
Simulation time 166179207 ps
CPU time 1.2 seconds
Started Jul 12 05:43:00 PM PDT 24
Finished Jul 12 05:43:02 PM PDT 24
Peak memory 197956 kb
Host smart-0c411572-e68a-4356-9e0d-9edd5836f6a3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673783975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.673783975
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1346231859
Short name T864
Test name
Test status
Simulation time 82528734 ps
CPU time 1.2 seconds
Started Jul 12 05:42:58 PM PDT 24
Finished Jul 12 05:43:01 PM PDT 24
Peak memory 197372 kb
Host smart-0a38f88d-c60a-40b0-b79e-0d65eb9ee3c1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1346231859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1346231859
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1440083740
Short name T893
Test name
Test status
Simulation time 113044104 ps
CPU time 1.02 seconds
Started Jul 12 05:42:58 PM PDT 24
Finished Jul 12 05:43:00 PM PDT 24
Peak memory 198152 kb
Host smart-bfc525fb-0361-4f60-9de3-642b35730170
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440083740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1440083740
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.914669222
Short name T926
Test name
Test status
Simulation time 185384445 ps
CPU time 1.28 seconds
Started Jul 12 05:43:03 PM PDT 24
Finished Jul 12 05:43:05 PM PDT 24
Peak memory 197224 kb
Host smart-6b05d512-ac7b-4a24-8a51-3b9ee4829856
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=914669222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.914669222
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3135484802
Short name T859
Test name
Test status
Simulation time 52847396 ps
CPU time 1.12 seconds
Started Jul 12 05:42:59 PM PDT 24
Finished Jul 12 05:43:01 PM PDT 24
Peak memory 192032 kb
Host smart-30c804ac-4b12-4fd3-b5b8-cf29f115060f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135484802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3135484802
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3862542368
Short name T935
Test name
Test status
Simulation time 70155763 ps
CPU time 1.29 seconds
Started Jul 12 05:43:03 PM PDT 24
Finished Jul 12 05:43:05 PM PDT 24
Peak memory 198384 kb
Host smart-5835d27f-7659-49ac-b699-4e6ffa7efc90
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3862542368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3862542368
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1759612921
Short name T892
Test name
Test status
Simulation time 219518169 ps
CPU time 1.35 seconds
Started Jul 12 05:43:02 PM PDT 24
Finished Jul 12 05:43:04 PM PDT 24
Peak memory 197024 kb
Host smart-5dafa978-9402-4d19-be6e-aa2f9dd791e2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759612921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1759612921
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1622393696
Short name T862
Test name
Test status
Simulation time 44091807 ps
CPU time 1.15 seconds
Started Jul 12 05:42:49 PM PDT 24
Finished Jul 12 05:42:51 PM PDT 24
Peak memory 197232 kb
Host smart-a2001219-8356-4b5e-8eb6-2326f0edc900
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1622393696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1622393696
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3222646937
Short name T860
Test name
Test status
Simulation time 653504866 ps
CPU time 1.45 seconds
Started Jul 12 05:42:49 PM PDT 24
Finished Jul 12 05:42:52 PM PDT 24
Peak memory 196944 kb
Host smart-5a620407-308c-46cb-ac0a-b1af3ba4eab1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222646937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3222646937
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3910075349
Short name T912
Test name
Test status
Simulation time 51250392 ps
CPU time 1.13 seconds
Started Jul 12 05:43:02 PM PDT 24
Finished Jul 12 05:43:04 PM PDT 24
Peak memory 198544 kb
Host smart-46b880c1-93df-435c-a24e-c55828d76b86
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3910075349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3910075349
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4117469480
Short name T848
Test name
Test status
Simulation time 120957591 ps
CPU time 1.08 seconds
Started Jul 12 05:43:03 PM PDT 24
Finished Jul 12 05:43:04 PM PDT 24
Peak memory 196900 kb
Host smart-b17836b6-bbff-44e3-b6f8-47dd915807e4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117469480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4117469480
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3785900795
Short name T934
Test name
Test status
Simulation time 121671143 ps
CPU time 1.35 seconds
Started Jul 12 05:43:00 PM PDT 24
Finished Jul 12 05:43:02 PM PDT 24
Peak memory 197028 kb
Host smart-e4b0fe77-6619-4259-8772-92548ea6f0f7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3785900795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3785900795
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.11530243
Short name T921
Test name
Test status
Simulation time 59594248 ps
CPU time 1.48 seconds
Started Jul 12 05:42:59 PM PDT 24
Finished Jul 12 05:43:01 PM PDT 24
Peak memory 198012 kb
Host smart-f2bf7e03-314d-4035-b4ac-6f479df052ac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11530243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.11530243
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2740848790
Short name T865
Test name
Test status
Simulation time 141113056 ps
CPU time 1.37 seconds
Started Jul 12 05:43:00 PM PDT 24
Finished Jul 12 05:43:02 PM PDT 24
Peak memory 198336 kb
Host smart-677f44c9-e38a-4259-aded-4927639561da
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2740848790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2740848790
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1163802309
Short name T904
Test name
Test status
Simulation time 115702458 ps
CPU time 1.11 seconds
Started Jul 12 05:43:01 PM PDT 24
Finished Jul 12 05:43:02 PM PDT 24
Peak memory 196944 kb
Host smart-fd3d76bf-cafd-40d1-985e-babc8d66ce68
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163802309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1163802309
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2149903004
Short name T872
Test name
Test status
Simulation time 449851792 ps
CPU time 1.07 seconds
Started Jul 12 05:43:01 PM PDT 24
Finished Jul 12 05:43:02 PM PDT 24
Peak memory 198320 kb
Host smart-ca17749b-6045-40cf-8cbb-118014247a4c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2149903004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2149903004
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3106124564
Short name T918
Test name
Test status
Simulation time 25353384 ps
CPU time 0.85 seconds
Started Jul 12 05:42:58 PM PDT 24
Finished Jul 12 05:43:00 PM PDT 24
Peak memory 195680 kb
Host smart-b390f50b-612b-4dee-87a9-6da19a518d36
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106124564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3106124564
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1041165721
Short name T884
Test name
Test status
Simulation time 69991328 ps
CPU time 1.34 seconds
Started Jul 12 05:42:59 PM PDT 24
Finished Jul 12 05:43:01 PM PDT 24
Peak memory 196936 kb
Host smart-7ac82801-490c-42e8-9058-8e7d1d602258
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1041165721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1041165721
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1718264549
Short name T896
Test name
Test status
Simulation time 102646324 ps
CPU time 1.34 seconds
Started Jul 12 05:43:00 PM PDT 24
Finished Jul 12 05:43:02 PM PDT 24
Peak memory 197268 kb
Host smart-5d213bf7-95bd-4cfe-bd03-54904dfbde5d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718264549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1718264549
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4097423483
Short name T924
Test name
Test status
Simulation time 221110971 ps
CPU time 0.84 seconds
Started Jul 12 05:43:01 PM PDT 24
Finished Jul 12 05:43:02 PM PDT 24
Peak memory 195744 kb
Host smart-8d947c0d-5bba-485a-bb89-b4e878ca1d76
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4097423483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.4097423483
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4156454619
Short name T915
Test name
Test status
Simulation time 201433791 ps
CPU time 1.57 seconds
Started Jul 12 05:43:08 PM PDT 24
Finished Jul 12 05:43:10 PM PDT 24
Peak memory 197304 kb
Host smart-ecae54bd-417e-4750-9ef6-b0af67911372
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156454619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4156454619
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2807622853
Short name T923
Test name
Test status
Simulation time 331307801 ps
CPU time 1 seconds
Started Jul 12 05:43:09 PM PDT 24
Finished Jul 12 05:43:11 PM PDT 24
Peak memory 196892 kb
Host smart-9492be72-650c-494e-aeb6-ab99bc6b9ddd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2807622853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2807622853
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1294624640
Short name T938
Test name
Test status
Simulation time 363624783 ps
CPU time 0.95 seconds
Started Jul 12 05:43:10 PM PDT 24
Finished Jul 12 05:43:12 PM PDT 24
Peak memory 198284 kb
Host smart-294f1a8d-a973-4219-b374-f0ad30fd53f5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294624640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1294624640
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3543860739
Short name T919
Test name
Test status
Simulation time 335719821 ps
CPU time 1.09 seconds
Started Jul 12 05:43:08 PM PDT 24
Finished Jul 12 05:43:10 PM PDT 24
Peak memory 198428 kb
Host smart-432417e3-c9c7-427e-84f2-34c776f42437
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3543860739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3543860739
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.24616917
Short name T866
Test name
Test status
Simulation time 56976915 ps
CPU time 1.34 seconds
Started Jul 12 05:43:07 PM PDT 24
Finished Jul 12 05:43:10 PM PDT 24
Peak memory 198676 kb
Host smart-40e7c4d7-0de7-4b86-a16b-9627ab89d8cd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24616917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.24616917
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2116261320
Short name T930
Test name
Test status
Simulation time 89809161 ps
CPU time 1.33 seconds
Started Jul 12 05:43:09 PM PDT 24
Finished Jul 12 05:43:11 PM PDT 24
Peak memory 197804 kb
Host smart-8e76779e-41a9-425a-a752-555ec1ca35c3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2116261320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2116261320
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1739619297
Short name T897
Test name
Test status
Simulation time 200412643 ps
CPU time 0.91 seconds
Started Jul 12 05:43:07 PM PDT 24
Finished Jul 12 05:43:09 PM PDT 24
Peak memory 195784 kb
Host smart-2b706942-5c4e-476f-b25e-deeb7f1f8e9b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739619297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1739619297
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2975711916
Short name T843
Test name
Test status
Simulation time 133127016 ps
CPU time 1.29 seconds
Started Jul 12 05:43:09 PM PDT 24
Finished Jul 12 05:43:11 PM PDT 24
Peak memory 197332 kb
Host smart-27f82b5e-ba86-4d94-b0d6-141384a03cc2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2975711916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2975711916
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2616638536
Short name T908
Test name
Test status
Simulation time 76514619 ps
CPU time 1.34 seconds
Started Jul 12 05:43:06 PM PDT 24
Finished Jul 12 05:43:09 PM PDT 24
Peak memory 196872 kb
Host smart-c5a032a6-d74a-46cc-afbd-c1aeb1251ab7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616638536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2616638536
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2853043590
Short name T925
Test name
Test status
Simulation time 144698282 ps
CPU time 1.44 seconds
Started Jul 12 05:42:54 PM PDT 24
Finished Jul 12 05:42:57 PM PDT 24
Peak memory 195792 kb
Host smart-1909e6f0-deff-47fb-bd5f-83e62cde8cf6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2853043590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2853043590
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2017061271
Short name T863
Test name
Test status
Simulation time 798078489 ps
CPU time 1.15 seconds
Started Jul 12 05:42:48 PM PDT 24
Finished Jul 12 05:42:50 PM PDT 24
Peak memory 197136 kb
Host smart-940cc76a-ef04-4d7e-955b-248d883e77b7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017061271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2017061271
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1249674130
Short name T885
Test name
Test status
Simulation time 28125414 ps
CPU time 0.76 seconds
Started Jul 12 05:43:06 PM PDT 24
Finished Jul 12 05:43:08 PM PDT 24
Peak memory 196416 kb
Host smart-7cfd08f4-0836-4b34-9bf7-30af86da26a6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1249674130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1249674130
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3301787663
Short name T928
Test name
Test status
Simulation time 74940014 ps
CPU time 1.47 seconds
Started Jul 12 05:43:10 PM PDT 24
Finished Jul 12 05:43:12 PM PDT 24
Peak memory 197016 kb
Host smart-41e791bb-7a85-4691-9c4f-be4c76a16417
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301787663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3301787663
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3638252703
Short name T868
Test name
Test status
Simulation time 1447576072 ps
CPU time 1.37 seconds
Started Jul 12 05:43:06 PM PDT 24
Finished Jul 12 05:43:08 PM PDT 24
Peak memory 197076 kb
Host smart-0c2917a4-9a31-4b79-99a4-fb7a4a8a1abd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3638252703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3638252703
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1081034965
Short name T861
Test name
Test status
Simulation time 50142750 ps
CPU time 0.96 seconds
Started Jul 12 05:43:08 PM PDT 24
Finished Jul 12 05:43:10 PM PDT 24
Peak memory 195692 kb
Host smart-9aa6b5bf-1460-4922-bc11-d56b4d3027ce
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081034965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1081034965
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3839147851
Short name T936
Test name
Test status
Simulation time 327811112 ps
CPU time 1.26 seconds
Started Jul 12 05:43:05 PM PDT 24
Finished Jul 12 05:43:07 PM PDT 24
Peak memory 197204 kb
Host smart-ba2c9011-7b7f-4f8c-b46c-730cae0691ad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3839147851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3839147851
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2877261668
Short name T909
Test name
Test status
Simulation time 140515804 ps
CPU time 1.23 seconds
Started Jul 12 05:43:07 PM PDT 24
Finished Jul 12 05:43:10 PM PDT 24
Peak memory 197052 kb
Host smart-6968afd6-8a58-4c1f-b3be-e7c3918e284f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877261668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2877261668
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.296143932
Short name T882
Test name
Test status
Simulation time 133859425 ps
CPU time 0.86 seconds
Started Jul 12 05:43:07 PM PDT 24
Finished Jul 12 05:43:10 PM PDT 24
Peak memory 196432 kb
Host smart-0a8dccec-bc14-40cd-97dc-d0bcdd38274f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=296143932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.296143932
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1991074520
Short name T894
Test name
Test status
Simulation time 54747002 ps
CPU time 1.09 seconds
Started Jul 12 05:43:08 PM PDT 24
Finished Jul 12 05:43:10 PM PDT 24
Peak memory 196204 kb
Host smart-2fe41e8a-7917-407e-9fe9-9999450d2773
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991074520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1991074520
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3527201244
Short name T878
Test name
Test status
Simulation time 63741689 ps
CPU time 1.12 seconds
Started Jul 12 05:43:06 PM PDT 24
Finished Jul 12 05:43:08 PM PDT 24
Peak memory 195976 kb
Host smart-6e97abe4-5ceb-4657-b61f-6c5b98fcdee2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3527201244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3527201244
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2191257857
Short name T875
Test name
Test status
Simulation time 103097886 ps
CPU time 1.26 seconds
Started Jul 12 05:43:06 PM PDT 24
Finished Jul 12 05:43:08 PM PDT 24
Peak memory 197012 kb
Host smart-c8aaf7f1-53c8-4075-b576-bc84c8f97377
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191257857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2191257857
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.97907136
Short name T889
Test name
Test status
Simulation time 1329534027 ps
CPU time 1.4 seconds
Started Jul 12 05:43:07 PM PDT 24
Finished Jul 12 05:43:10 PM PDT 24
Peak memory 192092 kb
Host smart-f0e0e3a3-5430-48e7-acc5-c689fb10dc52
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=97907136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.97907136
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.753179542
Short name T905
Test name
Test status
Simulation time 35265407 ps
CPU time 1.1 seconds
Started Jul 12 05:43:08 PM PDT 24
Finished Jul 12 05:43:10 PM PDT 24
Peak memory 197984 kb
Host smart-eb22aeaa-88ca-4789-a899-fe940a55aaa2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753179542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.753179542
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3196204284
Short name T851
Test name
Test status
Simulation time 255553945 ps
CPU time 0.89 seconds
Started Jul 12 05:43:09 PM PDT 24
Finished Jul 12 05:43:11 PM PDT 24
Peak memory 197140 kb
Host smart-9ee39c4c-5501-4b2f-a0ec-826254fda74b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3196204284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.3196204284
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2890768327
Short name T931
Test name
Test status
Simulation time 549870848 ps
CPU time 0.93 seconds
Started Jul 12 05:43:07 PM PDT 24
Finished Jul 12 05:43:09 PM PDT 24
Peak memory 197004 kb
Host smart-689ad228-e0f1-4b58-99c7-b6814b672f5c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890768327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2890768327
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3088560477
Short name T886
Test name
Test status
Simulation time 20806503 ps
CPU time 0.79 seconds
Started Jul 12 05:43:08 PM PDT 24
Finished Jul 12 05:43:10 PM PDT 24
Peak memory 195696 kb
Host smart-99fb0599-1721-4dda-877d-7308819263c6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3088560477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3088560477
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.920638675
Short name T911
Test name
Test status
Simulation time 35128365 ps
CPU time 0.92 seconds
Started Jul 12 05:43:06 PM PDT 24
Finished Jul 12 05:43:08 PM PDT 24
Peak memory 195664 kb
Host smart-e88fb5c6-8875-41ee-864c-33636ef4a193
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920638675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.920638675
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3473293597
Short name T913
Test name
Test status
Simulation time 57696994 ps
CPU time 1.09 seconds
Started Jul 12 05:43:11 PM PDT 24
Finished Jul 12 05:43:13 PM PDT 24
Peak memory 196964 kb
Host smart-adbbed4e-bca4-4925-9164-132903ac663c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3473293597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3473293597
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.750177061
Short name T850
Test name
Test status
Simulation time 167164543 ps
CPU time 1.36 seconds
Started Jul 12 05:43:12 PM PDT 24
Finished Jul 12 05:43:14 PM PDT 24
Peak memory 197268 kb
Host smart-0122075c-666c-4ef5-bcc2-f4fa3caf5098
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750177061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.750177061
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2918981346
Short name T898
Test name
Test status
Simulation time 117040703 ps
CPU time 0.86 seconds
Started Jul 12 05:43:13 PM PDT 24
Finished Jul 12 05:43:15 PM PDT 24
Peak memory 195772 kb
Host smart-6e3bbbb5-e5c5-47de-a939-5ca3cdb301f4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2918981346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2918981346
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3490965354
Short name T856
Test name
Test status
Simulation time 125887600 ps
CPU time 0.99 seconds
Started Jul 12 05:43:11 PM PDT 24
Finished Jul 12 05:43:13 PM PDT 24
Peak memory 198260 kb
Host smart-3935a977-6881-49bd-a506-f84fd4e8d71d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490965354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3490965354
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3553966033
Short name T907
Test name
Test status
Simulation time 263708821 ps
CPU time 1.08 seconds
Started Jul 12 05:42:51 PM PDT 24
Finished Jul 12 05:42:53 PM PDT 24
Peak memory 196144 kb
Host smart-023bbf2e-6e77-4b8f-ac95-a621c2db5fc1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3553966033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3553966033
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1914611194
Short name T842
Test name
Test status
Simulation time 177715750 ps
CPU time 1.37 seconds
Started Jul 12 05:42:47 PM PDT 24
Finished Jul 12 05:42:49 PM PDT 24
Peak memory 197248 kb
Host smart-37a7bc7b-6e43-4382-95e0-4d98304d4dc5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914611194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1914611194
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3848370725
Short name T895
Test name
Test status
Simulation time 100800531 ps
CPU time 1.55 seconds
Started Jul 12 05:42:49 PM PDT 24
Finished Jul 12 05:42:51 PM PDT 24
Peak memory 197028 kb
Host smart-0c94a2ed-4e26-472d-a72a-cdcf3d0279b3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3848370725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3848370725
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2227052300
Short name T900
Test name
Test status
Simulation time 73128398 ps
CPU time 1.08 seconds
Started Jul 12 05:42:54 PM PDT 24
Finished Jul 12 05:42:57 PM PDT 24
Peak memory 196848 kb
Host smart-2e92a521-93ee-45ff-83e0-f5cb349ce16d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227052300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2227052300
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3308592778
Short name T857
Test name
Test status
Simulation time 445891172 ps
CPU time 0.95 seconds
Started Jul 12 05:42:47 PM PDT 24
Finished Jul 12 05:42:49 PM PDT 24
Peak memory 198236 kb
Host smart-59d38c8b-4518-40ce-aa49-30192349462e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3308592778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3308592778
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2591801221
Short name T891
Test name
Test status
Simulation time 194627003 ps
CPU time 0.91 seconds
Started Jul 12 05:42:49 PM PDT 24
Finished Jul 12 05:42:52 PM PDT 24
Peak memory 196972 kb
Host smart-5fcc7c5b-f3c0-4f7f-b1d7-17a65e3c216d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591801221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2591801221
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3772046442
Short name T870
Test name
Test status
Simulation time 56738283 ps
CPU time 0.99 seconds
Started Jul 12 05:42:48 PM PDT 24
Finished Jul 12 05:42:50 PM PDT 24
Peak memory 196124 kb
Host smart-7b8f3822-39e6-4677-83cc-25adcdfee5d1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3772046442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3772046442
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.131786632
Short name T914
Test name
Test status
Simulation time 88045509 ps
CPU time 1.36 seconds
Started Jul 12 05:42:49 PM PDT 24
Finished Jul 12 05:42:52 PM PDT 24
Peak memory 197156 kb
Host smart-82ce85f5-1d68-42ac-a102-a6bdcb259d5a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131786632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.131786632
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2443906372
Short name T917
Test name
Test status
Simulation time 72460707 ps
CPU time 1.05 seconds
Started Jul 12 05:42:49 PM PDT 24
Finished Jul 12 05:42:51 PM PDT 24
Peak memory 196240 kb
Host smart-ecf006d6-01ce-4f9b-8c13-f7d1ebe1df63
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2443906372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2443906372
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.20133277
Short name T883
Test name
Test status
Simulation time 197807236 ps
CPU time 1.25 seconds
Started Jul 12 05:42:50 PM PDT 24
Finished Jul 12 05:42:53 PM PDT 24
Peak memory 198132 kb
Host smart-8584c22a-7164-4918-bf73-0e34bd163b04
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20133277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.20133277
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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