Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4368997	1			T22	1		T23	1		T24	98055
all_pins[1]	4368997	1			T22	1		T23	1		T24	98055
all_pins[2]	4368997	1			T22	1		T23	1		T24	98055
all_pins[3]	4368997	1			T22	1		T23	1		T24	98055
all_pins[4]	4368997	1			T22	1		T23	1		T24	98055
all_pins[5]	4368997	1			T22	1		T23	1		T24	98055
all_pins[6]	4368997	1			T22	1		T23	1		T24	98055
all_pins[7]	4368997	1			T22	1		T23	1		T24	98055
all_pins[8]	4368997	1			T22	1		T23	1		T24	98055
all_pins[9]	4368997	1			T22	1		T23	1		T24	98055
all_pins[10]	4368997	1			T22	1		T23	1		T24	98055
all_pins[11]	4368997	1			T22	1		T23	1		T24	98055
all_pins[12]	4368997	1			T22	1		T23	1		T24	98055
all_pins[13]	4368997	1			T22	1		T23	1		T24	98055
all_pins[14]	4368997	1			T22	1		T23	1		T24	98055
all_pins[15]	4368997	1			T22	1		T23	1		T24	98055
all_pins[16]	4368997	1			T22	1		T23	1		T24	98055
all_pins[17]	4368997	1			T22	1		T23	1		T24	98055
all_pins[18]	4368997	1			T22	1		T23	1		T24	98055
all_pins[19]	4368997	1			T22	1		T23	1		T24	98055
all_pins[20]	4368997	1			T22	1		T23	1		T24	98055
all_pins[21]	4368997	1			T22	1		T23	1		T24	98055
all_pins[22]	4368997	1			T22	1		T23	1		T24	98055
all_pins[23]	4368997	1			T22	1		T23	1		T24	98055
all_pins[24]	4368997	1			T22	1		T23	1		T24	98055
all_pins[25]	4368997	1			T22	1		T23	1		T24	98055
all_pins[26]	4368997	1			T22	1		T23	1		T24	98055
all_pins[27]	4368997	1			T22	1		T23	1		T24	98055
all_pins[28]	4368997	1			T22	1		T23	1		T24	98055
all_pins[29]	4368997	1			T22	1		T23	1		T24	98055
all_pins[30]	4368997	1			T22	1		T23	1		T24	98055
all_pins[31]	4368997	1			T22	1		T23	1		T24	98055

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	86811033	1			T22	32		T23	32		T24	194340
values[0x1]	52996871	1			T24	119435		T25	307369		T27	853
transitions[0x0=>0x1]	31754259	1			T24	716083		T25	184531		T27	433
transitions[0x1=>0x0]	31754079	1			T24	716082		T25	184531		T27	432

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2714220	1			T22	1		T23	1		T24	60936
all_pins[0]	values[0x1]	1654777	1			T24	37119		T25	9649		T27	27
all_pins[0]	transitions[0x0=>0x1]	1027598	1			T24	22903		T25	6089		T27	13
all_pins[0]	transitions[0x1=>0x0]	1027003	1			T24	23526		T25	5634		T27	13
all_pins[1]	values[0x0]	2713774	1			T22	1		T23	1		T24	61137
all_pins[1]	values[0x1]	1655223	1			T24	36918		T25	9713		T27	23
all_pins[1]	transitions[0x0=>0x1]	990077	1			T24	21896		T25	5781		T27	11
all_pins[1]	transitions[0x1=>0x0]	989631	1			T24	22097		T25	5717		T27	15
all_pins[2]	values[0x0]	2718275	1			T22	1		T23	1		T24	61796
all_pins[2]	values[0x1]	1650722	1			T24	36259		T25	9760		T27	31
all_pins[2]	transitions[0x0=>0x1]	985866	1			T24	21916		T25	5610		T27	20
all_pins[2]	transitions[0x1=>0x0]	990367	1			T24	22575		T25	5563		T27	12
all_pins[3]	values[0x0]	2705240	1			T22	1		T23	1		T24	61062
all_pins[3]	values[0x1]	1663757	1			T24	36993		T25	10171		T27	26
all_pins[3]	transitions[0x0=>0x1]	1000005	1			T24	22693		T25	5962		T27	13
all_pins[3]	transitions[0x1=>0x0]	986970	1			T24	21959		T25	5551		T27	18
all_pins[4]	values[0x0]	2708042	1			T22	1		T23	1		T24	60643
all_pins[4]	values[0x1]	1660955	1			T24	37412		T25	9862		T27	25
all_pins[4]	transitions[0x0=>0x1]	993175	1			T24	22239		T25	5539		T27	12
all_pins[4]	transitions[0x1=>0x0]	995977	1			T24	21820		T25	5848		T27	13
all_pins[5]	values[0x0]	2715906	1			T22	1		T23	1		T24	59672
all_pins[5]	values[0x1]	1653091	1			T24	38383		T25	9848		T27	30
all_pins[5]	transitions[0x0=>0x1]	985350	1			T24	22603		T25	5853		T27	17
all_pins[5]	transitions[0x1=>0x0]	993214	1			T24	21632		T25	5867		T27	12
all_pins[6]	values[0x0]	2710622	1			T22	1		T23	1		T24	61653
all_pins[6]	values[0x1]	1658375	1			T24	36402		T25	9205		T27	21
all_pins[6]	transitions[0x0=>0x1]	994011	1			T24	21258		T25	5510		T27	10
all_pins[6]	transitions[0x1=>0x0]	988727	1			T24	23239		T25	6153		T27	19
all_pins[7]	values[0x0]	2709549	1			T22	1		T23	1		T24	60579
all_pins[7]	values[0x1]	1659448	1			T24	37476		T25	9400		T27	25
all_pins[7]	transitions[0x0=>0x1]	993016	1			T24	22690		T25	5582		T27	16
all_pins[7]	transitions[0x1=>0x0]	991943	1			T24	21616		T25	5387		T27	12
all_pins[8]	values[0x0]	2710504	1			T22	1		T23	1		T24	60557
all_pins[8]	values[0x1]	1658493	1			T24	37498		T25	9596		T27	22
all_pins[8]	transitions[0x0=>0x1]	991511	1			T24	22045		T25	5913		T27	13
all_pins[8]	transitions[0x1=>0x0]	992466	1			T24	22023		T25	5717		T27	16
all_pins[9]	values[0x0]	2713342	1			T22	1		T23	1		T24	60158
all_pins[9]	values[0x1]	1655655	1			T24	37897		T25	9574		T27	25
all_pins[9]	transitions[0x0=>0x1]	990065	1			T24	22608		T25	5959		T27	13
all_pins[9]	transitions[0x1=>0x0]	992903	1			T24	22209		T25	5981		T27	10
all_pins[10]	values[0x0]	2718117	1			T22	1		T23	1		T24	61338
all_pins[10]	values[0x1]	1650880	1			T24	36717		T25	9716		T27	22
all_pins[10]	transitions[0x0=>0x1]	987908	1			T24	21839		T25	5808		T27	9
all_pins[10]	transitions[0x1=>0x0]	992683	1			T24	23019		T25	5666		T27	12
all_pins[11]	values[0x0]	2709468	1			T22	1		T23	1		T24	61266
all_pins[11]	values[0x1]	1659529	1			T24	36789		T25	9788		T27	27
all_pins[11]	transitions[0x0=>0x1]	995977	1			T24	22280		T25	5946		T27	16
all_pins[11]	transitions[0x1=>0x0]	987328	1			T24	22208		T25	5874		T27	11
all_pins[12]	values[0x0]	2714401	1			T22	1		T23	1		T24	60688
all_pins[12]	values[0x1]	1654596	1			T24	37367		T25	9628		T27	34
all_pins[12]	transitions[0x0=>0x1]	990504	1			T24	22211		T25	5649		T27	22
all_pins[12]	transitions[0x1=>0x0]	995437	1			T24	21633		T25	5809		T27	15
all_pins[13]	values[0x0]	2713180	1			T22	1		T23	1		T24	61398
all_pins[13]	values[0x1]	1655817	1			T24	36657		T25	9884		T27	25
all_pins[13]	transitions[0x0=>0x1]	988515	1			T24	21977		T25	5740		T27	11
all_pins[13]	transitions[0x1=>0x0]	987294	1			T24	22687		T25	5484		T27	20
all_pins[14]	values[0x0]	2715405	1			T22	1		T23	1		T24	60470
all_pins[14]	values[0x1]	1653592	1			T24	37585		T25	9239		T27	27
all_pins[14]	transitions[0x0=>0x1]	990495	1			T24	22567		T25	5652		T27	15
all_pins[14]	transitions[0x1=>0x0]	992720	1			T24	21639		T25	6297		T27	13
all_pins[15]	values[0x0]	2710076	1			T22	1		T23	1		T24	60372
all_pins[15]	values[0x1]	1658921	1			T24	37683		T25	10108		T27	20
all_pins[15]	transitions[0x0=>0x1]	994199	1			T24	22479		T25	6317		T27	7
all_pins[15]	transitions[0x1=>0x0]	988870	1			T24	22381		T25	5448		T27	14
all_pins[16]	values[0x0]	2714362	1			T22	1		T23	1		T24	60489
all_pins[16]	values[0x1]	1654635	1			T24	37566		T25	9563		T27	23
all_pins[16]	transitions[0x0=>0x1]	992515	1			T24	22544		T25	5698		T27	14
all_pins[16]	transitions[0x1=>0x0]	996801	1			T24	22661		T25	6243		T27	11
all_pins[17]	values[0x0]	2719062	1			T22	1		T23	1		T24	60134
all_pins[17]	values[0x1]	1649935	1			T24	37921		T25	9593		T27	22
all_pins[17]	transitions[0x0=>0x1]	991103	1			T24	22752		T25	5727		T27	11
all_pins[17]	transitions[0x1=>0x0]	995803	1			T24	22397		T25	5697		T27	12
all_pins[18]	values[0x0]	2717863	1			T22	1		T23	1		T24	60847
all_pins[18]	values[0x1]	1651134	1			T24	37208		T25	9482		T27	32
all_pins[18]	transitions[0x0=>0x1]	988908	1			T24	22572		T25	5719		T27	20
all_pins[18]	transitions[0x1=>0x0]	987709	1			T24	23285		T25	5830		T27	10
all_pins[19]	values[0x0]	2715699	1			T22	1		T23	1		T24	61311
all_pins[19]	values[0x1]	1653298	1			T24	36744		T25	9451		T27	34
all_pins[19]	transitions[0x0=>0x1]	990666	1			T24	22013		T25	5706		T27	16
all_pins[19]	transitions[0x1=>0x0]	988502	1			T24	22477		T25	5737		T27	14
all_pins[20]	values[0x0]	2712268	1			T22	1		T23	1		T24	61546
all_pins[20]	values[0x1]	1656729	1			T24	36509		T25	9632		T27	25
all_pins[20]	transitions[0x0=>0x1]	992574	1			T24	22105		T25	5875		T27	11
all_pins[20]	transitions[0x1=>0x0]	989143	1			T24	22340		T25	5694		T27	20
all_pins[21]	values[0x0]	2709029	1			T22	1		T23	1		T24	60791
all_pins[21]	values[0x1]	1659968	1			T24	37264		T25	9421		T27	30
all_pins[21]	transitions[0x0=>0x1]	993818	1			T24	22294		T25	5476		T27	13
all_pins[21]	transitions[0x1=>0x0]	990579	1			T24	21539		T25	5687		T27	8
all_pins[22]	values[0x0]	2709715	1			T22	1		T23	1		T24	59413
all_pins[22]	values[0x1]	1659282	1			T24	38642		T25	9135		T27	33
all_pins[22]	transitions[0x0=>0x1]	991068	1			T24	22867		T25	5684		T27	14
all_pins[22]	transitions[0x1=>0x0]	991754	1			T24	21489		T25	5970		T27	11
all_pins[23]	values[0x0]	2708804	1			T22	1		T23	1		T24	60055
all_pins[23]	values[0x1]	1660193	1			T24	38000		T25	9916		T27	23
all_pins[23]	transitions[0x0=>0x1]	995901	1			T24	22760		T25	6041		T27	10
all_pins[23]	transitions[0x1=>0x0]	994990	1			T24	23402		T25	5260		T27	20
all_pins[24]	values[0x0]	2712029	1			T22	1		T23	1		T24	60247
all_pins[24]	values[0x1]	1656968	1			T24	37808		T25	9461		T27	33
all_pins[24]	transitions[0x0=>0x1]	989661	1			T24	22501		T25	5567		T27	19
all_pins[24]	transitions[0x1=>0x0]	992886	1			T24	22693		T25	6022		T27	9
all_pins[25]	values[0x0]	2709233	1			T22	1		T23	1		T24	61263
all_pins[25]	values[0x1]	1659764	1			T24	36792		T25	9434		T27	23
all_pins[25]	transitions[0x0=>0x1]	991555	1			T24	21789		T25	5859		T27	8
all_pins[25]	transitions[0x1=>0x0]	988759	1			T24	22805		T25	5886		T27	18
all_pins[26]	values[0x0]	2716464	1			T22	1		T23	1		T24	61199
all_pins[26]	values[0x1]	1652533	1			T24	36856		T25	9566		T27	28
all_pins[26]	transitions[0x0=>0x1]	986376	1			T24	22215		T25	5698		T27	15
all_pins[26]	transitions[0x1=>0x0]	993607	1			T24	22151		T25	5566		T27	10
all_pins[27]	values[0x0]	2713613	1			T22	1		T23	1		T24	60541
all_pins[27]	values[0x1]	1655384	1			T24	37514		T25	9441		T27	30
all_pins[27]	transitions[0x0=>0x1]	994710	1			T24	22763		T25	5643		T27	15
all_pins[27]	transitions[0x1=>0x0]	991859	1			T24	22105		T25	5768		T27	13
all_pins[28]	values[0x0]	2707857	1			T22	1		T23	1		T24	60470
all_pins[28]	values[0x1]	1661140	1			T24	37585		T25	9489		T27	23
all_pins[28]	transitions[0x0=>0x1]	992661	1			T24	22598		T25	5773		T27	11
all_pins[28]	transitions[0x1=>0x0]	986905	1			T24	22527		T25	5725		T27	18
all_pins[29]	values[0x0]	2716532	1			T22	1		T23	1		T24	59768
all_pins[29]	values[0x1]	1652465	1			T24	38287		T25	9706		T27	29
all_pins[29]	transitions[0x0=>0x1]	984490	1			T24	23143		T25	5835		T27	13
all_pins[29]	transitions[0x1=>0x0]	993165	1			T24	22441		T25	5618		T27	7
all_pins[30]	values[0x0]	2713747	1			T22	1		T23	1		T24	61296
all_pins[30]	values[0x1]	1655250	1			T24	36759		T25	9744		T27	27
all_pins[30]	transitions[0x0=>0x1]	991099	1			T24	21890		T25	5842		T27	11
all_pins[30]	transitions[0x1=>0x0]	988314	1			T24	23418		T25	5804		T27	13
all_pins[31]	values[0x0]	2714635	1			T22	1		T23	1		T24	60312
all_pins[31]	values[0x1]	1654362	1			T24	37743		T25	9194		T27	28
all_pins[31]	transitions[0x0=>0x1]	988882	1			T24	23073		T25	5478		T27	14
all_pins[31]	transitions[0x1=>0x0]	989770	1			T24	22089		T25	6028		T27	13