Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14763688	1			T22	137		T23	235		T24	275787
all_values[1]	14763688	1			T22	137		T23	235		T24	275787
all_values[2]	14763688	1			T22	137		T23	235		T24	275787
all_values[3]	14763688	1			T22	137		T23	235		T24	275787
all_values[4]	14763688	1			T22	137		T23	235		T24	275787
all_values[5]	14763688	1			T22	137		T23	235		T24	275787
all_values[6]	14763688	1			T22	137		T23	235		T24	275787
all_values[7]	14763688	1			T22	137		T23	235		T24	275787
all_values[8]	14763688	1			T22	137		T23	235		T24	275787
all_values[9]	14763688	1			T22	137		T23	235		T24	275787
all_values[10]	14763688	1			T22	137		T23	235		T24	275787
all_values[11]	14763688	1			T22	137		T23	235		T24	275787
all_values[12]	14763688	1			T22	137		T23	235		T24	275787
all_values[13]	14763688	1			T22	137		T23	235		T24	275787
all_values[14]	14763688	1			T22	137		T23	235		T24	275787
all_values[15]	14763688	1			T22	137		T23	235		T24	275787
all_values[16]	14763688	1			T22	137		T23	235		T24	275787
all_values[17]	14763688	1			T22	137		T23	235		T24	275787
all_values[18]	14763688	1			T22	137		T23	235		T24	275787
all_values[19]	14763688	1			T22	137		T23	235		T24	275787
all_values[20]	14763688	1			T22	137		T23	235		T24	275787
all_values[21]	14763688	1			T22	137		T23	235		T24	275787
all_values[22]	14763688	1			T22	137		T23	235		T24	275787
all_values[23]	14763688	1			T22	137		T23	235		T24	275787
all_values[24]	14763688	1			T22	137		T23	235		T24	275787
all_values[25]	14763688	1			T22	137		T23	235		T24	275787
all_values[26]	14763688	1			T22	137		T23	235		T24	275787
all_values[27]	14763688	1			T22	137		T23	235		T24	275787
all_values[28]	14763688	1			T22	137		T23	235		T24	275787
all_values[29]	14763688	1			T22	137		T23	235		T24	275787
all_values[30]	14763688	1			T22	137		T23	235		T24	275787
all_values[31]	14763688	1			T22	137		T23	235		T24	275787

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

272771623

1

T22

4384

T23

7520

T24

442886

auto[1]

199666393

1

T24

439631

T25

993643

T1

151617

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111122602

1

T22

4384

T23

7520

T24

863258

auto[1]

361315414

1

T24

796192

T25

178054

T1

276512

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

467333066

1

T22

4384

T23

7520

T24

873226

auto[1]

5104950

1

T24

92924

T25

21402

T1

58330

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2872121	1			T22	137		T23	235		T24	14372
all_values[0]	auto[0]	auto[0]	auto[1]	5567581	1			T24	122396		T25	26101		T1	41246
all_values[0]	auto[0]	auto[1]	auto[0]	593578	1			T24	14511		T25	3222		T1	4414
all_values[0]	auto[0]	auto[1]	auto[1]	5570604	1			T24	121580		T25	28478		T1	43496
all_values[0]	auto[1]	auto[0]	auto[1]	80248	1			T24	1443		T25	315		T1	938
all_values[0]	auto[1]	auto[1]	auto[1]	79556	1			T24	1485		T25	345		T1	936
all_values[1]	auto[0]	auto[0]	auto[0]	2868320	1			T22	137		T23	235		T24	13429
all_values[1]	auto[0]	auto[0]	auto[1]	5576007	1			T24	126913		T25	26559		T1	44075
all_values[1]	auto[0]	auto[1]	auto[0]	602449	1			T24	12696		T25	3533		T1	4687
all_values[1]	auto[0]	auto[1]	auto[1]	5557321	1			T24	119888		T25	27986		T1	40503
all_values[1]	auto[1]	auto[0]	auto[1]	79814	1			T24	1475		T25	309		T1	975
all_values[1]	auto[1]	auto[1]	auto[1]	79777	1			T24	1386		T25	369		T1	862
all_values[2]	auto[0]	auto[0]	auto[0]	2884461	1			T22	137		T23	235		T24	14298
all_values[2]	auto[0]	auto[0]	auto[1]	5561244	1			T24	126977		T25	27984		T1	43218
all_values[2]	auto[0]	auto[1]	auto[0]	598415	1			T24	13451		T25	3437		T1	4538
all_values[2]	auto[0]	auto[1]	auto[1]	5560268	1			T24	118183		T25	27046		T1	41657
all_values[2]	auto[1]	auto[0]	auto[1]	79642	1			T24	1450		T25	351		T1	963
all_values[2]	auto[1]	auto[1]	auto[1]	79658	1			T24	1428		T25	310		T1	893
all_values[3]	auto[0]	auto[0]	auto[0]	2883485	1			T22	137		T23	235		T24	14614
all_values[3]	auto[0]	auto[0]	auto[1]	5560164	1			T24	124089		T25	26266		T1	41997
all_values[3]	auto[0]	auto[1]	auto[0]	591425	1			T24	14343		T25	3297		T1	4592
all_values[3]	auto[0]	auto[1]	auto[1]	5569275	1			T24	119844		T25	29307		T1	42450
all_values[3]	auto[1]	auto[0]	auto[1]	79938	1			T24	1402		T25	353		T1	944
all_values[3]	auto[1]	auto[1]	auto[1]	79401	1			T24	1495		T25	341		T1	859
all_values[4]	auto[0]	auto[0]	auto[0]	2871043	1			T22	137		T23	235		T24	13410
all_values[4]	auto[0]	auto[0]	auto[1]	5559737	1			T24	125106		T25	28029		T1	43011
all_values[4]	auto[0]	auto[1]	auto[0]	591135	1			T24	12801		T25	2988		T1	4585
all_values[4]	auto[0]	auto[1]	auto[1]	5581986	1			T24	121572		T25	27374		T1	42043
all_values[4]	auto[1]	auto[0]	auto[1]	80517	1			T24	1466		T25	379		T1	917
all_values[4]	auto[1]	auto[1]	auto[1]	79270	1			T24	1432		T25	292		T1	929
all_values[5]	auto[0]	auto[0]	auto[0]	2873860	1			T22	137		T23	235		T24	13666
all_values[5]	auto[0]	auto[0]	auto[1]	5539500	1			T24	114625		T25	27750		T1	41250
all_values[5]	auto[0]	auto[1]	auto[0]	609305	1			T24	13361		T25	3223		T1	4926
all_values[5]	auto[0]	auto[1]	auto[1]	5581325	1			T24	131224		T25	27369		T1	43126
all_values[5]	auto[1]	auto[0]	auto[1]	80505	1			T24	1396		T25	320		T1	953
all_values[5]	auto[1]	auto[1]	auto[1]	79193	1			T24	1515		T25	357		T1	900
all_values[6]	auto[0]	auto[0]	auto[0]	2875721	1			T22	137		T23	235		T24	13334
all_values[6]	auto[0]	auto[0]	auto[1]	5583282	1			T24	124631		T25	30205		T1	42880
all_values[6]	auto[0]	auto[1]	auto[0]	593142	1			T24	12589		T25	2982		T1	4620
all_values[6]	auto[0]	auto[1]	auto[1]	5552203	1			T24	122303		T25	25565		T1	41581
all_values[6]	auto[1]	auto[0]	auto[1]	80311	1			T24	1463		T25	366		T1	916
all_values[6]	auto[1]	auto[1]	auto[1]	79029	1			T24	1467		T25	312		T1	899
all_values[7]	auto[0]	auto[0]	auto[0]	2870067	1			T22	137		T23	235		T24	14381
all_values[7]	auto[0]	auto[0]	auto[1]	5586101	1			T24	121078		T25	26603		T1	41287
all_values[7]	auto[0]	auto[1]	auto[0]	589639	1			T24	13153		T25	3688		T1	4661
all_values[7]	auto[0]	auto[1]	auto[1]	5558114	1			T24	124275		T25	27874		T1	43403
all_values[7]	auto[1]	auto[0]	auto[1]	80466	1			T24	1432		T25	327		T1	952
all_values[7]	auto[1]	auto[1]	auto[1]	79301	1			T24	1468		T25	347		T1	908
all_values[8]	auto[0]	auto[0]	auto[0]	2880048	1			T22	137		T23	235		T24	14360
all_values[8]	auto[0]	auto[0]	auto[1]	5583566	1			T24	127120		T25	27382		T1	42586
all_values[8]	auto[0]	auto[1]	auto[0]	598261	1			T24	13795		T25	3172		T1	4454
all_values[8]	auto[0]	auto[1]	auto[1]	5542675	1			T24	117619		T25	27346		T1	42180
all_values[8]	auto[1]	auto[0]	auto[1]	79678	1			T24	1505		T25	354		T1	872
all_values[8]	auto[1]	auto[1]	auto[1]	79460	1			T24	1388		T25	317		T1	954
all_values[9]	auto[0]	auto[0]	auto[0]	2876247	1			T22	137		T23	235		T24	13737
all_values[9]	auto[0]	auto[0]	auto[1]	5596882	1			T24	122192		T25	26655		T1	45274
all_values[9]	auto[0]	auto[1]	auto[0]	593704	1			T24	13513		T25	3227		T1	4141
all_values[9]	auto[0]	auto[1]	auto[1]	5537388	1			T24	123385		T25	27659		T1	40070
all_values[9]	auto[1]	auto[0]	auto[1]	80135	1			T24	1479		T25	337		T1	926
all_values[9]	auto[1]	auto[1]	auto[1]	79332	1			T24	1481		T25	340		T1	820
all_values[10]	auto[0]	auto[0]	auto[0]	2871007	1			T22	137		T23	235		T24	13286
all_values[10]	auto[0]	auto[0]	auto[1]	5566315	1			T24	122885		T25	27745		T1	40815
all_values[10]	auto[0]	auto[1]	auto[0]	596143	1			T24	12145		T25	3191		T1	4947
all_values[10]	auto[0]	auto[1]	auto[1]	5571087	1			T24	124608		T25	27524		T1	43323
all_values[10]	auto[1]	auto[0]	auto[1]	79758	1			T24	1365		T25	345		T1	938
all_values[10]	auto[1]	auto[1]	auto[1]	79378	1			T24	1498		T25	317		T1	897
all_values[11]	auto[0]	auto[0]	auto[0]	2874031	1			T22	137		T23	235		T24	14167
all_values[11]	auto[0]	auto[0]	auto[1]	5565722	1			T24	117688		T25	26903		T1	41342
all_values[11]	auto[0]	auto[1]	auto[0]	592196	1			T24	14998		T25	3435		T1	4786
all_values[11]	auto[0]	auto[1]	auto[1]	5571748	1			T24	126070		T25	27796		T1	43008
all_values[11]	auto[1]	auto[0]	auto[1]	79788	1			T24	1469		T25	355		T1	876
all_values[11]	auto[1]	auto[1]	auto[1]	80203	1			T24	1395		T25	305		T1	942
all_values[12]	auto[0]	auto[0]	auto[0]	2872920	1			T22	137		T23	235		T24	13015
all_values[12]	auto[0]	auto[0]	auto[1]	5556227	1			T24	124170		T25	27275		T1	42014
all_values[12]	auto[0]	auto[1]	auto[0]	599457	1			T24	13489		T25	3522		T1	5265
all_values[12]	auto[0]	auto[1]	auto[1]	5575569	1			T24	122247		T25	27509		T1	42023
all_values[12]	auto[1]	auto[0]	auto[1]	79430	1			T24	1375		T25	363		T1	870
all_values[12]	auto[1]	auto[1]	auto[1]	80085	1			T24	1491		T25	321		T1	944
all_values[13]	auto[0]	auto[0]	auto[0]	2872915	1			T22	137		T23	235		T24	13959
all_values[13]	auto[0]	auto[0]	auto[1]	5586328	1			T24	128486		T25	25420		T1	43413
all_values[13]	auto[0]	auto[1]	auto[0]	592822	1			T24	12685		T25	3386		T1	4694
all_values[13]	auto[0]	auto[1]	auto[1]	5552120	1			T24	117776		T25	29495		T1	41524
all_values[13]	auto[1]	auto[0]	auto[1]	79882	1			T24	1486		T25	337		T1	971
all_values[13]	auto[1]	auto[1]	auto[1]	79621	1			T24	1395		T25	347		T1	832
all_values[14]	auto[0]	auto[0]	auto[0]	2867478	1			T22	137		T23	235		T24	13536
all_values[14]	auto[0]	auto[0]	auto[1]	5568517	1			T24	124213		T25	28735		T1	41805
all_values[14]	auto[0]	auto[1]	auto[0]	600041	1			T24	12456		T25	3567		T1	5175
all_values[14]	auto[0]	auto[1]	auto[1]	5568240	1			T24	122707		T25	25978		T1	42456
all_values[14]	auto[1]	auto[0]	auto[1]	80078	1			T24	1458		T25	344		T1	928
all_values[14]	auto[1]	auto[1]	auto[1]	79334	1			T24	1417		T25	347		T1	902
all_values[15]	auto[0]	auto[0]	auto[0]	2872356	1			T22	137		T23	235		T24	13723
all_values[15]	auto[0]	auto[0]	auto[1]	5570513	1			T24	123752		T25	26038		T1	43846
all_values[15]	auto[0]	auto[1]	auto[0]	601346	1			T24	12533		T25	3573		T1	4862
all_values[15]	auto[0]	auto[1]	auto[1]	5559741	1			T24	122881		T25	29070		T1	40693
all_values[15]	auto[1]	auto[0]	auto[1]	80388	1			T24	1460		T25	310		T1	892
all_values[15]	auto[1]	auto[1]	auto[1]	79344	1			T24	1438		T25	331		T1	864
all_values[16]	auto[0]	auto[0]	auto[0]	2873016	1			T22	137		T23	235		T24	13195
all_values[16]	auto[0]	auto[0]	auto[1]	5569572	1			T24	121627		T25	27442		T1	42377
all_values[16]	auto[0]	auto[1]	auto[0]	595212	1			T24	12767		T25	3199		T1	4631
all_values[16]	auto[0]	auto[1]	auto[1]	5565675	1			T24	125273		T25	27715		T1	42442
all_values[16]	auto[1]	auto[0]	auto[1]	80346	1			T24	1457		T25	338		T1	950
all_values[16]	auto[1]	auto[1]	auto[1]	79867	1			T24	1468		T25	346		T1	870
all_values[17]	auto[0]	auto[0]	auto[0]	2872424	1			T22	137		T23	235		T24	13698
all_values[17]	auto[0]	auto[0]	auto[1]	5586420	1			T24	121892		T25	27089		T1	43658
all_values[17]	auto[0]	auto[1]	auto[0]	609177	1			T24	14177		T25	3414		T1	5099
all_values[17]	auto[0]	auto[1]	auto[1]	5536034	1			T24	123135		T25	28004		T1	40512
all_values[17]	auto[1]	auto[0]	auto[1]	80024	1			T24	1466		T25	373		T1	841
all_values[17]	auto[1]	auto[1]	auto[1]	79609	1			T24	1419		T25	308		T1	976
all_values[18]	auto[0]	auto[0]	auto[0]	2874918	1			T22	137		T23	235		T24	15013
all_values[18]	auto[0]	auto[0]	auto[1]	5582537	1			T24	123340		T25	28329		T1	42948
all_values[18]	auto[0]	auto[1]	auto[0]	595520	1			T24	13661		T25	3139		T1	5121
all_values[18]	auto[0]	auto[1]	auto[1]	5551367	1			T24	120842		T25	26950		T1	41195
all_values[18]	auto[1]	auto[0]	auto[1]	80134	1			T24	1480		T25	329		T1	902
all_values[18]	auto[1]	auto[1]	auto[1]	79212	1			T24	1451		T25	345		T1	918
all_values[19]	auto[0]	auto[0]	auto[0]	2870868	1			T22	137		T23	235		T24	13411
all_values[19]	auto[0]	auto[0]	auto[1]	5569416	1			T24	127162		T25	27746		T1	44707
all_values[19]	auto[0]	auto[1]	auto[0]	596310	1			T24	12677		T25	2968		T1	4176
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all_values[30]	auto[0]	auto[1]	auto[1]	5566655	1			T24	120530		T25	27028		T1	40111
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all_values[31]	auto[0]	auto[0]	auto[1]	5531144	1			T24	124193		T25	29384		T1	42903
all_values[31]	auto[0]	auto[1]	auto[0]	603504	1			T24	12968		T25	3353		T1	4721
all_values[31]	auto[0]	auto[1]	auto[1]	5587503	1			T24	121964		T25	25389		T1	41479
all_values[31]	auto[1]	auto[0]	auto[1]	80161	1			T24	1380		T25	374		T1	948
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User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal