Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[1]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[2]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[3]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[4]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[5]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[6]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[7]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[8]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[9]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[10]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[11]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[12]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[13]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[14]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[15]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[16]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[17]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[18]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[19]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[20]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[21]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[22]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[23]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[24]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[25]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[26]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[27]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[28]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[29]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[30]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[31]	14519005	1			T22	268		T23	317		T24	262282

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

276152689

1

T22

1902

T23

6435

T24

537679

auto[1]

188455471

1

T22

6674

T23

3709

T24

301622

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

373857909

1

T22

6906

T23

7521

T24

672094

auto[1]

90750251

1

T22

1670

T23

2623

T24

167208

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

347170391

1

T22

4516

T23

7525

T24

622371

auto[1]

117437769

1

T22

4060

T23

2619

T24

216931

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5398124	1			T22	17		T23	127		T24	102077
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4024584	1			T22	130		T23	72		T24	65002
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1424646	1			T22	29		T23	42		T24	25465
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1799502	1			T22	5		T23	42		T24	40082
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	455128	1			T22	69		T24	3023		T25	10816
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1417021	1			T22	18		T23	34		T24	26633
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5411457	1			T22	11		T23	129		T24	102845
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4014340	1			T22	106		T23	64		T24	65430
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1421024	1			T22	11		T23	48		T24	25767
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1798661	1			T22	19		T23	40		T24	39188
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	456693	1			T22	82		T24	2876		T25	10550
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1416830	1			T22	39		T23	36		T24	26176
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5411025	1			T22	8		T23	121		T24	103222
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4009947	1			T22	72		T23	65		T24	65134
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1425380	1			T22	13		T23	32		T24	26261
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1798557	1			T22	17		T23	50		T24	39266
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	459136	1			T22	114		T24	2717		T25	10681
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1414960	1			T22	44		T23	49		T24	25682
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5407027	1			T22	21		T23	111		T24	103285
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4015387	1			T22	88		T23	71		T24	65258
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1425852	1			T22	32		T23	36		T24	25855
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1797670	1			T22	17		T23	46		T24	38889
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	456630	1			T22	78		T24	2773		T25	10378
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1416439	1			T22	32		T23	53		T24	26222
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5401478	1			T22	26		T23	117		T24	102172
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4015836	1			T22	105		T23	80		T24	65708
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1429448	1			T22	31		T23	40		T24	25765
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1800906	1			T22	13		T23	44		T24	39496
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	459447	1			T22	89		T24	2758		T25	10929
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1411890	1			T22	4		T23	36		T24	26383
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5397200	1			T22	10		T23	111		T24	102296
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4027295	1			T22	120		T23	78		T24	65092
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1430016	1			T22	19		T23	36		T24	26448
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1791878	1			T22	14		T23	40		T24	39318
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	456673	1			T22	86		T24	2859		T25	10745
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1415943	1			T22	19		T23	52		T24	26269
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5405847	1			T22	15		T23	106		T24	103263
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4015414	1			T22	79		T23	78		T24	65458
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1425855	1			T22	20		T23	61		T24	26278
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1798697	1			T22	28		T23	28		T24	39354
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	456645	1			T22	81		T24	2630		T25	10835
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1416547	1			T22	45		T23	44		T24	25299
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5407338	1			T22	2		T23	115		T24	101695
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4012532	1			T22	39		T23	81		T24	65779
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1428519	1			T22	25		T23	34		T24	26520
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1799108	1			T22	23		T23	49		T24	39256
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	455379	1			T22	147		T24	2871		T25	10215
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1416129	1			T22	32		T23	38		T24	26161
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5398446	1			T22	22		T23	123		T24	103430
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4025704	1			T22	97		T23	76		T24	65535
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1426093	1			T22	26		T23	46		T24	26163
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1797354	1			T22	6		T23	38		T24	38276
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	456949	1			T22	95		T24	2722		T25	10338
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1414459	1			T22	22		T23	34		T24	26156
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5392230	1			T22	23		T23	92		T24	103665
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4022737	1			T22	80		T23	82		T24	65511
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1427350	1			T22	24		T23	28		T24	25784
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1800771	1			T22	17		T23	51		T24	38692
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	457924	1			T22	106		T24	2590		T25	10254
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1417993	1			T22	18		T23	64		T24	26040
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5403740	1			T22	23		T23	109		T24	103385
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4016448	1			T22	88		T23	81		T24	65568
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1430583	1			T22	34		T23	43		T24	26242
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1798156	1			T22	7		T23	50		T24	39003
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	458744	1			T22	89		T24	2690		T25	10606
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1411334	1			T22	27		T23	34		T24	25394
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5404903	1			T22	16		T23	125		T24	102526
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4014619	1			T22	64		T23	73		T24	65314
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1426808	1			T22	14		T23	40		T24	25880
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1798879	1			T22	14		T23	38		T24	38815
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	457856	1			T22	144		T24	2798		T25	11373
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1415940	1			T22	16		T23	41		T24	26949
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5402617	1			T22	10		T23	131		T24	102119
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4014081	1			T22	121		T23	80		T24	65340
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1425418	1			T22	32		T23	22		T24	25721
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1804490	1			T22	21		T23	46		T24	40244
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	457136	1			T22	70		T24	2772		T25	11195
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1415263	1			T22	14		T23	38		T24	26086
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5398619	1			T22	9		T23	110		T24	102387
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4026526	1			T22	59		T23	77		T24	65598
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1424488	1			T22	30		T23	42		T24	26095
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1797779	1			T22	20		T23	30		T24	38682
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	458296	1			T22	109		T24	2689		T25	11212
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1413297	1			T22	41		T23	58		T24	26831
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5405341	1			T22	2		T23	129		T24	103374
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4014930	1			T22	74		T23	75		T24	65249
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1424572	1			T22	24		T23	54		T24	25933
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1800514	1			T22	31		T23	29		T24	38962
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	457294	1			T22	102		T24	2711		T25	10781
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1416354	1			T22	35		T23	30		T24	26053
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5401316	1			T22	27		T23	135		T24	102655
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4022331	1			T22	94		T23	79		T24	65465
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1430163	1			T22	43		T23	35		T24	25921
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1794631	1			T22	13		T23	34		T24	39949
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	456921	1			T22	82		T24	2750		T25	10770
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1413643	1			T22	9		T23	34		T24	25542
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5399038	1			T22	13		T23	110		T24	102363
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4024290	1			T22	87		T23	76		T24	65093
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1416572	1			T22	35		T23	52		T24	25645
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1806997	1			T22	24		T23	39		T24	40040
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	460088	1			T22	88		T24	2889		T25	10868
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1412020	1			T22	21		T23	40		T24	26252
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5401886	1			T22	12		T23	114		T24	102844
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4028377	1			T22	122		T23	68		T24	65497
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1424205	1			T22	18		T23	47		T24	26945
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1798570	1			T22	13		T23	18		T24	38482
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	459167	1			T22	84		T24	2619		T25	10622
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1406800	1			T22	19		T23	70		T24	25895
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5405524	1			T22	16		T23	126		T24	102538
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4024171	1			T22	127		T23	74		T24	65844
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1427298	1			T22	21		T23	30		T24	25788
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1799687	1			T22	15		T23	49		T24	39384
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	456038	1			T22	68		T24	2727		T25	10643
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1406287	1			T22	21		T23	38		T24	26001
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5401210	1			T22	16		T23	105		T24	103545
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4025464	1			T22	118		T23	86		T24	65763
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1413609	1			T22	24		T23	42		T24	26293
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1810869	1			T22	19		T23	38		T24	38406
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	459735	1			T22	61		T24	2706		T25	10332
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1408118	1			T22	30		T23	46		T24	25569
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5402908	1			T22	9		T23	133		T24	102332
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4020395	1			T22	79		T23	73		T24	65418
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1428929	1			T22	17		T23	32		T24	27053
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1803981	1			T22	27		T23	42		T24	38438
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	457710	1			T22	112		T24	2699		T25	10921
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1405082	1			T22	24		T23	37		T24	26342
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5410417	1			T22	12		T23	109		T24	103382
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4027709	1			T22	86		T23	92		T24	65404
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1419040	1			T22	35		T23	28		T24	26050
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1802394	1			T22	25		T23	40		T24	38604
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	457266	1			T22	82		T24	2690		T25	10623
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1402179	1			T22	28		T23	48		T24	26152
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5407484	1			T22	14		T23	116		T24	103064
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4019521	1			T22	115		T23	76		T24	65521
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1419154	1			T22	38		T23	42		T24	25940
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1799546	1			T22	13		T23	49		T24	39149
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	459162	1			T22	67		T24	2668		T25	11117
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1414138	1			T22	21		T23	34		T24	25940
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5404760	1			T22	9		T23	128		T24	103124
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4031301	1			T22	114		T23	72		T24	65476
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1424994	1			T22	15		T23	54		T24	26963
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1793737	1			T22	24		T23	32		T24	37711
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	457092	1			T22	80		T24	2708		T25	10573
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1407121	1			T22	26		T23	31		T24	26300
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5408710	1			T22	20		T23	114		T24	103260
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4017006	1			T22	132		T23	66		T24	65449
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1418558	1			T22	24		T23	30		T24	26434
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1808452	1			T22	7		T23	61		T24	38504
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	457481	1			T22	80		T24	2811		T25	11158
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1408798	1			T22	5		T23	46		T24	25824
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5422402	1			T22	9		T23	137		T24	103241
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4007050	1			T22	94		T23	69		T24	65560
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1424235	1			T22	43		T23	55		T24	26269
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1802665	1			T22	24		T23	30		T24	38679
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	458479	1			T22	69		T24	2701		T25	11051
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1404174	1			T22	29		T23	26		T24	25832
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5414038	1			T22	31		T23	132		T24	102663
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4013742	1			T22	125		T23	63		T24	65795
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1422090	1			T22	43		T23	42		T24	26770
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1800817	1			T22	10		T23	54		T24	38427
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	460434	1			T22	50		T24	2744		T25	11003
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1407884	1			T22	9		T23	26		T24	25883
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5401561	1			T22	17		T23	143		T24	102719
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4026051	1			T22	122		T23	65		T24	65499
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1420705	1			T22	30		T23	34		T24	25924
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1802870	1			T22	11		T23	32		T24	39427
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	460197	1			T22	70		T24	2790		T25	10424
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1407621	1			T22	18		T23	43		T24	25923
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5409498	1			T22	30		T23	112		T24	103471
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4017851	1			T22	114		T23	70		T24	65395
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1420175	1			T22	58		T23	43		T24	26809
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1802999	1			T22	9		T23	34		T24	38320
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	456505	1			T22	42		T24	2638		T25	10281
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1411977	1			T22	15		T23	58		T24	25649
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5406061	1			T22	9		T23	119		T24	103315
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4018335	1			T22	126		T23	77		T24	64998
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1422143	1			T22	34		T23	41		T24	26451
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1800107	1			T22	16		T23	44		T24	38435
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	458421	1			T22	40		T24	2803		T25	10609
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1413938	1			T22	43		T23	36		T24	26280
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5411597	1			T22	20		T23	129		T24	103245
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4014542	1			T22	114		T23	77		T24	65638
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1424076	1			T22	39		T23	35		T24	26164
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1805438	1			T22	8		T23	38		T24	38877
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	457839	1			T22	69		T24	2639		T25	10411
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1405513	1			T22	18		T23	38		T24	25719
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5406027	1			T22	3		T23	131		T24	101696
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4025733	1			T22	49		T23	65		T24	65716
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1424315	1			T22	13		T23	49		T24	26411
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1799865	1			T22	16		T23	36		T24	39237
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	454819	1			T22	153		T24	2585		T25	10381
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1408246	1			T22	34		T23	36		T24	26637

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal