Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[1]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[2]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[3]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[4]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[5]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[6]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[7]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[8]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[9]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[10]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[11]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[12]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[13]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[14]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[15]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[16]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[17]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[18]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[19]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[20]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[21]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[22]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[23]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[24]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[25]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[26]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[27]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[28]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[29]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[30]	14519005	1			T22	268		T23	317		T24	262282
bins_for_gpio_bits[31]	14519005	1			T22	268		T23	317		T24	262282

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

276152689

1

T22

1902

T23

6435

T24

537679

auto[1]

188455471

1

T22

6674

T23

3709

T24

301622

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

276144842

1

T22

1913

T23

6429

T24

537679

auto[1]

188463318

1

T22

6663

T23

3715

T24

301623

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8369227	1			T22	44		T23	200		T24	162905
bins_for_gpio_bits[0]	auto[0]	auto[1]	252818	1			T22	7		T23	11		T24	4719
bins_for_gpio_bits[0]	auto[1]	auto[0]	253045	1			T22	7		T23	11		T24	4719
bins_for_gpio_bits[0]	auto[1]	auto[1]	5643915	1			T22	210		T23	95		T24	89939
bins_for_gpio_bits[1]	auto[0]	auto[0]	8377356	1			T22	37		T23	209		T24	163155
bins_for_gpio_bits[1]	auto[0]	auto[1]	253541	1			T22	4		T23	8		T24	4644
bins_for_gpio_bits[1]	auto[1]	auto[0]	253786	1			T22	4		T23	8		T24	4645
bins_for_gpio_bits[1]	auto[1]	auto[1]	5634322	1			T22	223		T23	92		T24	89838
bins_for_gpio_bits[2]	auto[0]	auto[0]	8381865	1			T22	35		T23	191		T24	164171
bins_for_gpio_bits[2]	auto[0]	auto[1]	252848	1			T22	3		T23	11		T24	4578
bins_for_gpio_bits[2]	auto[1]	auto[0]	253097	1			T22	3		T23	12		T24	4578
bins_for_gpio_bits[2]	auto[1]	auto[1]	5631195	1			T22	227		T23	103		T24	88955
bins_for_gpio_bits[3]	auto[0]	auto[0]	8376843	1			T22	65		T23	180		T24	163460
bins_for_gpio_bits[3]	auto[0]	auto[1]	253430	1			T22	5		T23	12		T24	4569
bins_for_gpio_bits[3]	auto[1]	auto[0]	253706	1			T22	5		T23	13		T24	4569
bins_for_gpio_bits[3]	auto[1]	auto[1]	5635026	1			T22	193		T23	112		T24	89684
bins_for_gpio_bits[4]	auto[0]	auto[0]	8378108	1			T22	66		T23	191		T24	162682
bins_for_gpio_bits[4]	auto[0]	auto[1]	253492	1			T22	4		T23	10		T24	4751
bins_for_gpio_bits[4]	auto[1]	auto[0]	253724	1			T22	4		T23	10		T24	4751
bins_for_gpio_bits[4]	auto[1]	auto[1]	5633681	1			T22	194		T23	106		T24	90098
bins_for_gpio_bits[5]	auto[0]	auto[0]	8365486	1			T22	40		T23	176		T24	163422
bins_for_gpio_bits[5]	auto[0]	auto[1]	253364	1			T22	3		T23	11		T24	4640
bins_for_gpio_bits[5]	auto[1]	auto[0]	253608	1			T22	3		T23	11		T24	4640
bins_for_gpio_bits[5]	auto[1]	auto[1]	5646547	1			T22	222		T23	119		T24	89580
bins_for_gpio_bits[6]	auto[0]	auto[0]	8376351	1			T22	58		T23	186		T24	164306
bins_for_gpio_bits[6]	auto[0]	auto[1]	253831	1			T22	6		T23	9		T24	4589
bins_for_gpio_bits[6]	auto[1]	auto[0]	254048	1			T22	5		T23	9		T24	4589
bins_for_gpio_bits[6]	auto[1]	auto[1]	5634775	1			T22	199		T23	113		T24	88798
bins_for_gpio_bits[7]	auto[0]	auto[0]	8381437	1			T22	46		T23	188		T24	162763
bins_for_gpio_bits[7]	auto[0]	auto[1]	253251	1			T22	5		T23	10		T24	4708
bins_for_gpio_bits[7]	auto[1]	auto[0]	253528	1			T22	4		T23	10		T24	4708
bins_for_gpio_bits[7]	auto[1]	auto[1]	5630789	1			T22	213		T23	109		T24	90103
bins_for_gpio_bits[8]	auto[0]	auto[0]	8368052	1			T22	47		T23	199		T24	163334
bins_for_gpio_bits[8]	auto[0]	auto[1]	253582	1			T22	7		T23	8		T24	4535
bins_for_gpio_bits[8]	auto[1]	auto[0]	253841	1			T22	7		T23	8		T24	4535
bins_for_gpio_bits[8]	auto[1]	auto[1]	5643530	1			T22	207		T23	102		T24	89878
bins_for_gpio_bits[9]	auto[0]	auto[0]	8366533	1			T22	61		T23	159		T24	163486
bins_for_gpio_bits[9]	auto[0]	auto[1]	253610	1			T22	4		T23	12		T24	4655
bins_for_gpio_bits[9]	auto[1]	auto[0]	253818	1			T22	3		T23	12		T24	4655
bins_for_gpio_bits[9]	auto[1]	auto[1]	5645044	1			T22	200		T23	134		T24	89486
bins_for_gpio_bits[10]	auto[0]	auto[0]	8379452	1			T22	59		T23	190		T24	164049
bins_for_gpio_bits[10]	auto[0]	auto[1]	252736	1			T22	5		T23	12		T24	4581
bins_for_gpio_bits[10]	auto[1]	auto[0]	253027	1			T22	5		T23	12		T24	4581
bins_for_gpio_bits[10]	auto[1]	auto[1]	5633790	1			T22	199		T23	103		T24	89071
bins_for_gpio_bits[11]	auto[0]	auto[0]	8377058	1			T22	41		T23	191		T24	162487
bins_for_gpio_bits[11]	auto[0]	auto[1]	253271	1			T22	3		T23	11		T24	4733
bins_for_gpio_bits[11]	auto[1]	auto[0]	253532	1			T22	3		T23	12		T24	4734
bins_for_gpio_bits[11]	auto[1]	auto[1]	5635144	1			T22	221		T23	103		T24	90328
bins_for_gpio_bits[12]	auto[0]	auto[0]	8378691	1			T22	57		T23	190		T24	163444
bins_for_gpio_bits[12]	auto[0]	auto[1]	253602	1			T22	7		T23	9		T24	4640
bins_for_gpio_bits[12]	auto[1]	auto[0]	253834	1			T22	6		T23	9		T24	4640
bins_for_gpio_bits[12]	auto[1]	auto[1]	5632878	1			T22	198		T23	109		T24	89558
bins_for_gpio_bits[13]	auto[0]	auto[0]	8367883	1			T22	54		T23	170		T24	162422
bins_for_gpio_bits[13]	auto[0]	auto[1]	252742	1			T22	6		T23	12		T24	4741
bins_for_gpio_bits[13]	auto[1]	auto[0]	253003	1			T22	5		T23	12		T24	4742
bins_for_gpio_bits[13]	auto[1]	auto[1]	5645377	1			T22	203		T23	123		T24	90377
bins_for_gpio_bits[14]	auto[0]	auto[0]	8376812	1			T22	53		T23	202		T24	163714
bins_for_gpio_bits[14]	auto[0]	auto[1]	253389	1			T22	4		T23	10		T24	4555
bins_for_gpio_bits[14]	auto[1]	auto[0]	253615	1			T22	4		T23	10		T24	4555
bins_for_gpio_bits[14]	auto[1]	auto[1]	5635189	1			T22	207		T23	95		T24	89458
bins_for_gpio_bits[15]	auto[0]	auto[0]	8372556	1			T22	75		T23	196		T24	163892
bins_for_gpio_bits[15]	auto[0]	auto[1]	253334	1			T22	9		T23	8		T24	4633
bins_for_gpio_bits[15]	auto[1]	auto[0]	253554	1			T22	8		T23	8		T24	4633
bins_for_gpio_bits[15]	auto[1]	auto[1]	5639561	1			T22	176		T23	105		T24	89124
bins_for_gpio_bits[16]	auto[0]	auto[0]	8369463	1			T22	66		T23	190		T24	163373
bins_for_gpio_bits[16]	auto[0]	auto[1]	252913	1			T22	7		T23	11		T24	4675
bins_for_gpio_bits[16]	auto[1]	auto[0]	253144	1			T22	6		T23	11		T24	4675
bins_for_gpio_bits[16]	auto[1]	auto[1]	5643485	1			T22	189		T23	105		T24	89559
bins_for_gpio_bits[17]	auto[0]	auto[0]	8371306	1			T22	37		T23	168		T24	163578
bins_for_gpio_bits[17]	auto[0]	auto[1]	253135	1			T22	6		T23	11		T24	4692
bins_for_gpio_bits[17]	auto[1]	auto[0]	253355	1			T22	6		T23	11		T24	4693
bins_for_gpio_bits[17]	auto[1]	auto[1]	5641209	1			T22	219		T23	127		T24	89319
bins_for_gpio_bits[18]	auto[0]	auto[0]	8379164	1			T22	46		T23	197		T24	163108
bins_for_gpio_bits[18]	auto[0]	auto[1]	253087	1			T22	6		T23	8		T24	4602
bins_for_gpio_bits[18]	auto[1]	auto[0]	253345	1			T22	6		T23	8		T24	4602
bins_for_gpio_bits[18]	auto[1]	auto[1]	5633409	1			T22	210		T23	104		T24	89970
bins_for_gpio_bits[19]	auto[0]	auto[0]	8372586	1			T22	54		T23	175		T24	163633
bins_for_gpio_bits[19]	auto[0]	auto[1]	252865	1			T22	5		T23	10		T24	4611
bins_for_gpio_bits[19]	auto[1]	auto[0]	253102	1			T22	5		T23	10		T24	4611
bins_for_gpio_bits[19]	auto[1]	auto[1]	5640452	1			T22	204		T23	122		T24	89427
bins_for_gpio_bits[20]	auto[0]	auto[0]	8382595	1			T22	50		T23	197		T24	163165
bins_for_gpio_bits[20]	auto[0]	auto[1]	252956	1			T22	3		T23	9		T24	4658
bins_for_gpio_bits[20]	auto[1]	auto[0]	253223	1			T22	3		T23	10		T24	4658
bins_for_gpio_bits[20]	auto[1]	auto[1]	5630231	1			T22	212		T23	101		T24	89801
bins_for_gpio_bits[21]	auto[0]	auto[0]	8379200	1			T22	64		T23	167		T24	163437
bins_for_gpio_bits[21]	auto[0]	auto[1]	252379	1			T22	8		T23	10		T24	4599
bins_for_gpio_bits[21]	auto[1]	auto[0]	252651	1			T22	8		T23	10		T24	4599
bins_for_gpio_bits[21]	auto[1]	auto[1]	5634775	1			T22	188		T23	130		T24	89647
bins_for_gpio_bits[22]	auto[0]	auto[0]	8372381	1			T22	60		T23	201		T24	163577
bins_for_gpio_bits[22]	auto[0]	auto[1]	253532	1			T22	6		T23	6		T24	4576
bins_for_gpio_bits[22]	auto[1]	auto[0]	253803	1			T22	5		T23	6		T24	4576
bins_for_gpio_bits[22]	auto[1]	auto[1]	5639289	1			T22	197		T23	104		T24	89553
bins_for_gpio_bits[23]	auto[0]	auto[0]	8370439	1			T22	43		T23	204		T24	163039
bins_for_gpio_bits[23]	auto[0]	auto[1]	252844	1			T22	5		T23	9		T24	4759
bins_for_gpio_bits[23]	auto[1]	auto[0]	253052	1			T22	5		T23	10		T24	4759
bins_for_gpio_bits[23]	auto[1]	auto[1]	5642670	1			T22	215		T23	94		T24	89725
bins_for_gpio_bits[24]	auto[0]	auto[0]	8382642	1			T22	46		T23	194		T24	163602
bins_for_gpio_bits[24]	auto[0]	auto[1]	252857	1			T22	5		T23	11		T24	4596
bins_for_gpio_bits[24]	auto[1]	auto[0]	253078	1			T22	5		T23	11		T24	4596
bins_for_gpio_bits[24]	auto[1]	auto[1]	5630428	1			T22	212		T23	101		T24	89488
bins_for_gpio_bits[25]	auto[0]	auto[0]	8396549	1			T22	69		T23	213		T24	163590
bins_for_gpio_bits[25]	auto[0]	auto[1]	252486	1			T22	8		T23	9		T24	4599
bins_for_gpio_bits[25]	auto[1]	auto[0]	252753	1			T22	7		T23	9		T24	4599
bins_for_gpio_bits[25]	auto[1]	auto[1]	5617217	1			T22	184		T23	86		T24	89494
bins_for_gpio_bits[26]	auto[0]	auto[0]	8383878	1			T22	75		T23	219		T24	163185
bins_for_gpio_bits[26]	auto[0]	auto[1]	252817	1			T22	10		T23	9		T24	4674
bins_for_gpio_bits[26]	auto[1]	auto[0]	253067	1			T22	9		T23	9		T24	4675
bins_for_gpio_bits[26]	auto[1]	auto[1]	5629243	1			T22	174		T23	80		T24	89748
bins_for_gpio_bits[27]	auto[0]	auto[0]	8372174	1			T22	51		T23	198		T24	163423
bins_for_gpio_bits[27]	auto[0]	auto[1]	252709	1			T22	7		T23	10		T24	4646
bins_for_gpio_bits[27]	auto[1]	auto[0]	252962	1			T22	7		T23	11		T24	4647
bins_for_gpio_bits[27]	auto[1]	auto[1]	5641160	1			T22	203		T23	98		T24	89566
bins_for_gpio_bits[28]	auto[0]	auto[0]	8379092	1			T22	89		T23	174		T24	164018
bins_for_gpio_bits[28]	auto[0]	auto[1]	253313	1			T22	9		T23	15		T24	4582
bins_for_gpio_bits[28]	auto[1]	auto[0]	253580	1			T22	8		T23	15		T24	4582
bins_for_gpio_bits[28]	auto[1]	auto[1]	5633020	1			T22	162		T23	113		T24	89100
bins_for_gpio_bits[29]	auto[0]	auto[0]	8375004	1			T22	49		T23	198		T24	163511
bins_for_gpio_bits[29]	auto[0]	auto[1]	253091	1			T22	10		T23	6		T24	4690
bins_for_gpio_bits[29]	auto[1]	auto[0]	253307	1			T22	10		T23	6		T24	4690
bins_for_gpio_bits[29]	auto[1]	auto[1]	5637603	1			T22	199		T23	107		T24	89391
bins_for_gpio_bits[30]	auto[0]	auto[0]	8387678	1			T22	59		T23	193		T24	163680
bins_for_gpio_bits[30]	auto[0]	auto[1]	253174	1			T22	8		T23	9		T24	4606
bins_for_gpio_bits[30]	auto[1]	auto[0]	253433	1			T22	8		T23	9		T24	4606
bins_for_gpio_bits[30]	auto[1]	auto[1]	5624720	1			T22	193		T23	106		T24	89390
bins_for_gpio_bits[31]	auto[0]	auto[0]	8376764	1			T22	29		T23	205		T24	162675
bins_for_gpio_bits[31]	auto[0]	auto[1]	253218	1			T22	3		T23	11		T24	4669
bins_for_gpio_bits[31]	auto[1]	auto[0]	253443	1			T22	3		T23	11		T24	4669
bins_for_gpio_bits[31]	auto[1]	auto[1]	5635580	1			T22	233		T23	90		T24	90269