Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8519950 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
138211 |
| auto[1] |
6243738 |
1 |
|
|
T24 |
137576 |
|
T25 |
32045 |
|
T1 |
48846 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13954392 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256334 |
| auto[1] |
809296 |
1 |
|
|
T24 |
19453 |
|
T25 |
4279 |
|
T1 |
4870 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8500751 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
134339 |
| auto[1] |
6262937 |
1 |
|
|
T24 |
141448 |
|
T25 |
30551 |
|
T1 |
46543 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2723063 |
1 |
|
|
T24 |
62107 |
|
T25 |
12826 |
|
T1 |
20338 |
| auto[1] |
auto[0] |
auto[1] |
404225 |
1 |
|
|
T24 |
10029 |
|
T25 |
2067 |
|
T1 |
2368 |
| auto[1] |
auto[1] |
auto[0] |
2730578 |
1 |
|
|
T24 |
59888 |
|
T25 |
13446 |
|
T1 |
21335 |
| auto[1] |
auto[1] |
auto[1] |
405071 |
1 |
|
|
T24 |
9424 |
|
T25 |
2212 |
|
T1 |
2502 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8524141 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
141817 |
| auto[1] |
6239547 |
1 |
|
|
T24 |
133970 |
|
T25 |
31888 |
|
T1 |
46052 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13953620 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
257065 |
| auto[1] |
810068 |
1 |
|
|
T24 |
18722 |
|
T25 |
4228 |
|
T1 |
4794 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8496508 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
138517 |
| auto[1] |
6267180 |
1 |
|
|
T24 |
137270 |
|
T25 |
30850 |
|
T1 |
46232 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2733296 |
1 |
|
|
T24 |
62244 |
|
T25 |
12972 |
|
T1 |
19901 |
| auto[1] |
auto[0] |
auto[1] |
406102 |
1 |
|
|
T24 |
9826 |
|
T25 |
2084 |
|
T1 |
2291 |
| auto[1] |
auto[1] |
auto[0] |
2723816 |
1 |
|
|
T24 |
56304 |
|
T25 |
13650 |
|
T1 |
21537 |
| auto[1] |
auto[1] |
auto[1] |
403966 |
1 |
|
|
T24 |
8896 |
|
T25 |
2144 |
|
T1 |
2503 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8517080 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
137536 |
| auto[1] |
6246608 |
1 |
|
|
T24 |
138251 |
|
T25 |
31032 |
|
T1 |
49167 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13953221 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256799 |
| auto[1] |
810467 |
1 |
|
|
T24 |
18988 |
|
T25 |
4055 |
|
T1 |
4728 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8484441 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
136633 |
| auto[1] |
6279247 |
1 |
|
|
T24 |
139154 |
|
T25 |
30098 |
|
T1 |
46207 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2721416 |
1 |
|
|
T24 |
58449 |
|
T25 |
13372 |
|
T1 |
20367 |
| auto[1] |
auto[0] |
auto[1] |
401939 |
1 |
|
|
T24 |
9170 |
|
T25 |
2058 |
|
T1 |
2220 |
| auto[1] |
auto[1] |
auto[0] |
2747364 |
1 |
|
|
T24 |
61717 |
|
T25 |
12671 |
|
T1 |
21112 |
| auto[1] |
auto[1] |
auto[1] |
408528 |
1 |
|
|
T24 |
9818 |
|
T25 |
1997 |
|
T1 |
2508 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8519541 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
133324 |
| auto[1] |
6244147 |
1 |
|
|
T24 |
142463 |
|
T25 |
31536 |
|
T1 |
48736 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13959521 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256950 |
| auto[1] |
804167 |
1 |
|
|
T24 |
18837 |
|
T25 |
4388 |
|
T1 |
5019 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8526275 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
138595 |
| auto[1] |
6237413 |
1 |
|
|
T24 |
137192 |
|
T25 |
31987 |
|
T1 |
47366 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2713744 |
1 |
|
|
T24 |
56312 |
|
T25 |
13695 |
|
T1 |
20105 |
| auto[1] |
auto[0] |
auto[1] |
402385 |
1 |
|
|
T24 |
8941 |
|
T25 |
2103 |
|
T1 |
2362 |
| auto[1] |
auto[1] |
auto[0] |
2719502 |
1 |
|
|
T24 |
62043 |
|
T25 |
13904 |
|
T1 |
22242 |
| auto[1] |
auto[1] |
auto[1] |
401782 |
1 |
|
|
T24 |
9896 |
|
T25 |
2285 |
|
T1 |
2657 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8508577 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
138560 |
| auto[1] |
6255111 |
1 |
|
|
T24 |
137227 |
|
T25 |
31352 |
|
T1 |
48232 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13958576 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256876 |
| auto[1] |
805112 |
1 |
|
|
T24 |
18911 |
|
T25 |
4153 |
|
T1 |
5084 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8525428 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
137902 |
| auto[1] |
6238260 |
1 |
|
|
T24 |
137885 |
|
T25 |
31093 |
|
T1 |
47600 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2714558 |
1 |
|
|
T24 |
59767 |
|
T25 |
13803 |
|
T1 |
22253 |
| auto[1] |
auto[0] |
auto[1] |
402850 |
1 |
|
|
T24 |
9631 |
|
T25 |
2143 |
|
T1 |
2792 |
| auto[1] |
auto[1] |
auto[0] |
2718590 |
1 |
|
|
T24 |
59207 |
|
T25 |
13137 |
|
T1 |
20263 |
| auto[1] |
auto[1] |
auto[1] |
402262 |
1 |
|
|
T24 |
9280 |
|
T25 |
2010 |
|
T1 |
2292 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8539125 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
143931 |
| auto[1] |
6224563 |
1 |
|
|
T24 |
131856 |
|
T25 |
33228 |
|
T1 |
47050 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13957518 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
257476 |
| auto[1] |
806170 |
1 |
|
|
T24 |
18311 |
|
T25 |
4373 |
|
T1 |
5332 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8517174 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
142344 |
| auto[1] |
6246514 |
1 |
|
|
T24 |
133443 |
|
T25 |
31645 |
|
T1 |
49000 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2727825 |
1 |
|
|
T24 |
60280 |
|
T25 |
12464 |
|
T1 |
20883 |
| auto[1] |
auto[0] |
auto[1] |
405271 |
1 |
|
|
T24 |
9677 |
|
T25 |
1985 |
|
T1 |
2349 |
| auto[1] |
auto[1] |
auto[0] |
2712519 |
1 |
|
|
T24 |
54852 |
|
T25 |
14808 |
|
T1 |
22785 |
| auto[1] |
auto[1] |
auto[1] |
400899 |
1 |
|
|
T24 |
8634 |
|
T25 |
2388 |
|
T1 |
2983 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8516073 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
139207 |
| auto[1] |
6247615 |
1 |
|
|
T24 |
136580 |
|
T25 |
29892 |
|
T1 |
48533 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13957139 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256485 |
| auto[1] |
806549 |
1 |
|
|
T24 |
19302 |
|
T25 |
4121 |
|
T1 |
4867 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8516182 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
135153 |
| auto[1] |
6247506 |
1 |
|
|
T24 |
140634 |
|
T25 |
30081 |
|
T1 |
46445 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2714890 |
1 |
|
|
T24 |
61376 |
|
T25 |
13108 |
|
T1 |
20707 |
| auto[1] |
auto[0] |
auto[1] |
402429 |
1 |
|
|
T24 |
9822 |
|
T25 |
2151 |
|
T1 |
2376 |
| auto[1] |
auto[1] |
auto[0] |
2726067 |
1 |
|
|
T24 |
59956 |
|
T25 |
12852 |
|
T1 |
20871 |
| auto[1] |
auto[1] |
auto[1] |
404120 |
1 |
|
|
T24 |
9480 |
|
T25 |
1970 |
|
T1 |
2491 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8523257 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
138935 |
| auto[1] |
6240431 |
1 |
|
|
T24 |
136852 |
|
T25 |
32974 |
|
T1 |
46419 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13955576 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256436 |
| auto[1] |
808112 |
1 |
|
|
T24 |
19351 |
|
T25 |
3994 |
|
T1 |
5280 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8507875 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
136040 |
| auto[1] |
6255813 |
1 |
|
|
T24 |
139747 |
|
T25 |
28984 |
|
T1 |
49092 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2729619 |
1 |
|
|
T24 |
61778 |
|
T25 |
11462 |
|
T1 |
22155 |
| auto[1] |
auto[0] |
auto[1] |
404414 |
1 |
|
|
T24 |
10009 |
|
T25 |
1828 |
|
T1 |
2702 |
| auto[1] |
auto[1] |
auto[0] |
2718082 |
1 |
|
|
T24 |
58618 |
|
T25 |
13528 |
|
T1 |
21657 |
| auto[1] |
auto[1] |
auto[1] |
403698 |
1 |
|
|
T24 |
9342 |
|
T25 |
2166 |
|
T1 |
2578 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8522934 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
136279 |
| auto[1] |
6240754 |
1 |
|
|
T24 |
139508 |
|
T25 |
31260 |
|
T1 |
47943 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13959915 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
257031 |
| auto[1] |
803773 |
1 |
|
|
T24 |
18756 |
|
T25 |
4172 |
|
T1 |
4970 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8527813 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
138204 |
| auto[1] |
6235875 |
1 |
|
|
T24 |
137583 |
|
T25 |
30795 |
|
T1 |
46766 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2724015 |
1 |
|
|
T24 |
59217 |
|
T25 |
13190 |
|
T1 |
21143 |
| auto[1] |
auto[0] |
auto[1] |
402663 |
1 |
|
|
T24 |
9254 |
|
T25 |
2060 |
|
T1 |
2424 |
| auto[1] |
auto[1] |
auto[0] |
2708087 |
1 |
|
|
T24 |
59610 |
|
T25 |
13433 |
|
T1 |
20653 |
| auto[1] |
auto[1] |
auto[1] |
401110 |
1 |
|
|
T24 |
9502 |
|
T25 |
2112 |
|
T1 |
2546 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8538868 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
137056 |
| auto[1] |
6224820 |
1 |
|
|
T24 |
138731 |
|
T25 |
31726 |
|
T1 |
46587 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13954880 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256346 |
| auto[1] |
808808 |
1 |
|
|
T24 |
19441 |
|
T25 |
4178 |
|
T1 |
5188 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8505290 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
135337 |
| auto[1] |
6258398 |
1 |
|
|
T24 |
140450 |
|
T25 |
30160 |
|
T1 |
48311 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2739417 |
1 |
|
|
T24 |
58988 |
|
T25 |
12956 |
|
T1 |
23244 |
| auto[1] |
auto[0] |
auto[1] |
407380 |
1 |
|
|
T24 |
9314 |
|
T25 |
2103 |
|
T1 |
2899 |
| auto[1] |
auto[1] |
auto[0] |
2710173 |
1 |
|
|
T24 |
62021 |
|
T25 |
13026 |
|
T1 |
19879 |
| auto[1] |
auto[1] |
auto[1] |
401428 |
1 |
|
|
T24 |
10127 |
|
T25 |
2075 |
|
T1 |
2289 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8537589 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
139833 |
| auto[1] |
6226099 |
1 |
|
|
T24 |
135954 |
|
T25 |
30434 |
|
T1 |
47234 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13959648 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
257709 |
| auto[1] |
804040 |
1 |
|
|
T24 |
18078 |
|
T25 |
3928 |
|
T1 |
5524 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8538096 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
141804 |
| auto[1] |
6225592 |
1 |
|
|
T24 |
133983 |
|
T25 |
28917 |
|
T1 |
49537 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2724233 |
1 |
|
|
T24 |
56483 |
|
T25 |
13172 |
|
T1 |
22401 |
| auto[1] |
auto[0] |
auto[1] |
404290 |
1 |
|
|
T24 |
8918 |
|
T25 |
2163 |
|
T1 |
2833 |
| auto[1] |
auto[1] |
auto[0] |
2697319 |
1 |
|
|
T24 |
59422 |
|
T25 |
11817 |
|
T1 |
21612 |
| auto[1] |
auto[1] |
auto[1] |
399750 |
1 |
|
|
T24 |
9160 |
|
T25 |
1765 |
|
T1 |
2691 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8520647 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
142044 |
| auto[1] |
6243041 |
1 |
|
|
T24 |
133743 |
|
T25 |
30759 |
|
T1 |
45621 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13957637 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
255943 |
| auto[1] |
806051 |
1 |
|
|
T24 |
19844 |
|
T25 |
4400 |
|
T1 |
5237 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8531869 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
133673 |
| auto[1] |
6231819 |
1 |
|
|
T24 |
142114 |
|
T25 |
31733 |
|
T1 |
48591 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2717006 |
1 |
|
|
T24 |
61068 |
|
T25 |
13602 |
|
T1 |
22758 |
| auto[1] |
auto[0] |
auto[1] |
404114 |
1 |
|
|
T24 |
10010 |
|
T25 |
2180 |
|
T1 |
2838 |
| auto[1] |
auto[1] |
auto[0] |
2708762 |
1 |
|
|
T24 |
61202 |
|
T25 |
13731 |
|
T1 |
20596 |
| auto[1] |
auto[1] |
auto[1] |
401937 |
1 |
|
|
T24 |
9834 |
|
T25 |
2220 |
|
T1 |
2399 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8525347 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
142725 |
| auto[1] |
6238341 |
1 |
|
|
T24 |
133062 |
|
T25 |
30793 |
|
T1 |
47088 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13962457 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256750 |
| auto[1] |
801231 |
1 |
|
|
T24 |
19037 |
|
T25 |
4293 |
|
T1 |
5161 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8547094 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
136790 |
| auto[1] |
6216594 |
1 |
|
|
T24 |
138997 |
|
T25 |
31107 |
|
T1 |
48587 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2711478 |
1 |
|
|
T24 |
62407 |
|
T25 |
13901 |
|
T1 |
22216 |
| auto[1] |
auto[0] |
auto[1] |
402198 |
1 |
|
|
T24 |
10057 |
|
T25 |
2168 |
|
T1 |
2619 |
| auto[1] |
auto[1] |
auto[0] |
2703885 |
1 |
|
|
T24 |
57553 |
|
T25 |
12913 |
|
T1 |
21210 |
| auto[1] |
auto[1] |
auto[1] |
399033 |
1 |
|
|
T24 |
8980 |
|
T25 |
2125 |
|
T1 |
2542 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8530422 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
140236 |
| auto[1] |
6233266 |
1 |
|
|
T24 |
135551 |
|
T25 |
30623 |
|
T1 |
48103 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13960714 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
257011 |
| auto[1] |
802974 |
1 |
|
|
T24 |
18776 |
|
T25 |
4358 |
|
T1 |
4890 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8546914 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
138769 |
| auto[1] |
6216774 |
1 |
|
|
T24 |
137018 |
|
T25 |
31850 |
|
T1 |
46366 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2710947 |
1 |
|
|
T24 |
61967 |
|
T25 |
14156 |
|
T1 |
20788 |
| auto[1] |
auto[0] |
auto[1] |
402079 |
1 |
|
|
T24 |
10049 |
|
T25 |
2202 |
|
T1 |
2447 |
| auto[1] |
auto[1] |
auto[0] |
2702853 |
1 |
|
|
T24 |
56275 |
|
T25 |
13336 |
|
T1 |
20688 |
| auto[1] |
auto[1] |
auto[1] |
400895 |
1 |
|
|
T24 |
8727 |
|
T25 |
2156 |
|
T1 |
2443 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8543999 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
137729 |
| auto[1] |
6219689 |
1 |
|
|
T24 |
138058 |
|
T25 |
30459 |
|
T1 |
47283 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13962971 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256730 |
| auto[1] |
800717 |
1 |
|
|
T24 |
19057 |
|
T25 |
4390 |
|
T1 |
4836 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8564110 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
137696 |
| auto[1] |
6199578 |
1 |
|
|
T24 |
138091 |
|
T25 |
31655 |
|
T1 |
46304 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2706691 |
1 |
|
|
T24 |
60570 |
|
T25 |
13660 |
|
T1 |
20408 |
| auto[1] |
auto[0] |
auto[1] |
399476 |
1 |
|
|
T24 |
9820 |
|
T25 |
2147 |
|
T1 |
2394 |
| auto[1] |
auto[1] |
auto[0] |
2692170 |
1 |
|
|
T24 |
58464 |
|
T25 |
13605 |
|
T1 |
21060 |
| auto[1] |
auto[1] |
auto[1] |
401241 |
1 |
|
|
T24 |
9237 |
|
T25 |
2243 |
|
T1 |
2442 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8500902 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
132823 |
| auto[1] |
6262786 |
1 |
|
|
T24 |
142964 |
|
T25 |
29855 |
|
T1 |
48076 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13957131 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
257310 |
| auto[1] |
806557 |
1 |
|
|
T24 |
18477 |
|
T25 |
4351 |
|
T1 |
5375 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8519691 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
140474 |
| auto[1] |
6243997 |
1 |
|
|
T24 |
135313 |
|
T25 |
31316 |
|
T1 |
49561 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2717362 |
1 |
|
|
T24 |
57927 |
|
T25 |
14428 |
|
T1 |
22530 |
| auto[1] |
auto[0] |
auto[1] |
402171 |
1 |
|
|
T24 |
9225 |
|
T25 |
2333 |
|
T1 |
2780 |
| auto[1] |
auto[1] |
auto[0] |
2720078 |
1 |
|
|
T24 |
58909 |
|
T25 |
12537 |
|
T1 |
21656 |
| auto[1] |
auto[1] |
auto[1] |
404386 |
1 |
|
|
T24 |
9252 |
|
T25 |
2018 |
|
T1 |
2595 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8523973 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
139311 |
| auto[1] |
6239715 |
1 |
|
|
T24 |
136476 |
|
T25 |
32808 |
|
T1 |
48846 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13961023 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256649 |
| auto[1] |
802665 |
1 |
|
|
T24 |
19138 |
|
T25 |
4277 |
|
T1 |
4994 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8534346 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
137501 |
| auto[1] |
6229342 |
1 |
|
|
T24 |
138286 |
|
T25 |
30880 |
|
T1 |
47047 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2700956 |
1 |
|
|
T24 |
60525 |
|
T25 |
12506 |
|
T1 |
19645 |
| auto[1] |
auto[0] |
auto[1] |
399505 |
1 |
|
|
T24 |
9771 |
|
T25 |
1969 |
|
T1 |
2253 |
| auto[1] |
auto[1] |
auto[0] |
2725721 |
1 |
|
|
T24 |
58623 |
|
T25 |
14097 |
|
T1 |
22408 |
| auto[1] |
auto[1] |
auto[1] |
403160 |
1 |
|
|
T24 |
9367 |
|
T25 |
2308 |
|
T1 |
2741 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8497906 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
138111 |
| auto[1] |
6265782 |
1 |
|
|
T24 |
137676 |
|
T25 |
29662 |
|
T1 |
45271 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13956764 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
258016 |
| auto[1] |
806924 |
1 |
|
|
T24 |
17771 |
|
T25 |
4128 |
|
T1 |
4994 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8508234 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
144153 |
| auto[1] |
6255454 |
1 |
|
|
T24 |
131634 |
|
T25 |
30661 |
|
T1 |
47607 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2708169 |
1 |
|
|
T24 |
54455 |
|
T25 |
14307 |
|
T1 |
22539 |
| auto[1] |
auto[0] |
auto[1] |
400241 |
1 |
|
|
T24 |
8436 |
|
T25 |
2271 |
|
T1 |
2751 |
| auto[1] |
auto[1] |
auto[0] |
2740361 |
1 |
|
|
T24 |
59408 |
|
T25 |
12226 |
|
T1 |
20074 |
| auto[1] |
auto[1] |
auto[1] |
406683 |
1 |
|
|
T24 |
9335 |
|
T25 |
1857 |
|
T1 |
2243 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8541755 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
140607 |
| auto[1] |
6221933 |
1 |
|
|
T24 |
135180 |
|
T25 |
30233 |
|
T1 |
45211 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13958747 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256765 |
| auto[1] |
804941 |
1 |
|
|
T24 |
19022 |
|
T25 |
4157 |
|
T1 |
5152 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8539932 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
136353 |
| auto[1] |
6223756 |
1 |
|
|
T24 |
139434 |
|
T25 |
30354 |
|
T1 |
48158 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2715708 |
1 |
|
|
T24 |
61561 |
|
T25 |
13968 |
|
T1 |
21973 |
| auto[1] |
auto[0] |
auto[1] |
404190 |
1 |
|
|
T24 |
10008 |
|
T25 |
2267 |
|
T1 |
2708 |
| auto[1] |
auto[1] |
auto[0] |
2703107 |
1 |
|
|
T24 |
58851 |
|
T25 |
12229 |
|
T1 |
21033 |
| auto[1] |
auto[1] |
auto[1] |
400751 |
1 |
|
|
T24 |
9014 |
|
T25 |
1890 |
|
T1 |
2444 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8539018 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
135136 |
| auto[1] |
6224670 |
1 |
|
|
T24 |
140651 |
|
T25 |
30218 |
|
T1 |
48813 |